ARMAsmBackend.cpp revision e545ee20f1b6ea6c03919cc9bc1a4a059c2f03b6
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMMCTargetDesc.h" 11#include "MCTargetDesc/ARMBaseInfo.h" 12#include "MCTargetDesc/ARMFixupKinds.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "llvm/ADT/Twine.h" 15#include "llvm/MC/MCAssembler.h" 16#include "llvm/MC/MCDirectives.h" 17#include "llvm/MC/MCELFObjectWriter.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCMachObjectWriter.h" 20#include "llvm/MC/MCObjectWriter.h" 21#include "llvm/MC/MCSectionELF.h" 22#include "llvm/MC/MCSectionMachO.h" 23#include "llvm/MC/MCAsmBackend.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCValue.h" 26#include "llvm/Object/MachOFormat.h" 27#include "llvm/Support/ELF.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/raw_ostream.h" 30using namespace llvm; 31 32namespace { 33class ARMELFObjectWriter : public MCELFObjectTargetWriter { 34public: 35 ARMELFObjectWriter(uint8_t OSABI) 36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 37 /*HasRelocationAddend*/ false) {} 38}; 39 40class ARMAsmBackend : public MCAsmBackend { 41 const MCSubtargetInfo* STI; 42 bool isThumbMode; // Currently emitting Thumb code. 43public: 44 ARMAsmBackend(const Target &T, const StringRef TT) 45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 46 isThumbMode(TT.startswith("thumb")) {} 47 48 ~ARMAsmBackend() { 49 delete STI; 50 } 51 52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 53 54 bool hasNOP() const { 55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 56 } 57 58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 60// This table *must* be in the order that the fixup_* kinds are defined in 61// ARMFixupKinds.h. 62// 63// Name Offset (bits) Size (bits) Flags 64{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 65{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 67{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 68{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 69{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 74{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 76{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 77{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 78{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 79{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 81{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 82{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 83{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 84{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 85{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 86// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 87{ "fixup_arm_movt_hi16", 0, 20, 0 }, 88{ "fixup_arm_movw_lo16", 0, 20, 0 }, 89{ "fixup_t2_movt_hi16", 0, 20, 0 }, 90{ "fixup_t2_movw_lo16", 0, 20, 0 }, 91{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 94{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 95 }; 96 97 if (Kind < FirstTargetFixupKind) 98 return MCAsmBackend::getFixupKindInfo(Kind); 99 100 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 101 "Invalid kind!"); 102 return Infos[Kind - FirstTargetFixupKind]; 103 } 104 105 /// processFixupValue - Target hook to process the literal value of a fixup 106 /// if necessary. 107 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 108 const MCFixup &Fixup, const MCFragment *DF, 109 MCValue &Target, uint64_t &Value) { 110 // Some fixups to thumb function symbols need the low bit (thumb bit) 111 // twiddled. 112 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 113 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 114 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 115 if (const MCSymbolRefExpr *A = Target.getSymA()) { 116 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 117 if (Asm.isThumbFunc(&Sym)) 118 Value |= 1; 119 } 120 } 121 } 122 123 bool mayNeedRelaxation(const MCInst &Inst) const; 124 125 bool fixupNeedsRelaxation(const MCFixup &Fixup, 126 uint64_t Value, 127 const MCInstFragment *DF, 128 const MCAsmLayout &Layout) const; 129 130 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 131 132 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 133 134 void handleAssemblerFlag(MCAssemblerFlag Flag) { 135 switch (Flag) { 136 default: break; 137 case MCAF_Code16: 138 setIsThumb(true); 139 break; 140 case MCAF_Code32: 141 setIsThumb(false); 142 break; 143 } 144 } 145 146 unsigned getPointerSize() const { return 4; } 147 bool isThumb() const { return isThumbMode; } 148 void setIsThumb(bool it) { isThumbMode = it; } 149}; 150} // end anonymous namespace 151 152static unsigned getRelaxedOpcode(unsigned Op) { 153 switch (Op) { 154 default: return Op; 155 case ARM::tBcc: return ARM::t2Bcc; 156 case ARM::tLDRpciASM: return ARM::t2LDRpci; 157 case ARM::tADR: return ARM::t2ADR; 158 } 159} 160 161bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 162 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 163 return true; 164 return false; 165} 166 167bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 168 uint64_t Value, 169 const MCInstFragment *DF, 170 const MCAsmLayout &Layout) const { 171 switch ((unsigned)Fixup.getKind()) { 172 case ARM::fixup_arm_thumb_bcc: { 173 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 174 // low bit being an implied zero. There's an implied +4 offset for the 175 // branch, so we adjust the other way here to determine what's 176 // encodable. 177 // 178 // Relax if the value is too big for a (signed) i8. 179 int64_t Offset = int64_t(Value) - 4; 180 return Offset > 254 || Offset < -256; 181 } 182 case ARM::fixup_thumb_adr_pcrel_10: 183 case ARM::fixup_arm_thumb_cp: { 184 // If the immediate is negative, greater than 1020, or not a multiple 185 // of four, the wide version of the instruction must be used. 186 int64_t Offset = int64_t(Value) - 4; 187 return Offset > 1020 || Offset < 0 || Offset & 3; 188 } 189 } 190 llvm_unreachable("Unexpected fixup kind in fixupNeedsRelaxation()!"); 191} 192 193void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 194 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 195 196 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 197 if (RelaxedOp == Inst.getOpcode()) { 198 SmallString<256> Tmp; 199 raw_svector_ostream OS(Tmp); 200 Inst.dump_pretty(OS); 201 OS << "\n"; 202 report_fatal_error("unexpected instruction to relax: " + OS.str()); 203 } 204 205 // The instructions we're relaxing have (so far) the same operands. 206 // We just need to update to the proper opcode. 207 Res = Inst; 208 Res.setOpcode(RelaxedOp); 209} 210 211bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 212 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 213 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 214 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 215 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 216 if (isThumb()) { 217 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 218 : Thumb1_16bitNopEncoding; 219 uint64_t NumNops = Count / 2; 220 for (uint64_t i = 0; i != NumNops; ++i) 221 OW->Write16(nopEncoding); 222 if (Count & 1) 223 OW->Write8(0); 224 return true; 225 } 226 // ARM mode 227 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 228 : ARMv4_NopEncoding; 229 uint64_t NumNops = Count / 4; 230 for (uint64_t i = 0; i != NumNops; ++i) 231 OW->Write32(nopEncoding); 232 // FIXME: should this function return false when unable to write exactly 233 // 'Count' bytes with NOP encodings? 234 switch (Count % 4) { 235 default: break; // No leftover bytes to write 236 case 1: OW->Write8(0); break; 237 case 2: OW->Write16(0); break; 238 case 3: OW->Write16(0); OW->Write8(0xa0); break; 239 } 240 241 return true; 242} 243 244static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 245 switch (Kind) { 246 default: 247 llvm_unreachable("Unknown fixup kind!"); 248 case FK_Data_1: 249 case FK_Data_2: 250 case FK_Data_4: 251 return Value; 252 case ARM::fixup_arm_movt_hi16: 253 Value >>= 16; 254 // Fallthrough 255 case ARM::fixup_arm_movw_lo16: 256 case ARM::fixup_arm_movt_hi16_pcrel: 257 case ARM::fixup_arm_movw_lo16_pcrel: { 258 unsigned Hi4 = (Value & 0xF000) >> 12; 259 unsigned Lo12 = Value & 0x0FFF; 260 // inst{19-16} = Hi4; 261 // inst{11-0} = Lo12; 262 Value = (Hi4 << 16) | (Lo12); 263 return Value; 264 } 265 case ARM::fixup_t2_movt_hi16: 266 Value >>= 16; 267 // Fallthrough 268 case ARM::fixup_t2_movw_lo16: 269 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 270 // the other hi16 fixup? 271 case ARM::fixup_t2_movw_lo16_pcrel: { 272 unsigned Hi4 = (Value & 0xF000) >> 12; 273 unsigned i = (Value & 0x800) >> 11; 274 unsigned Mid3 = (Value & 0x700) >> 8; 275 unsigned Lo8 = Value & 0x0FF; 276 // inst{19-16} = Hi4; 277 // inst{26} = i; 278 // inst{14-12} = Mid3; 279 // inst{7-0} = Lo8; 280 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 281 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 282 swapped |= (Value & 0x0000FFFF) << 16; 283 return swapped; 284 } 285 case ARM::fixup_arm_ldst_pcrel_12: 286 // ARM PC-relative values are offset by 8. 287 Value -= 4; 288 // FALLTHROUGH 289 case ARM::fixup_t2_ldst_pcrel_12: { 290 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 291 Value -= 4; 292 bool isAdd = true; 293 if ((int64_t)Value < 0) { 294 Value = -Value; 295 isAdd = false; 296 } 297 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 298 Value |= isAdd << 23; 299 300 // Same addressing mode as fixup_arm_pcrel_10, 301 // but with 16-bit halfwords swapped. 302 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 303 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 304 swapped |= (Value & 0x0000FFFF) << 16; 305 return swapped; 306 } 307 308 return Value; 309 } 310 case ARM::fixup_thumb_adr_pcrel_10: 311 return ((Value - 4) >> 2) & 0xff; 312 case ARM::fixup_arm_adr_pcrel_12: { 313 // ARM PC-relative values are offset by 8. 314 Value -= 8; 315 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 316 if ((int64_t)Value < 0) { 317 Value = -Value; 318 opc = 2; // 0b0010 319 } 320 assert(ARM_AM::getSOImmVal(Value) != -1 && 321 "Out of range pc-relative fixup value!"); 322 // Encode the immediate and shift the opcode into place. 323 return ARM_AM::getSOImmVal(Value) | (opc << 21); 324 } 325 326 case ARM::fixup_t2_adr_pcrel_12: { 327 Value -= 4; 328 unsigned opc = 0; 329 if ((int64_t)Value < 0) { 330 Value = -Value; 331 opc = 5; 332 } 333 334 uint32_t out = (opc << 21); 335 out |= (Value & 0x800) << 15; 336 out |= (Value & 0x700) << 4; 337 out |= (Value & 0x0FF); 338 339 uint64_t swapped = (out & 0xFFFF0000) >> 16; 340 swapped |= (out & 0x0000FFFF) << 16; 341 return swapped; 342 } 343 344 case ARM::fixup_arm_condbranch: 345 case ARM::fixup_arm_uncondbranch: 346 // These values don't encode the low two bits since they're always zero. 347 // Offset by 8 just as above. 348 return 0xffffff & ((Value - 8) >> 2); 349 case ARM::fixup_t2_uncondbranch: { 350 Value = Value - 4; 351 Value >>= 1; // Low bit is not encoded. 352 353 uint32_t out = 0; 354 bool I = Value & 0x800000; 355 bool J1 = Value & 0x400000; 356 bool J2 = Value & 0x200000; 357 J1 ^= I; 358 J2 ^= I; 359 360 out |= I << 26; // S bit 361 out |= !J1 << 13; // J1 bit 362 out |= !J2 << 11; // J2 bit 363 out |= (Value & 0x1FF800) << 5; // imm6 field 364 out |= (Value & 0x0007FF); // imm11 field 365 366 uint64_t swapped = (out & 0xFFFF0000) >> 16; 367 swapped |= (out & 0x0000FFFF) << 16; 368 return swapped; 369 } 370 case ARM::fixup_t2_condbranch: { 371 Value = Value - 4; 372 Value >>= 1; // Low bit is not encoded. 373 374 uint64_t out = 0; 375 out |= (Value & 0x80000) << 7; // S bit 376 out |= (Value & 0x40000) >> 7; // J2 bit 377 out |= (Value & 0x20000) >> 4; // J1 bit 378 out |= (Value & 0x1F800) << 5; // imm6 field 379 out |= (Value & 0x007FF); // imm11 field 380 381 uint32_t swapped = (out & 0xFFFF0000) >> 16; 382 swapped |= (out & 0x0000FFFF) << 16; 383 return swapped; 384 } 385 case ARM::fixup_arm_thumb_bl: { 386 // The value doesn't encode the low bit (always zero) and is offset by 387 // four. The value is encoded into disjoint bit positions in the destination 388 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 389 // 390 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 391 // 392 // Note that the halfwords are stored high first, low second; so we need 393 // to transpose the fixup value here to map properly. 394 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 395 uint32_t Binary = 0; 396 Value = 0x3fffff & ((Value - 4) >> 1); 397 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 398 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 399 Binary |= isNeg << 10; // Sign bit. 400 return Binary; 401 } 402 case ARM::fixup_arm_thumb_blx: { 403 // The value doesn't encode the low two bits (always zero) and is offset by 404 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 405 // positions in the destination opcode. x = unchanged, I = immediate value 406 // bit, S = sign extension bit, 0 = zero. 407 // 408 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 409 // 410 // Note that the halfwords are stored high first, low second; so we need 411 // to transpose the fixup value here to map properly. 412 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 413 uint32_t Binary = 0; 414 Value = 0xfffff & ((Value - 2) >> 2); 415 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 416 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 417 Binary |= isNeg << 10; // Sign bit. 418 return Binary; 419 } 420 case ARM::fixup_arm_thumb_cp: 421 // Offset by 4, and don't encode the low two bits. Two bytes of that 422 // 'off by 4' is implicitly handled by the half-word ordering of the 423 // Thumb encoding, so we only need to adjust by 2 here. 424 return ((Value - 2) >> 2) & 0xff; 425 case ARM::fixup_arm_thumb_cb: { 426 // Offset by 4 and don't encode the lower bit, which is always 0. 427 uint32_t Binary = (Value - 4) >> 1; 428 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 429 } 430 case ARM::fixup_arm_thumb_br: 431 // Offset by 4 and don't encode the lower bit, which is always 0. 432 return ((Value - 4) >> 1) & 0x7ff; 433 case ARM::fixup_arm_thumb_bcc: 434 // Offset by 4 and don't encode the lower bit, which is always 0. 435 return ((Value - 4) >> 1) & 0xff; 436 case ARM::fixup_arm_pcrel_10_unscaled: { 437 Value = Value - 8; // ARM fixups offset by an additional word and don't 438 // need to adjust for the half-word ordering. 439 bool isAdd = true; 440 if ((int64_t)Value < 0) { 441 Value = -Value; 442 isAdd = false; 443 } 444 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 445 return Value | (isAdd << 23); 446 } 447 case ARM::fixup_arm_pcrel_10: 448 Value = Value - 4; // ARM fixups offset by an additional word and don't 449 // need to adjust for the half-word ordering. 450 // Fall through. 451 case ARM::fixup_t2_pcrel_10: { 452 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 453 Value = Value - 4; 454 bool isAdd = true; 455 if ((int64_t)Value < 0) { 456 Value = -Value; 457 isAdd = false; 458 } 459 // These values don't encode the low two bits since they're always zero. 460 Value >>= 2; 461 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 462 Value |= isAdd << 23; 463 464 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 465 // swapped. 466 if (Kind == ARM::fixup_t2_pcrel_10) { 467 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 468 swapped |= (Value & 0x0000FFFF) << 16; 469 return swapped; 470 } 471 472 return Value; 473 } 474 } 475} 476 477namespace { 478 479// FIXME: This should be in a separate file. 480// ELF is an ELF of course... 481class ELFARMAsmBackend : public ARMAsmBackend { 482public: 483 uint8_t OSABI; 484 ELFARMAsmBackend(const Target &T, const StringRef TT, 485 uint8_t _OSABI) 486 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 487 488 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 489 uint64_t Value) const; 490 491 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 492 return createARMELFObjectWriter(OS, OSABI); 493 } 494}; 495 496// FIXME: Raise this to share code between Darwin and ELF. 497void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 498 unsigned DataSize, uint64_t Value) const { 499 unsigned NumBytes = 4; // FIXME: 2 for Thumb 500 Value = adjustFixupValue(Fixup.getKind(), Value); 501 if (!Value) return; // Doesn't change encoding. 502 503 unsigned Offset = Fixup.getOffset(); 504 505 // For each byte of the fragment that the fixup touches, mask in the bits from 506 // the fixup value. The Value has been "split up" into the appropriate 507 // bitfields above. 508 for (unsigned i = 0; i != NumBytes; ++i) 509 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 510} 511 512// FIXME: This should be in a separate file. 513class DarwinARMAsmBackend : public ARMAsmBackend { 514public: 515 const object::mach::CPUSubtypeARM Subtype; 516 DarwinARMAsmBackend(const Target &T, const StringRef TT, 517 object::mach::CPUSubtypeARM st) 518 : ARMAsmBackend(T, TT), Subtype(st) { } 519 520 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 521 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 522 object::mach::CTM_ARM, 523 Subtype); 524 } 525 526 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 527 uint64_t Value) const; 528 529 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 530 return false; 531 } 532}; 533 534/// getFixupKindNumBytes - The number of bytes the fixup may change. 535static unsigned getFixupKindNumBytes(unsigned Kind) { 536 switch (Kind) { 537 default: 538 llvm_unreachable("Unknown fixup kind!"); 539 540 case FK_Data_1: 541 case ARM::fixup_arm_thumb_bcc: 542 case ARM::fixup_arm_thumb_cp: 543 case ARM::fixup_thumb_adr_pcrel_10: 544 return 1; 545 546 case FK_Data_2: 547 case ARM::fixup_arm_thumb_br: 548 case ARM::fixup_arm_thumb_cb: 549 return 2; 550 551 case ARM::fixup_arm_pcrel_10_unscaled: 552 case ARM::fixup_arm_ldst_pcrel_12: 553 case ARM::fixup_arm_pcrel_10: 554 case ARM::fixup_arm_adr_pcrel_12: 555 case ARM::fixup_arm_condbranch: 556 case ARM::fixup_arm_uncondbranch: 557 return 3; 558 559 case FK_Data_4: 560 case ARM::fixup_t2_ldst_pcrel_12: 561 case ARM::fixup_t2_condbranch: 562 case ARM::fixup_t2_uncondbranch: 563 case ARM::fixup_t2_pcrel_10: 564 case ARM::fixup_t2_adr_pcrel_12: 565 case ARM::fixup_arm_thumb_bl: 566 case ARM::fixup_arm_thumb_blx: 567 case ARM::fixup_arm_movt_hi16: 568 case ARM::fixup_arm_movw_lo16: 569 case ARM::fixup_arm_movt_hi16_pcrel: 570 case ARM::fixup_arm_movw_lo16_pcrel: 571 case ARM::fixup_t2_movt_hi16: 572 case ARM::fixup_t2_movw_lo16: 573 case ARM::fixup_t2_movt_hi16_pcrel: 574 case ARM::fixup_t2_movw_lo16_pcrel: 575 return 4; 576 } 577} 578 579void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 580 unsigned DataSize, uint64_t Value) const { 581 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 582 Value = adjustFixupValue(Fixup.getKind(), Value); 583 if (!Value) return; // Doesn't change encoding. 584 585 unsigned Offset = Fixup.getOffset(); 586 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 587 588 // For each byte of the fragment that the fixup touches, mask in the 589 // bits from the fixup value. 590 for (unsigned i = 0; i != NumBytes; ++i) 591 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 592} 593 594} // end anonymous namespace 595 596MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 597 Triple TheTriple(TT); 598 599 if (TheTriple.isOSDarwin()) { 600 if (TheTriple.getArchName() == "armv4t" || 601 TheTriple.getArchName() == "thumbv4t") 602 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 603 else if (TheTriple.getArchName() == "armv5e" || 604 TheTriple.getArchName() == "thumbv5e") 605 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 606 else if (TheTriple.getArchName() == "armv6" || 607 TheTriple.getArchName() == "thumbv6") 608 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 609 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 610 } 611 612 if (TheTriple.isOSWindows()) 613 assert(0 && "Windows not supported on ARM"); 614 615 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 616 return new ELFARMAsmBackend(T, TT, OSABI); 617} 618