1//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the PowerPC 32- and 64-bit
11// architectures.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Return Value Calling Convention
17//===----------------------------------------------------------------------===//
18
19// Return-value convention for PowerPC
20def RetCC_PPC : CallingConv<[
21  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
22  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
23  
24  CCIfType<[f32], CCAssignToReg<[F1]>>,
25  CCIfType<[f64], CCAssignToReg<[F1, F2]>>,
26  
27  // Vector types are always returned in V2.
28  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>>
29]>;
30
31
32//===----------------------------------------------------------------------===//
33// PowerPC Argument Calling Conventions
34//===----------------------------------------------------------------------===//
35/*
36def CC_PPC : CallingConv<[
37  // The first 8 integer arguments are passed in integer registers.
38  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
39  CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
40  
41  // Common sub-targets passes FP values in F1 - F13
42  CCIfType<[f32, f64], 
43           CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>,
44           
45  // The first 12 Vector arguments are passed in altivec registers.
46  CCIfType<[v16i8, v8i16, v4i32, v4f32],
47              CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10,V11,V12,V13]>>
48
49/*
50  // Integer/FP values get stored in stack slots that are 8 bytes in size and
51  // 8-byte aligned if there are no more registers to hold them.
52  CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
53  
54  // Vectors get 16-byte stack slots that are 16-byte aligned.
55  CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
56              CCAssignToStack<16, 16>>*/
57]>;
58
59*/
60
61//===----------------------------------------------------------------------===//
62// PowerPC System V Release 4 ABI
63//===----------------------------------------------------------------------===//
64
65def CC_PPC_SVR4_Common : CallingConv<[
66  // The ABI requires i64 to be passed in two adjacent registers with the first
67  // register having an odd register number.
68  CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignArgRegs">>>,
69
70  // The first 8 integer arguments are passed in integer registers.
71  CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
72
73  // Make sure the i64 words from a long double are either both passed in
74  // registers or both passed on the stack.
75  CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC_SVR4_Custom_AlignFPArgRegs">>>,
76  
77  // FP values are passed in F1 - F8.
78  CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
79
80  // Split arguments have an alignment of 8 bytes on the stack.
81  CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
82  
83  CCIfType<[i32], CCAssignToStack<4, 4>>,
84  
85  // Floats are stored in double precision format, thus they have the same
86  // alignment and size as doubles.
87  CCIfType<[f32,f64], CCAssignToStack<8, 8>>,  
88
89  // Vectors get 16-byte stack slots that are 16-byte aligned.
90  CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToStack<16, 16>>
91]>;
92
93// This calling convention puts vector arguments always on the stack. It is used
94// to assign vector arguments which belong to the variable portion of the
95// parameter list of a variable argument function.
96def CC_PPC_SVR4_VarArg : CallingConv<[
97  CCDelegateTo<CC_PPC_SVR4_Common>
98]>;
99
100// In contrast to CC_PPC_SVR4_VarArg, this calling convention first tries to put
101// vector arguments in vector registers before putting them on the stack.
102def CC_PPC_SVR4 : CallingConv<[
103  // The first 12 Vector arguments are passed in AltiVec registers.
104  CCIfType<[v16i8, v8i16, v4i32, v4f32],
105           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13]>>,
106           
107  CCDelegateTo<CC_PPC_SVR4_Common>
108]>;  
109
110// Helper "calling convention" to handle aggregate by value arguments.
111// Aggregate by value arguments are always placed in the local variable space
112// of the caller. This calling convention is only used to assign those stack
113// offsets in the callers stack frame.
114//
115// Still, the address of the aggregate copy in the callers stack frame is passed
116// in a GPR (or in the parameter list area if all GPRs are allocated) from the
117// caller to the callee. The location for the address argument is assigned by
118// the CC_PPC_SVR4 calling convention.
119//
120// The only purpose of CC_PPC_SVR4_Custom_Dummy is to skip arguments which are
121// not passed by value.
122 
123def CC_PPC_SVR4_ByVal : CallingConv<[
124  CCIfByVal<CCPassByVal<4, 4>>,
125  
126  CCCustom<"CC_PPC_SVR4_Custom_Dummy">
127]>;
128
129def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
130                                        R21, R22, R23, R24, R25, R26, R27, R28,
131                                        R29, R30, R31, F14, F15, F16, F17, F18,
132                                        F19, F20, F21, F22, F23, F24, F25, F26,
133                                        F27, F28, F29, F30, F31, CR2, CR3, CR4,
134                                        V20, V21, V22, V23, V24, V25, V26, V27,
135                                        V28, V29, V30, V31)>;
136
137def CSR_SVR432   : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
138                                        R21, R22, R23, R24, R25, R26, R27, R28,
139                                        R29, R30, R31, F14, F15, F16, F17, F18,
140                                        F19, F20, F21, F22, F23, F24, F25, F26,
141                                        F27, F28, F29, F30, F31, CR2, CR3, CR4,
142                                        V20, V21, V22, V23, V24, V25, V26, V27,
143                                        V28, V29, V30, V31)>;
144
145def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
146                                        X21, X22, X23, X24, X25, X26, X27, X28,
147                                        X29, X30, X31, F14, F15, F16, F17, F18,
148                                        F19, F20, F21, F22, F23, F24, F25, F26,
149                                        F27, F28, F29, F30, F31, CR2, CR3, CR4,
150                                        V20, V21, V22, V23, V24, V25, V26, V27,
151                                        V28, V29, V30, V31)>;
152
153def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
154                                        X21, X22, X23, X24, X25, X26, X27, X28,
155                                        X29, X30, X31, F14, F15, F16, F17, F18,
156                                        F19, F20, F21, F22, F23, F24, F25, F26,
157                                        F27, F28, F29, F30, F31, CR2, CR3, CR4,
158                                        V20, V21, V22, V23, V24, V25, V26, V27,
159                                        V28, V29, V30, V31)>;
160