1//===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler.
11// It contains code to translate the data produced by the decoder into
12//  MCInsts.
13// Documentation for the disassembler can be found in X86Disassembler.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86Disassembler.h"
18#include "X86DisassemblerDecoder.h"
19
20#include "llvm/MC/EDInstInfo.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCDisassembler.h"
24#include "llvm/MC/MCInst.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/MemoryObject.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31
32#define GET_REGINFO_ENUM
33#include "X86GenRegisterInfo.inc"
34#define GET_INSTRINFO_ENUM
35#include "X86GenInstrInfo.inc"
36#include "X86GenEDInfo.inc"
37
38using namespace llvm;
39using namespace llvm::X86Disassembler;
40
41void x86DisassemblerDebug(const char *file,
42                          unsigned line,
43                          const char *s) {
44  dbgs() << file << ":" << line << ": " << s;
45}
46
47const char *x86DisassemblerGetInstrName(unsigned Opcode, void *mii) {
48  const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
49  return MII->getName(Opcode);
50}
51
52#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
53
54namespace llvm {
55
56// Fill-ins to make the compiler happy.  These constants are never actually
57//   assigned; they are just filler to make an automatically-generated switch
58//   statement work.
59namespace X86 {
60  enum {
61    BX_SI = 500,
62    BX_DI = 501,
63    BP_SI = 502,
64    BP_DI = 503,
65    sib   = 504,
66    sib64 = 505
67  };
68}
69
70extern Target TheX86_32Target, TheX86_64Target;
71
72}
73
74static bool translateInstruction(MCInst &target,
75                                InternalInstruction &source,
76                                const MCDisassembler *Dis);
77
78X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI,
79                                               DisassemblerMode mode,
80                                               const MCInstrInfo *MII)
81  : MCDisassembler(STI), MII(MII), fMode(mode) {}
82
83X86GenericDisassembler::~X86GenericDisassembler() {
84  delete MII;
85}
86
87const EDInstInfo *X86GenericDisassembler::getEDInfo() const {
88  return instInfoX86;
89}
90
91/// regionReader - a callback function that wraps the readByte method from
92///   MemoryObject.
93///
94/// @param arg      - The generic callback parameter.  In this case, this should
95///                   be a pointer to a MemoryObject.
96/// @param byte     - A pointer to the byte to be read.
97/// @param address  - The address to be read.
98static int regionReader(void* arg, uint8_t* byte, uint64_t address) {
99  MemoryObject* region = static_cast<MemoryObject*>(arg);
100  return region->readByte(address, byte);
101}
102
103/// logger - a callback function that wraps the operator<< method from
104///   raw_ostream.
105///
106/// @param arg      - The generic callback parameter.  This should be a pointe
107///                   to a raw_ostream.
108/// @param log      - A string to be logged.  logger() adds a newline.
109static void logger(void* arg, const char* log) {
110  if (!arg)
111    return;
112
113  raw_ostream &vStream = *(static_cast<raw_ostream*>(arg));
114  vStream << log << "\n";
115}
116
117//
118// Public interface for the disassembler
119//
120
121MCDisassembler::DecodeStatus
122X86GenericDisassembler::getInstruction(MCInst &instr,
123                                       uint64_t &size,
124                                       const MemoryObject &region,
125                                       uint64_t address,
126                                       raw_ostream &vStream,
127                                       raw_ostream &cStream) const {
128  CommentStream = &cStream;
129
130  InternalInstruction internalInstr;
131
132  dlog_t loggerFn = logger;
133  if (&vStream == &nulls())
134    loggerFn = 0; // Disable logging completely if it's going to nulls().
135
136  int ret = decodeInstruction(&internalInstr,
137                              regionReader,
138                              (void*)&region,
139                              loggerFn,
140                              (void*)&vStream,
141                              (void*)MII,
142                              address,
143                              fMode);
144
145  if (ret) {
146    size = internalInstr.readerCursor - address;
147    return Fail;
148  }
149  else {
150    size = internalInstr.length;
151    return (!translateInstruction(instr, internalInstr, this)) ?
152            Success : Fail;
153  }
154}
155
156//
157// Private code that translates from struct InternalInstructions to MCInsts.
158//
159
160/// translateRegister - Translates an internal register to the appropriate LLVM
161///   register, and appends it as an operand to an MCInst.
162///
163/// @param mcInst     - The MCInst to append to.
164/// @param reg        - The Reg to append.
165static void translateRegister(MCInst &mcInst, Reg reg) {
166#define ENTRY(x) X86::x,
167  uint8_t llvmRegnums[] = {
168    ALL_REGS
169    0
170  };
171#undef ENTRY
172
173  uint8_t llvmRegnum = llvmRegnums[reg];
174  mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
175}
176
177/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
178/// immediate Value in the MCInst.
179///
180/// @param Value      - The immediate Value, has had any PC adjustment made by
181///                     the caller.
182/// @param isBranch   - If the instruction is a branch instruction
183/// @param Address    - The starting address of the instruction
184/// @param Offset     - The byte offset to this immediate in the instruction
185/// @param Width      - The byte width of this immediate in the instruction
186///
187/// If the getOpInfo() function was set when setupForSymbolicDisassembly() was
188/// called then that function is called to get any symbolic information for the
189/// immediate in the instruction using the Address, Offset and Width.  If that
190/// returns non-zero then the symbolic information it returns is used to create
191/// an MCExpr and that is added as an operand to the MCInst.  If getOpInfo()
192/// returns zero and isBranch is true then a symbol look up for immediate Value
193/// is done and if a symbol is found an MCExpr is created with that, else
194/// an MCExpr with the immediate Value is created.  This function returns true
195/// if it adds an operand to the MCInst and false otherwise.
196static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
197                                     uint64_t Address, uint64_t Offset,
198                                     uint64_t Width, MCInst &MI,
199                                     const MCDisassembler *Dis) {
200  LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
201  struct LLVMOpInfo1 SymbolicOp;
202  memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
203  SymbolicOp.Value = Value;
204  void *DisInfo = Dis->getDisInfoBlock();
205
206  if (!getOpInfo ||
207      !getOpInfo(DisInfo, Address, Offset, Width, 1, &SymbolicOp)) {
208    // Clear SymbolicOp.Value from above and also all other fields.
209    memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
210    LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
211    if (!SymbolLookUp)
212      return false;
213    uint64_t ReferenceType;
214    if (isBranch)
215       ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
216    else
217       ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
218    const char *ReferenceName;
219    const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
220                                    &ReferenceName);
221    if (Name) {
222      SymbolicOp.AddSymbol.Name = Name;
223      SymbolicOp.AddSymbol.Present = true;
224    }
225    // For branches always create an MCExpr so it gets printed as hex address.
226    else if (isBranch) {
227      SymbolicOp.Value = Value;
228    }
229    if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
230      (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
231    if (!Name && !isBranch)
232      return false;
233  }
234
235  MCContext *Ctx = Dis->getMCContext();
236  const MCExpr *Add = NULL;
237  if (SymbolicOp.AddSymbol.Present) {
238    if (SymbolicOp.AddSymbol.Name) {
239      StringRef Name(SymbolicOp.AddSymbol.Name);
240      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
241      Add = MCSymbolRefExpr::Create(Sym, *Ctx);
242    } else {
243      Add = MCConstantExpr::Create((int)SymbolicOp.AddSymbol.Value, *Ctx);
244    }
245  }
246
247  const MCExpr *Sub = NULL;
248  if (SymbolicOp.SubtractSymbol.Present) {
249      if (SymbolicOp.SubtractSymbol.Name) {
250      StringRef Name(SymbolicOp.SubtractSymbol.Name);
251      MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
252      Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
253    } else {
254      Sub = MCConstantExpr::Create((int)SymbolicOp.SubtractSymbol.Value, *Ctx);
255    }
256  }
257
258  const MCExpr *Off = NULL;
259  if (SymbolicOp.Value != 0)
260    Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
261
262  const MCExpr *Expr;
263  if (Sub) {
264    const MCExpr *LHS;
265    if (Add)
266      LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
267    else
268      LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
269    if (Off != 0)
270      Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
271    else
272      Expr = LHS;
273  } else if (Add) {
274    if (Off != 0)
275      Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
276    else
277      Expr = Add;
278  } else {
279    if (Off != 0)
280      Expr = Off;
281    else
282      Expr = MCConstantExpr::Create(0, *Ctx);
283  }
284
285  MI.addOperand(MCOperand::CreateExpr(Expr));
286
287  return true;
288}
289
290/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
291/// referenced by a load instruction with the base register that is the rip.
292/// These can often be addresses in a literal pool.  The Address of the
293/// instruction and its immediate Value are used to determine the address
294/// being referenced in the literal pool entry.  The SymbolLookUp call back will
295/// return a pointer to a literal 'C' string if the referenced address is an
296/// address into a section with 'C' string literals.
297static void tryAddingPcLoadReferenceComment(uint64_t Address, uint64_t Value,
298                                            const void *Decoder) {
299  const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
300  LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
301  if (SymbolLookUp) {
302    void *DisInfo = Dis->getDisInfoBlock();
303    uint64_t ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
304    const char *ReferenceName;
305    (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
306    if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
307      (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
308  }
309}
310
311/// translateImmediate  - Appends an immediate operand to an MCInst.
312///
313/// @param mcInst       - The MCInst to append to.
314/// @param immediate    - The immediate value to append.
315/// @param operand      - The operand, as stored in the descriptor table.
316/// @param insn         - The internal instruction.
317static void translateImmediate(MCInst &mcInst, uint64_t immediate,
318                               const OperandSpecifier &operand,
319                               InternalInstruction &insn,
320                               const MCDisassembler *Dis) {
321  // Sign-extend the immediate if necessary.
322
323  OperandType type = (OperandType)operand.type;
324
325  bool isBranch = false;
326  uint64_t pcrel = 0;
327  if (type == TYPE_RELv) {
328    isBranch = true;
329    pcrel = insn.startLocation +
330            insn.displacementOffset + insn.displacementSize;
331    switch (insn.displacementSize) {
332    default:
333      break;
334    case 1:
335      type = TYPE_MOFFS8;
336      break;
337    case 2:
338      type = TYPE_MOFFS16;
339      break;
340    case 4:
341      type = TYPE_MOFFS32;
342      break;
343    case 8:
344      type = TYPE_MOFFS64;
345      break;
346    }
347  }
348  // By default sign-extend all X86 immediates based on their encoding.
349  else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 ||
350           type == TYPE_IMM64) {
351    uint32_t Opcode = mcInst.getOpcode();
352    switch (operand.encoding) {
353    default:
354      break;
355    case ENCODING_IB:
356      // Special case those X86 instructions that use the imm8 as a set of
357      // bits, bit count, etc. and are not sign-extend.
358      if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri &&
359	  Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri &&
360	  Opcode != X86::DPPSrri && Opcode != X86::DPPDrri &&
361	  Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri &&
362	  Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri &&
363	  Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri &&
364	  Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri &&
365	  Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri &&
366	  Opcode != X86::VINSERTPSrr)
367	type = TYPE_MOFFS8;
368      break;
369    case ENCODING_IW:
370      type = TYPE_MOFFS16;
371      break;
372    case ENCODING_ID:
373      type = TYPE_MOFFS32;
374      break;
375    case ENCODING_IO:
376      type = TYPE_MOFFS64;
377      break;
378    }
379  }
380
381  switch (type) {
382  case TYPE_XMM128:
383    mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
384    return;
385  case TYPE_XMM256:
386    mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
387    return;
388  case TYPE_REL8:
389    isBranch = true;
390    pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
391    // fall through to sign extend the immediate if needed.
392  case TYPE_MOFFS8:
393    if(immediate & 0x80)
394      immediate |= ~(0xffull);
395    break;
396  case TYPE_MOFFS16:
397    if(immediate & 0x8000)
398      immediate |= ~(0xffffull);
399    break;
400  case TYPE_REL32:
401  case TYPE_REL64:
402    isBranch = true;
403    pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize;
404    // fall through to sign extend the immediate if needed.
405  case TYPE_MOFFS32:
406    if(immediate & 0x80000000)
407      immediate |= ~(0xffffffffull);
408    break;
409  case TYPE_MOFFS64:
410  default:
411    // operand is 64 bits wide.  Do nothing.
412    break;
413  }
414
415  if(!tryAddingSymbolicOperand(immediate + pcrel, isBranch, insn.startLocation,
416                               insn.immediateOffset, insn.immediateSize,
417                               mcInst, Dis))
418    mcInst.addOperand(MCOperand::CreateImm(immediate));
419}
420
421/// translateRMRegister - Translates a register stored in the R/M field of the
422///   ModR/M byte to its LLVM equivalent and appends it to an MCInst.
423/// @param mcInst       - The MCInst to append to.
424/// @param insn         - The internal instruction to extract the R/M field
425///                       from.
426/// @return             - 0 on success; -1 otherwise
427static bool translateRMRegister(MCInst &mcInst,
428                                InternalInstruction &insn) {
429  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
430    debug("A R/M register operand may not have a SIB byte");
431    return true;
432  }
433
434  switch (insn.eaBase) {
435  default:
436    debug("Unexpected EA base register");
437    return true;
438  case EA_BASE_NONE:
439    debug("EA_BASE_NONE for ModR/M base");
440    return true;
441#define ENTRY(x) case EA_BASE_##x:
442  ALL_EA_BASES
443#undef ENTRY
444    debug("A R/M register operand may not have a base; "
445          "the operand must be a register.");
446    return true;
447#define ENTRY(x)                                                      \
448  case EA_REG_##x:                                                    \
449    mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
450  ALL_REGS
451#undef ENTRY
452  }
453
454  return false;
455}
456
457/// translateRMMemory - Translates a memory operand stored in the Mod and R/M
458///   fields of an internal instruction (and possibly its SIB byte) to a memory
459///   operand in LLVM's format, and appends it to an MCInst.
460///
461/// @param mcInst       - The MCInst to append to.
462/// @param insn         - The instruction to extract Mod, R/M, and SIB fields
463///                       from.
464/// @return             - 0 on success; nonzero otherwise
465static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn,
466                              const MCDisassembler *Dis) {
467  // Addresses in an MCInst are represented as five operands:
468  //   1. basereg       (register)  The R/M base, or (if there is a SIB) the
469  //                                SIB base
470  //   2. scaleamount   (immediate) 1, or (if there is a SIB) the specified
471  //                                scale amount
472  //   3. indexreg      (register)  x86_registerNONE, or (if there is a SIB)
473  //                                the index (which is multiplied by the
474  //                                scale amount)
475  //   4. displacement  (immediate) 0, or the displacement if there is one
476  //   5. segmentreg    (register)  x86_registerNONE for now, but could be set
477  //                                if we have segment overrides
478
479  MCOperand baseReg;
480  MCOperand scaleAmount;
481  MCOperand indexReg;
482  MCOperand displacement;
483  MCOperand segmentReg;
484  uint64_t pcrel = 0;
485
486  if (insn.eaBase == EA_BASE_sib || insn.eaBase == EA_BASE_sib64) {
487    if (insn.sibBase != SIB_BASE_NONE) {
488      switch (insn.sibBase) {
489      default:
490        debug("Unexpected sibBase");
491        return true;
492#define ENTRY(x)                                          \
493      case SIB_BASE_##x:                                  \
494        baseReg = MCOperand::CreateReg(X86::x); break;
495      ALL_SIB_BASES
496#undef ENTRY
497      }
498    } else {
499      baseReg = MCOperand::CreateReg(0);
500    }
501
502    if (insn.sibIndex != SIB_INDEX_NONE) {
503      switch (insn.sibIndex) {
504      default:
505        debug("Unexpected sibIndex");
506        return true;
507#define ENTRY(x)                                          \
508      case SIB_INDEX_##x:                                 \
509        indexReg = MCOperand::CreateReg(X86::x); break;
510      EA_BASES_32BIT
511      EA_BASES_64BIT
512#undef ENTRY
513      }
514    } else {
515      indexReg = MCOperand::CreateReg(0);
516    }
517
518    scaleAmount = MCOperand::CreateImm(insn.sibScale);
519  } else {
520    switch (insn.eaBase) {
521    case EA_BASE_NONE:
522      if (insn.eaDisplacement == EA_DISP_NONE) {
523        debug("EA_BASE_NONE and EA_DISP_NONE for ModR/M base");
524        return true;
525      }
526      if (insn.mode == MODE_64BIT){
527        pcrel = insn.startLocation +
528                insn.displacementOffset + insn.displacementSize;
529        tryAddingPcLoadReferenceComment(insn.startLocation +
530                                        insn.displacementOffset,
531                                        insn.displacement + pcrel, Dis);
532        baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6
533      }
534      else
535        baseReg = MCOperand::CreateReg(0);
536
537      indexReg = MCOperand::CreateReg(0);
538      break;
539    case EA_BASE_BX_SI:
540      baseReg = MCOperand::CreateReg(X86::BX);
541      indexReg = MCOperand::CreateReg(X86::SI);
542      break;
543    case EA_BASE_BX_DI:
544      baseReg = MCOperand::CreateReg(X86::BX);
545      indexReg = MCOperand::CreateReg(X86::DI);
546      break;
547    case EA_BASE_BP_SI:
548      baseReg = MCOperand::CreateReg(X86::BP);
549      indexReg = MCOperand::CreateReg(X86::SI);
550      break;
551    case EA_BASE_BP_DI:
552      baseReg = MCOperand::CreateReg(X86::BP);
553      indexReg = MCOperand::CreateReg(X86::DI);
554      break;
555    default:
556      indexReg = MCOperand::CreateReg(0);
557      switch (insn.eaBase) {
558      default:
559        debug("Unexpected eaBase");
560        return true;
561        // Here, we will use the fill-ins defined above.  However,
562        //   BX_SI, BX_DI, BP_SI, and BP_DI are all handled above and
563        //   sib and sib64 were handled in the top-level if, so they're only
564        //   placeholders to keep the compiler happy.
565#define ENTRY(x)                                        \
566      case EA_BASE_##x:                                 \
567        baseReg = MCOperand::CreateReg(X86::x); break;
568      ALL_EA_BASES
569#undef ENTRY
570#define ENTRY(x) case EA_REG_##x:
571      ALL_REGS
572#undef ENTRY
573        debug("A R/M memory operand may not be a register; "
574              "the base field must be a base.");
575        return true;
576      }
577    }
578
579    scaleAmount = MCOperand::CreateImm(1);
580  }
581
582  displacement = MCOperand::CreateImm(insn.displacement);
583
584  static const uint8_t segmentRegnums[SEG_OVERRIDE_max] = {
585    0,        // SEG_OVERRIDE_NONE
586    X86::CS,
587    X86::SS,
588    X86::DS,
589    X86::ES,
590    X86::FS,
591    X86::GS
592  };
593
594  segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
595
596  mcInst.addOperand(baseReg);
597  mcInst.addOperand(scaleAmount);
598  mcInst.addOperand(indexReg);
599  if(!tryAddingSymbolicOperand(insn.displacement + pcrel, false,
600                               insn.startLocation, insn.displacementOffset,
601                               insn.displacementSize, mcInst, Dis))
602    mcInst.addOperand(displacement);
603  mcInst.addOperand(segmentReg);
604  return false;
605}
606
607/// translateRM - Translates an operand stored in the R/M (and possibly SIB)
608///   byte of an instruction to LLVM form, and appends it to an MCInst.
609///
610/// @param mcInst       - The MCInst to append to.
611/// @param operand      - The operand, as stored in the descriptor table.
612/// @param insn         - The instruction to extract Mod, R/M, and SIB fields
613///                       from.
614/// @return             - 0 on success; nonzero otherwise
615static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand,
616                        InternalInstruction &insn, const MCDisassembler *Dis) {
617  switch (operand.type) {
618  default:
619    debug("Unexpected type for a R/M operand");
620    return true;
621  case TYPE_R8:
622  case TYPE_R16:
623  case TYPE_R32:
624  case TYPE_R64:
625  case TYPE_Rv:
626  case TYPE_MM:
627  case TYPE_MM32:
628  case TYPE_MM64:
629  case TYPE_XMM:
630  case TYPE_XMM32:
631  case TYPE_XMM64:
632  case TYPE_XMM128:
633  case TYPE_XMM256:
634  case TYPE_DEBUGREG:
635  case TYPE_CONTROLREG:
636    return translateRMRegister(mcInst, insn);
637  case TYPE_M:
638  case TYPE_M8:
639  case TYPE_M16:
640  case TYPE_M32:
641  case TYPE_M64:
642  case TYPE_M128:
643  case TYPE_M256:
644  case TYPE_M512:
645  case TYPE_Mv:
646  case TYPE_M32FP:
647  case TYPE_M64FP:
648  case TYPE_M80FP:
649  case TYPE_M16INT:
650  case TYPE_M32INT:
651  case TYPE_M64INT:
652  case TYPE_M1616:
653  case TYPE_M1632:
654  case TYPE_M1664:
655  case TYPE_LEA:
656    return translateRMMemory(mcInst, insn, Dis);
657  }
658}
659
660/// translateFPRegister - Translates a stack position on the FPU stack to its
661///   LLVM form, and appends it to an MCInst.
662///
663/// @param mcInst       - The MCInst to append to.
664/// @param stackPos     - The stack position to translate.
665/// @return             - 0 on success; nonzero otherwise.
666static bool translateFPRegister(MCInst &mcInst,
667                               uint8_t stackPos) {
668  if (stackPos >= 8) {
669    debug("Invalid FP stack position");
670    return true;
671  }
672
673  mcInst.addOperand(MCOperand::CreateReg(X86::ST0 + stackPos));
674
675  return false;
676}
677
678/// translateOperand - Translates an operand stored in an internal instruction
679///   to LLVM's format and appends it to an MCInst.
680///
681/// @param mcInst       - The MCInst to append to.
682/// @param operand      - The operand, as stored in the descriptor table.
683/// @param insn         - The internal instruction.
684/// @return             - false on success; true otherwise.
685static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
686                             InternalInstruction &insn,
687                             const MCDisassembler *Dis) {
688  switch (operand.encoding) {
689  default:
690    debug("Unhandled operand encoding during translation");
691    return true;
692  case ENCODING_REG:
693    translateRegister(mcInst, insn.reg);
694    return false;
695  case ENCODING_RM:
696    return translateRM(mcInst, operand, insn, Dis);
697  case ENCODING_CB:
698  case ENCODING_CW:
699  case ENCODING_CD:
700  case ENCODING_CP:
701  case ENCODING_CO:
702  case ENCODING_CT:
703    debug("Translation of code offsets isn't supported.");
704    return true;
705  case ENCODING_IB:
706  case ENCODING_IW:
707  case ENCODING_ID:
708  case ENCODING_IO:
709  case ENCODING_Iv:
710  case ENCODING_Ia:
711    translateImmediate(mcInst,
712                       insn.immediates[insn.numImmediatesTranslated++],
713                       operand,
714                       insn,
715                       Dis);
716    return false;
717  case ENCODING_RB:
718  case ENCODING_RW:
719  case ENCODING_RD:
720  case ENCODING_RO:
721    translateRegister(mcInst, insn.opcodeRegister);
722    return false;
723  case ENCODING_I:
724    return translateFPRegister(mcInst, insn.opcodeModifier);
725  case ENCODING_Rv:
726    translateRegister(mcInst, insn.opcodeRegister);
727    return false;
728  case ENCODING_VVVV:
729    translateRegister(mcInst, insn.vvvv);
730    return false;
731  case ENCODING_DUP:
732    return translateOperand(mcInst,
733                            insn.spec->operands[operand.type - TYPE_DUP0],
734                            insn, Dis);
735  }
736}
737
738/// translateInstruction - Translates an internal instruction and all its
739///   operands to an MCInst.
740///
741/// @param mcInst       - The MCInst to populate with the instruction's data.
742/// @param insn         - The internal instruction.
743/// @return             - false on success; true otherwise.
744static bool translateInstruction(MCInst &mcInst,
745                                InternalInstruction &insn,
746                                const MCDisassembler *Dis) {
747  if (!insn.spec) {
748    debug("Instruction has no specification");
749    return true;
750  }
751
752  mcInst.setOpcode(insn.instructionID);
753
754  int index;
755
756  insn.numImmediatesTranslated = 0;
757
758  for (index = 0; index < X86_MAX_OPERANDS; ++index) {
759    if (insn.spec->operands[index].encoding != ENCODING_NONE) {
760      if (translateOperand(mcInst, insn.spec->operands[index], insn, Dis)) {
761        return true;
762      }
763    }
764  }
765
766  return false;
767}
768
769static MCDisassembler *createX86_32Disassembler(const Target &T,
770                                                const MCSubtargetInfo &STI) {
771  return new X86Disassembler::X86GenericDisassembler(STI, MODE_32BIT,
772                                                     T.createMCInstrInfo());
773}
774
775static MCDisassembler *createX86_64Disassembler(const Target &T,
776                                                const MCSubtargetInfo &STI) {
777  return new X86Disassembler::X86GenericDisassembler(STI, MODE_64BIT,
778                                                     T.createMCInstrInfo());
779}
780
781extern "C" void LLVMInitializeX86Disassembler() {
782  // Register the disassembler.
783  TargetRegistry::RegisterMCDisassembler(TheX86_32Target,
784                                         createX86_32Disassembler);
785  TargetRegistry::RegisterMCDisassembler(TheX86_64Target,
786                                         createX86_64Disassembler);
787}
788