X86DisassemblerDecoderCommon.h revision a21e2eae3def2fe39caed861dcb73c76c715569b
1/*===- X86DisassemblerDecoderCommon.h - Disassembler decoder -------*- C -*-==* 2 * 3 * The LLVM Compiler Infrastructure 4 * 5 * This file is distributed under the University of Illinois Open Source 6 * License. See LICENSE.TXT for details. 7 * 8 *===----------------------------------------------------------------------===* 9 * 10 * This file is part of the X86 Disassembler. 11 * It contains common definitions used by both the disassembler and the table 12 * generator. 13 * Documentation for the disassembler can be found in X86Disassembler.h. 14 * 15 *===----------------------------------------------------------------------===*/ 16 17/* 18 * This header file provides those definitions that need to be shared between 19 * the decoder and the table generator in a C-friendly manner. 20 */ 21 22#ifndef X86DISASSEMBLERDECODERCOMMON_H 23#define X86DISASSEMBLERDECODERCOMMON_H 24 25#include "llvm/Support/DataTypes.h" 26 27#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers 28#define CONTEXTS_SYM x86DisassemblerContexts 29#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes 30#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes 31#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes 32#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes 33 34#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers" 35#define CONTEXTS_STR "x86DisassemblerContexts" 36#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes" 37#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes" 38#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes" 39#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes" 40 41/* 42 * Attributes of an instruction that must be known before the opcode can be 43 * processed correctly. Most of these indicate the presence of particular 44 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context. 45 */ 46#define ATTRIBUTE_BITS \ 47 ENUM_ENTRY(ATTR_NONE, 0x00) \ 48 ENUM_ENTRY(ATTR_64BIT, 0x01) \ 49 ENUM_ENTRY(ATTR_XS, 0x02) \ 50 ENUM_ENTRY(ATTR_XD, 0x04) \ 51 ENUM_ENTRY(ATTR_REXW, 0x08) \ 52 ENUM_ENTRY(ATTR_OPSIZE, 0x10) \ 53 ENUM_ENTRY(ATTR_VEX, 0x20) \ 54 ENUM_ENTRY(ATTR_VEXL, 0x40) 55 56#define ENUM_ENTRY(n, v) n = v, 57enum attributeBits { 58 ATTRIBUTE_BITS 59 ATTR_max 60}; 61#undef ENUM_ENTRY 62 63/* 64 * Combinations of the above attributes that are relevant to instruction 65 * decode. Although other combinations are possible, they can be reduced to 66 * these without affecting the ultimately decoded instruction. 67 */ 68 69/* Class name Rank Rationale for rank assignment */ 70#define INSTRUCTION_CONTEXTS \ 71 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \ 72 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \ 73 "64-bit mode but no more") \ 74 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \ 75 "operands change width") \ 76 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \ 77 "but not the operands") \ 78 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \ 79 "but not the operands") \ 80 ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\ 81 "change width; overrides IC_OPSIZE") \ 82 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \ 83 ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \ 84 "secondary") \ 85 ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \ 86 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \ 87 "opcode") \ 88 ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \ 89 "IC_64BIT_REXW_XS") \ 90 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \ 91 "else because this changes most " \ 92 "operands' meaning") \ 93 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \ 94 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \ 95 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \ 96 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \ 97 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \ 98 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \ 99 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \ 100 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \ 101 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \ 102 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\ 103 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XS prefix")\ 104 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") 105 106 107#define ENUM_ENTRY(n, r, d) n, 108typedef enum { 109 INSTRUCTION_CONTEXTS 110 IC_max 111} InstructionContext; 112#undef ENUM_ENTRY 113 114/* 115 * Opcode types, which determine which decode table to use, both in the Intel 116 * manual and also for the decoder. 117 */ 118typedef enum { 119 ONEBYTE = 0, 120 TWOBYTE = 1, 121 THREEBYTE_38 = 2, 122 THREEBYTE_3A = 3 123} OpcodeType; 124 125/* 126 * The following structs are used for the hierarchical decode table. After 127 * determining the instruction's class (i.e., which IC_* constant applies to 128 * it), the decoder reads the opcode. Some instructions require specific 129 * values of the ModR/M byte, so the ModR/M byte indexes into the final table. 130 * 131 * If a ModR/M byte is not required, "required" is left unset, and the values 132 * for each instructionID are identical. 133 */ 134 135typedef uint16_t InstrUID; 136 137/* 138 * ModRMDecisionType - describes the type of ModR/M decision, allowing the 139 * consumer to determine the number of entries in it. 140 * 141 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded 142 * instruction is the same. 143 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode 144 * corresponds to one instruction; otherwise, it corresponds to 145 * a different instruction. 146 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond 147 * to a different instruction. 148 */ 149 150#define MODRMTYPES \ 151 ENUM_ENTRY(MODRM_ONEENTRY) \ 152 ENUM_ENTRY(MODRM_SPLITRM) \ 153 ENUM_ENTRY(MODRM_FULL) 154 155#define ENUM_ENTRY(n) n, 156typedef enum { 157 MODRMTYPES 158 MODRM_max 159} ModRMDecisionType; 160#undef ENUM_ENTRY 161 162/* 163 * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which 164 * instruction each possible value of the ModR/M byte corresponds to. Once 165 * this information is known, we have narrowed down to a single instruction. 166 */ 167struct ModRMDecision { 168 uint8_t modrm_type; 169 170 /* The macro below must be defined wherever this file is included. */ 171 INSTRUCTION_IDS 172}; 173 174/* 175 * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at 176 * given a particular opcode. 177 */ 178struct OpcodeDecision { 179 struct ModRMDecision modRMDecisions[256]; 180}; 181 182/* 183 * ContextDecision - Specifies which opcode->instruction tables to look at given 184 * a particular context (set of attributes). Since there are many possible 185 * contexts, the decoder first uses CONTEXTS_SYM to determine which context 186 * applies given a specific set of attributes. Hence there are only IC_max 187 * entries in this table, rather than 2^(ATTR_max). 188 */ 189struct ContextDecision { 190 struct OpcodeDecision opcodeDecisions[IC_max]; 191}; 192 193/* 194 * Physical encodings of instruction operands. 195 */ 196 197#define ENCODINGS \ 198 ENUM_ENTRY(ENCODING_NONE, "") \ 199 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \ 200 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \ 201 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ 202 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \ 203 ENUM_ENTRY(ENCODING_CW, "2-byte") \ 204 ENUM_ENTRY(ENCODING_CD, "4-byte") \ 205 ENUM_ENTRY(ENCODING_CP, "6-byte") \ 206 ENUM_ENTRY(ENCODING_CO, "8-byte") \ 207 ENUM_ENTRY(ENCODING_CT, "10-byte") \ 208 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ 209 ENUM_ENTRY(ENCODING_IW, "2-byte") \ 210 ENUM_ENTRY(ENCODING_ID, "4-byte") \ 211 ENUM_ENTRY(ENCODING_IO, "8-byte") \ 212 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \ 213 "the opcode byte") \ 214 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \ 215 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \ 216 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \ 217 ENUM_ENTRY(ENCODING_I, "Position on floating-point stack added to the " \ 218 "opcode byte") \ 219 \ 220 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \ 221 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \ 222 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \ 223 "opcode byte") \ 224 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \ 225 "in type") 226 227#define ENUM_ENTRY(n, d) n, 228 typedef enum { 229 ENCODINGS 230 ENCODING_max 231 } OperandEncoding; 232#undef ENUM_ENTRY 233 234/* 235 * Semantic interpretations of instruction operands. 236 */ 237 238#define TYPES \ 239 ENUM_ENTRY(TYPE_NONE, "") \ 240 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \ 241 ENUM_ENTRY(TYPE_REL16, "2-byte") \ 242 ENUM_ENTRY(TYPE_REL32, "4-byte") \ 243 ENUM_ENTRY(TYPE_REL64, "8-byte") \ 244 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ 245 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ 246 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ 247 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ 248 ENUM_ENTRY(TYPE_R16, "2-byte") \ 249 ENUM_ENTRY(TYPE_R32, "4-byte") \ 250 ENUM_ENTRY(TYPE_R64, "8-byte") \ 251 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ 252 ENUM_ENTRY(TYPE_IMM16, "2-byte") \ 253 ENUM_ENTRY(TYPE_IMM32, "4-byte") \ 254 ENUM_ENTRY(TYPE_IMM64, "8-byte") \ 255 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ 256 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ 257 ENUM_ENTRY(TYPE_RM16, "2-byte") \ 258 ENUM_ENTRY(TYPE_RM32, "4-byte") \ 259 ENUM_ENTRY(TYPE_RM64, "8-byte") \ 260 ENUM_ENTRY(TYPE_M, "Memory operand") \ 261 ENUM_ENTRY(TYPE_M8, "1-byte") \ 262 ENUM_ENTRY(TYPE_M16, "2-byte") \ 263 ENUM_ENTRY(TYPE_M32, "4-byte") \ 264 ENUM_ENTRY(TYPE_M64, "8-byte") \ 265 ENUM_ENTRY(TYPE_LEA, "Effective address") \ 266 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ 267 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ 268 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ 269 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ 270 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ 271 ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \ 272 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \ 273 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \ 274 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \ 275 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ 276 "base)") \ 277 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ 278 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ 279 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ 280 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \ 281 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \ 282 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ 283 ENUM_ENTRY(TYPE_M64FP, "64-bit") \ 284 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ 285 ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \ 286 "floating-point instructions") \ 287 ENUM_ENTRY(TYPE_M32INT, "4-byte") \ 288 ENUM_ENTRY(TYPE_M64INT, "8-byte") \ 289 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ 290 ENUM_ENTRY(TYPE_MM, "MMX register operand") \ 291 ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \ 292 ENUM_ENTRY(TYPE_MM64, "8-byte") \ 293 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \ 294 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ 295 ENUM_ENTRY(TYPE_XMM64, "8-byte") \ 296 ENUM_ENTRY(TYPE_XMM128, "16-byte") \ 297 ENUM_ENTRY(TYPE_XMM256, "32-byte") \ 298 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \ 299 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ 300 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ 301 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ 302 \ 303 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ 304 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ 305 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ 306 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ 307 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ 308 ENUM_ENTRY(TYPE_DUP1, "operand 1") \ 309 ENUM_ENTRY(TYPE_DUP2, "operand 2") \ 310 ENUM_ENTRY(TYPE_DUP3, "operand 3") \ 311 ENUM_ENTRY(TYPE_DUP4, "operand 4") \ 312 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") 313 314#define ENUM_ENTRY(n, d) n, 315typedef enum { 316 TYPES 317 TYPE_max 318} OperandType; 319#undef ENUM_ENTRY 320 321/* 322 * OperandSpecifier - The specification for how to extract and interpret one 323 * operand. 324 */ 325struct OperandSpecifier { 326 OperandEncoding encoding; 327 OperandType type; 328}; 329 330/* 331 * Indicates where the opcode modifier (if any) is to be found. Extended 332 * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte. 333 */ 334 335#define MODIFIER_TYPES \ 336 ENUM_ENTRY(MODIFIER_NONE) \ 337 ENUM_ENTRY(MODIFIER_OPCODE) \ 338 ENUM_ENTRY(MODIFIER_MODRM) 339 340#define ENUM_ENTRY(n) n, 341typedef enum { 342 MODIFIER_TYPES 343 MODIFIER_max 344} ModifierType; 345#undef ENUM_ENTRY 346 347#define X86_MAX_OPERANDS 5 348 349/* 350 * The specification for how to extract and interpret a full instruction and 351 * its operands. 352 */ 353struct InstructionSpecifier { 354 ModifierType modifierType; 355 uint8_t modifierBase; 356 struct OperandSpecifier operands[X86_MAX_OPERANDS]; 357 358 /* The macro below must be defined wherever this file is included. */ 359 INSTRUCTION_SPECIFIER_FIELDS 360}; 361 362/* 363 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode 364 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, 365 * respectively. 366 */ 367typedef enum { 368 MODE_16BIT, 369 MODE_32BIT, 370 MODE_64BIT 371} DisassemblerMode; 372 373#endif 374