| 769bbfd951018f9b36f3d2f0d70a23d81f2d3287 |
|
03-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 991271d9c454c9d599b63e4ebdd27b546e1782a1 |
|
04-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 930a1ebd929aa0ab4c2610e7f7a721c18dcfe052 |
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27-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| f41ab77847251f1ca88142b4e9cba597f9c094a8 |
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09-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
More tweaks to get the size of the X86 disassembler tables down.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| c8eb880a7fb0958a3a048a82c8558beec11f1209 |
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07-Nov-2011 |
Craig Topper <craig.topper@gmail.com> |
More AVX2 instructions and their intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 29480fd798dc6452948f63825ff41c66f09c2493 |
|
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 6744a17dcfb941d9fdd869b9f06e20660e18ff88 |
|
04-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| e1b4a1a07ec79440536e4535721f15de3893cd13 |
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01-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 4a8ac8de1ddfeaadb9ff13ce361bfc6435f18028 |
|
04-Apr-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Add support for the VIA PadLock instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| a21e2eae3def2fe39caed861dcb73c76c715569b |
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15-Mar-2011 |
Sean Callanan <scallanan@apple.com> |
X86 table-generator and disassembler support for the AVX
instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
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| 1f6efa3996dd1929fbc129203ce5009b620e6969 |
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29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Merge System into Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| b2ef4c1235c846c2503d0796541f4255ef1e13f5 |
|
29-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
|
06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 5edca8162623b742282f5f03b0872ac3469b5bed |
|
07-Apr-2010 |
Sean Callanan <scallanan@apple.com> |
Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter. Now, the
disassembler rejects instructions with out-of-range values
for that immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 7fb35a2fd83f5deadefcb230669b07e1d5b98137 |
|
22-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Fixes to the X86 disassembler:
Made LEA memory operands emit only 4 MCInst operands.
Made the scale operand equal 1 for instructions that have no
SIB byte.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|
| 8ed9f51663bc5533f36ca62e5668ae08e9a1313f |
|
19-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
|