1#if !defined(__QEMU_MIPS_EXEC_H__)
2#define __QEMU_MIPS_EXEC_H__
3
4//#define DEBUG_OP
5
6#include "config.h"
7#include "mips-defs.h"
8#include "dyngen-exec.h"
9#include "cpu-defs.h"
10
11register struct CPUMIPSState *env asm(AREG0);
12
13#include "cpu.h"
14#include "exec-all.h"
15
16#if !defined(CONFIG_USER_ONLY)
17#include "softmmu_exec.h"
18#endif /* !defined(CONFIG_USER_ONLY) */
19
20void dump_fpu(CPUState *env);
21void fpu_dump_state(CPUState *env, FILE *f,
22                    int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
23                    int flags);
24
25void cpu_mips_clock_init (CPUState *env);
26void cpu_mips_tlb_flush (CPUState *env, int flush_global);
27
28static inline void env_to_regs(void)
29{
30}
31
32static inline void regs_to_env(void)
33{
34}
35
36static inline int cpu_has_work(CPUState *env)
37{
38    return (env->interrupt_request &
39            (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER));
40}
41
42
43static inline int cpu_halted(CPUState *env)
44{
45    if (!env->halted)
46        return 0;
47    if (cpu_has_work(env)) {
48        env->halted = 0;
49        return 0;
50    }
51    return EXCP_HALTED;
52}
53
54static inline void compute_hflags(CPUState *env)
55{
56    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
57                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
58                     MIPS_HFLAG_UX);
59    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
60        !(env->CP0_Status & (1 << CP0St_ERL)) &&
61        !(env->hflags & MIPS_HFLAG_DM)) {
62        env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
63    }
64#if defined(TARGET_MIPS64)
65    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
66        (env->CP0_Status & (1 << CP0St_PX)) ||
67        (env->CP0_Status & (1 << CP0St_UX)))
68        env->hflags |= MIPS_HFLAG_64;
69    if (env->CP0_Status & (1 << CP0St_UX))
70        env->hflags |= MIPS_HFLAG_UX;
71#endif
72    if ((env->CP0_Status & (1 << CP0St_CU0)) ||
73        !(env->hflags & MIPS_HFLAG_KSU))
74        env->hflags |= MIPS_HFLAG_CP0;
75    if (env->CP0_Status & (1 << CP0St_CU1))
76        env->hflags |= MIPS_HFLAG_FPU;
77    if (env->CP0_Status & (1 << CP0St_FR))
78        env->hflags |= MIPS_HFLAG_F64;
79    if (env->insn_flags & ISA_MIPS32R2) {
80        if (env->active_fpu.fcr0 & (1 << FCR0_F64))
81            env->hflags |= MIPS_HFLAG_COP1X;
82    } else if (env->insn_flags & ISA_MIPS32) {
83        if (env->hflags & MIPS_HFLAG_64)
84            env->hflags |= MIPS_HFLAG_COP1X;
85    } else if (env->insn_flags & ISA_MIPS4) {
86        /* All supported MIPS IV CPUs use the XX (CU3) to enable
87           and disable the MIPS IV extensions to the MIPS III ISA.
88           Some other MIPS IV CPUs ignore the bit, so the check here
89           would be too restrictive for them.  */
90        if (env->CP0_Status & (1 << CP0St_CU3))
91            env->hflags |= MIPS_HFLAG_COP1X;
92    }
93}
94
95#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
96