/external/llvm/lib/CodeGen/ |
H A D | LiveDebugVariables.cpp | 350 void UserValue::print(raw_ostream &OS, const TargetMachine *TM) { argument 366 locations[i].print(OS, TM);
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H A D | MachineLICM.cpp | 63 const TargetMachine *TM; member in class:__anon7368::MachineLICM 323 TM = &MF.getTarget(); 324 TII = TM->getInstrInfo(); 325 TLI = TM->getTargetLowering(); 326 TRI = TM->getRegisterInfo(); 329 InstrItins = TM->getInstrItineraryData();
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H A D | MachineVerifier.cpp | 65 const TargetMachine *TM; member in struct:__anon7377::MachineVerifier 269 TM = &MF.getTarget(); 270 TII = TM->getInstrInfo(); 271 TRI = TM->getRegisterInfo(); 358 MI->print(*OS, TM); 366 MO->print(*OS, TM); 435 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
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H A D | RegisterCoalescer.cpp | 84 const TargetMachine* TM; member in class:__anon7393::RegisterCoalescer 1799 TM = &fn.getTarget(); 1800 TRI = TM->getRegisterInfo(); 1801 TII = TM->getInstrInfo(); 1958 if (MRI->recomputeRegClass(Reg, *TM)) {
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H A D | TwoAddressInstructionPass.cpp | 1384 const TargetMachine &TM = MF.getTarget(); local 1386 TII = TM.getInstrInfo(); 1387 TRI = TM.getRegisterInfo(); 1388 InstrItins = TM.getInstrItineraryData(); 1391 OptLevel = TM.getOptLevel();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 50 const TargetMachine &TM; member in class:__anon7401::SelectionDAGLegalize 206 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 1540 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3347 if (TM.getRelocationModel() == Reloc::PIC_) {
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H A D | SelectionDAGBuilder.h | 292 const TargetMachine &TM; member in class:llvm::SelectionDAGBuilder 337 : SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
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/external/llvm/lib/ExecutionEngine/ |
H A D | ExecutionEngine.cpp | 46 TargetMachine *TM) = 0; 52 TargetMachine *TM) = 0; 444 TargetMachine *TM = EB.selectTarget(); local 445 if (!TM || (ErrorStr && ErrorStr->length() > 0)) return 0; 447 return ExecutionEngine::JITCtor(M, ErrorStr, JMM, GVsWithCode, TM); 450 ExecutionEngine *EngineBuilder::create(TargetMachine *TM) { argument 451 OwningPtr<TargetMachine> TheTM(TM); // Take ownership. 475 if (!TM->getTarget().hasJIT()) {
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 147 const SPUTargetMachine &TM; member in class:__anon7571::SPUDAGToDAGISel 154 TM(tm), 211 SPU::LowerConstantPool(CPIdx, *CurDAG, TM); 1191 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) { argument 1192 return new SPUDAGToDAGISel(TM);
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H A D | SPUISelLowering.cpp | 91 SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) argument 92 : TargetLowering(TM, new TargetLoweringObjectFileELF()), 93 SPUTM(TM) { 1015 const TargetMachine &TM = DAG.getTarget(); local 1019 if (TM.getRelocationModel() == Reloc::Static) { 1036 SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) { argument 1037 return ::LowerConstantPool(Op, DAG, TM.getSubtargetImpl()); 1046 const TargetMachine &TM = DAG.getTarget(); local 1050 if (TM.getRelocationModel() == Reloc::Static) { 1071 const TargetMachine &TM local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 40 HexagonTargetMachine& TM; member in class:__anon7583::HexagonDAGToDAGISel 47 TM(targetmachine), 48 TII(static_cast<const HexagonInstrInfo*>(TM.getInstrInfo())) { 105 FunctionPass *llvm::createHexagonISelDag(HexagonTargetMachine &TM) { argument 106 return new HexagonDAGToDAGISel(TM); 1123 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 55 MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM) argument 56 : TargetLowering(TM, new MBlazeTargetObjectFile()) { 57 Subtarget = &TM.getSubtarget<MBlazeSubtarget>();
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 41 const PPCTargetMachine &TM; member in class:__anon7646::PPCDAGToDAGISel 47 : SelectionDAGISel(tm), TM(tm), 48 PPCLowering(*TM.getTargetLowering()), 49 PPCSubTarget(*TM.getSubtargetImpl()) {} 198 const TargetInstrInfo &TII = *TM.getInstrInfo(); 234 const TargetInstrInfo &TII = *TM.getInstrInfo(); 1082 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { argument 1083 return new PPCDAGToDAGISel(TM);
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H A D | PPCISelLowering.cpp | 58 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) { argument 59 if (TM.getSubtargetImpl()->isDarwin()) 65 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) argument 66 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) { 76 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4); 143 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { 229 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) { 230 if (TM 445 const TargetMachine &TM = getTargetMachine(); local 1138 GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV = 0) argument 4605 const TargetMachine &TM = getTargetMachine(); local 5250 const TargetMachine &TM = getTargetMachine(); local [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 688 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) argument 689 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 803 if (TM.getSubtarget<SparcSubtarget>().isV9())
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/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 101 TM(tm), MAI(tm.getMCAsmInfo()), 133 return TM.getTargetLowering()->getObjFileLowering(); 139 return *TM.getTargetData(); 164 .Initialize(OutContext, TM); 166 Mang = new Mangler(OutContext, *TM.getTargetData()); 288 SectionKind GVKind = TargetLoweringObjectFile::getKindForGlobal(GV, TM); 290 const TargetData *TD = TM.getTargetData(); 316 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM); 340 getObjFileLowering().SectionForGlobal(GV, GVKind, Mang, TM); 430 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM)); 500 const TargetMachine &TM = MF->getTarget(); local 1603 isRepeatedByteSequence(const Value *V, TargetMachine &TM) argument [all...] |
/external/llvm/lib/ExecutionEngine/JIT/ |
H A D | JITEmitter.cpp | 364 JITEmitter(JIT &jit, JITMemoryManager *JMM, TargetMachine &TM) argument 367 JITExceptionHandling(TM.Options.JITExceptionHandling) {
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/external/llvm/lib/Target/ARM/ |
H A D | ARMCodeEmitter.cpp | 52 TargetMachine &TM; member in class:__anon7517::ARMCodeEmitter 70 TD(tm.getTargetData()), TM(tm), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 377 FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, argument 379 return new ARMCodeEmitter(TM, JCE); 389 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 393 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 715 Reloc::Model RelocM = TM.getRelocationModel();
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H A D | ARMFastISel.cpp | 85 const TargetMachine &TM; member in class:__anon7522::ARMFastISel 97 TM(funcInfo.MF->getTarget()), 98 TII(*TM.getInstrInfo()), 99 TLI(*TM.getTargetLowering()) { 100 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 617 Reloc::Model RelocM = TM.getRelocationModel(); 1828 TM.Options.FloatABIType == FloatABI::Hard) 1851 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context); 1994 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); 2055 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLoc 2639 const TargetMachine &TM = funcInfo.MF->getTarget(); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 67 ARMBaseTargetMachine &TM; member in class:__anon7525::ARMDAGToDAGISel 77 : SelectionDAGISel(tm, OptLevel), TM(tm), 78 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())), 79 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 3396 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM, argument 3398 return new ARMDAGToDAGISel(TM, OptLevel);
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H A D | ARMLoadStoreOptimizer.cpp | 1424 const TargetMachine &TM = Fn.getTarget(); local 1426 TII = TM.getInstrInfo(); 1427 TRI = TM.getRegisterInfo(); 1428 STI = &TM.getSubtarget<ARMSubtarget>(); 1437 if (TM.getSubtarget<ARMSubtarget>().hasV5TOps())
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H A D | ARMBaseInstrInfo.cpp | 98 CreateTargetHazardRecognizer(const TargetMachine *TM, argument 101 const InstrItineraryData *II = TM->getInstrItineraryData(); 104 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 283 return static_cast<const X86TargetMachine &>(TM); 539 const TargetInstrInfo *TII = TM.getInstrInfo(); 568 CodeModel::Model M = TM.getCodeModel(); 619 CodeModel::Model M = TM.getCodeModel(); 715 if (TM.getCodeModel() == CodeModel::Small && 2536 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, argument 2538 return new X86DAGToDAGISel(TM, OptLevel);
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H A D | X86InstrInfo.cpp | 98 TM(tm), RI(tm, *this) { 1154 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 1563 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1680 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1686 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1700 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 2423 bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX(); 2435 TM.getSubtarget<X86Subtarget>().is64Bit()) { 2491 const TargetMachine &TM, 2493 bool HasAVX = TM 2488 getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const TargetMachine &TM, bool load) argument 2555 getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, TargetMachine &TM) argument 2563 getLoadRegOpcode(unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const TargetMachine &TM) argument 3812 const X86TargetMachine *TM = local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 87 MipsTargetLowering(MipsTargetMachine &TM) argument 88 : TargetLowering(TM, new MipsTargetObjectFile()), 89 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 104 if (!TM.Options.UseSoftFloat) { 150 if (!TM.Options.NoNaNsFPMath) { 219 if (!TM.Options.NoNaNsFPMath) {
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