1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50static cl::opt<bool>
51DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52  cl::desc("Enable / disable ARM integer abs transform"),
53  cl::init(false));
54
55//===--------------------------------------------------------------------===//
56/// ARMDAGToDAGISel - ARM specific code to select ARM machine
57/// instructions for SelectionDAG operations.
58///
59namespace {
60
61enum AddrMode2Type {
62  AM2_BASE, // Simple AM2 (+-imm12)
63  AM2_SHOP  // Shifter-op AM2
64};
65
66class ARMDAGToDAGISel : public SelectionDAGISel {
67  ARMBaseTargetMachine &TM;
68  const ARMBaseInstrInfo *TII;
69
70  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71  /// make the right decision when generating code for different targets.
72  const ARMSubtarget *Subtarget;
73
74public:
75  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76                           CodeGenOpt::Level OptLevel)
77    : SelectionDAGISel(tm, OptLevel), TM(tm),
78      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
80  }
81
82  virtual const char *getPassName() const {
83    return "ARM Instruction Selection";
84  }
85
86  /// getI32Imm - Return a target constant of type i32 with the specified
87  /// value.
88  inline SDValue getI32Imm(unsigned Imm) {
89    return CurDAG->getTargetConstant(Imm, MVT::i32);
90  }
91
92  SDNode *Select(SDNode *N);
93
94
95  bool hasNoVMLxHazardUse(SDNode *N) const;
96  bool isShifterOpProfitable(const SDValue &Shift,
97                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98  bool SelectRegShifterOperand(SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C,
100                               bool CheckProfitability = true);
101  bool SelectImmShifterOperand(SDValue N, SDValue &A,
102                               SDValue &B, bool CheckProfitability = true);
103  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B, SDValue &C) {
105    // Don't apply the profitability check
106    return SelectRegShifterOperand(N, A, B, C, false);
107  }
108  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109                                    SDValue &B) {
110    // Don't apply the profitability check
111    return SelectImmShifterOperand(N, A, B, false);
112  }
113
114  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116
117  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118                                      SDValue &Offset, SDValue &Opc);
119  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122  }
123
124  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125                           SDValue &Opc) {
126    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127  }
128
129  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130                       SDValue &Opc) {
131    SelectAddrMode2Worker(N, Base, Offset, Opc);
132//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133    // This always matches one way or another.
134    return true;
135  }
136
137  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138                             SDValue &Offset, SDValue &Opc);
139  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140                             SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144  bool SelectAddrMode3(SDValue N, SDValue &Base,
145                       SDValue &Offset, SDValue &Opc);
146  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147                             SDValue &Offset, SDValue &Opc);
148  bool SelectAddrMode5(SDValue N, SDValue &Base,
149                       SDValue &Offset);
150  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
152
153  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
154
155  // Thumb Addressing Modes:
156  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
158                             unsigned Scale);
159  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163                                SDValue &OffImm);
164  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165                                 SDValue &OffImm);
166  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167                                 SDValue &OffImm);
168  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169                                 SDValue &OffImm);
170  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
171
172  // Thumb 2 Addressing Modes:
173  bool SelectT2ShifterOperandReg(SDValue N,
174                                 SDValue &BaseReg, SDValue &Opc);
175  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177                            SDValue &OffImm);
178  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179                                 SDValue &OffImm);
180  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181                             SDValue &OffReg, SDValue &ShImm);
182
183  inline bool is_so_imm(unsigned Imm) const {
184    return ARM_AM::getSOImmVal(Imm) != -1;
185  }
186
187  inline bool is_so_imm_not(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(~Imm) != -1;
189  }
190
191  inline bool is_t2_so_imm(unsigned Imm) const {
192    return ARM_AM::getT2SOImmVal(Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm_not(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(~Imm) != -1;
197  }
198
199  // Include the pieces autogenerated from the target description.
200#include "ARMGenDAGISel.inc"
201
202private:
203  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
204  /// ARM.
205  SDNode *SelectARMIndexedLoad(SDNode *N);
206  SDNode *SelectT2IndexedLoad(SDNode *N);
207
208  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
209  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
210  /// loads of D registers and even subregs and odd subregs of Q registers.
211  /// For NumVecs <= 2, QOpcodes1 is not used.
212  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213                    unsigned *DOpcodes,
214                    unsigned *QOpcodes0, unsigned *QOpcodes1);
215
216  /// SelectVST - Select NEON store intrinsics.  NumVecs should
217  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
218  /// stores of D registers and even subregs and odd subregs of Q registers.
219  /// For NumVecs <= 2, QOpcodes1 is not used.
220  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221                    unsigned *DOpcodes,
222                    unsigned *QOpcodes0, unsigned *QOpcodes1);
223
224  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
226  /// load/store of D registers and Q registers.
227  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228                          bool isUpdating, unsigned NumVecs,
229                          unsigned *DOpcodes, unsigned *QOpcodes);
230
231  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
232  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
233  /// for loading D registers.  (Q registers are not supported.)
234  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235                       unsigned *Opcodes);
236
237  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
238  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
239  /// generated to force the table registers to be consecutive.
240  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
241
242  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
244
245  /// SelectCMOVOp - Select CMOV instructions for ARM.
246  SDNode *SelectCMOVOp(SDNode *N);
247  SDNode *SelectConditionalOp(SDNode *N);
248  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
249                              ARMCC::CondCodes CCVal, SDValue CCR,
250                              SDValue InFlag);
251  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
252                               ARMCC::CondCodes CCVal, SDValue CCR,
253                               SDValue InFlag);
254  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
255                              ARMCC::CondCodes CCVal, SDValue CCR,
256                              SDValue InFlag);
257  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
258                               ARMCC::CondCodes CCVal, SDValue CCR,
259                               SDValue InFlag);
260
261  // Select special operations if node forms integer ABS pattern
262  SDNode *SelectABSOp(SDNode *N);
263
264  SDNode *SelectConcatVector(SDNode *N);
265
266  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
267
268  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
269  /// inline asm expressions.
270  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
271                                            char ConstraintCode,
272                                            std::vector<SDValue> &OutOps);
273
274  // Form pairs of consecutive S, D, or Q registers.
275  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
276  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
277  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
278
279  // Form sequences of 4 consecutive S, D, or Q registers.
280  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
283
284  // Get the alignment operand for a NEON VLD or VST instruction.
285  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
286};
287}
288
289/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
290/// operand. If so Imm will receive the 32-bit value.
291static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
292  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
293    Imm = cast<ConstantSDNode>(N)->getZExtValue();
294    return true;
295  }
296  return false;
297}
298
299// isInt32Immediate - This method tests to see if a constant operand.
300// If so Imm will receive the 32 bit value.
301static bool isInt32Immediate(SDValue N, unsigned &Imm) {
302  return isInt32Immediate(N.getNode(), Imm);
303}
304
305// isOpcWithIntImmediate - This method tests to see if the node is a specific
306// opcode and that it has a immediate integer right operand.
307// If so Imm will receive the 32 bit value.
308static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
309  return N->getOpcode() == Opc &&
310         isInt32Immediate(N->getOperand(1).getNode(), Imm);
311}
312
313/// \brief Check whether a particular node is a constant value representable as
314/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
315///
316/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
317static bool isScaledConstantInRange(SDValue Node, int Scale,
318                                    int RangeMin, int RangeMax,
319                                    int &ScaledConstant) {
320  assert(Scale > 0 && "Invalid scale!");
321
322  // Check that this is a constant.
323  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
324  if (!C)
325    return false;
326
327  ScaledConstant = (int) C->getZExtValue();
328  if ((ScaledConstant % Scale) != 0)
329    return false;
330
331  ScaledConstant /= Scale;
332  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
333}
334
335/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
336/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
337/// least on current ARM implementations) which should be avoidded.
338bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
339  if (OptLevel == CodeGenOpt::None)
340    return true;
341
342  if (!CheckVMLxHazard)
343    return true;
344
345  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
346    return true;
347
348  if (!N->hasOneUse())
349    return false;
350
351  SDNode *Use = *N->use_begin();
352  if (Use->getOpcode() == ISD::CopyToReg)
353    return true;
354  if (Use->isMachineOpcode()) {
355    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
356    if (MCID.mayStore())
357      return true;
358    unsigned Opcode = MCID.getOpcode();
359    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
360      return true;
361    // vmlx feeding into another vmlx. We actually want to unfold
362    // the use later in the MLxExpansion pass. e.g.
363    // vmla
364    // vmla (stall 8 cycles)
365    //
366    // vmul (5 cycles)
367    // vadd (5 cycles)
368    // vmla
369    // This adds up to about 18 - 19 cycles.
370    //
371    // vmla
372    // vmul (stall 4 cycles)
373    // vadd adds up to about 14 cycles.
374    return TII->isFpMLxInstruction(Opcode);
375  }
376
377  return false;
378}
379
380bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
381                                            ARM_AM::ShiftOpc ShOpcVal,
382                                            unsigned ShAmt) {
383  if (!Subtarget->isCortexA9())
384    return true;
385  if (Shift.hasOneUse())
386    return true;
387  // R << 2 is free.
388  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
389}
390
391bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
392                                              SDValue &BaseReg,
393                                              SDValue &Opc,
394                                              bool CheckProfitability) {
395  if (DisableShifterOp)
396    return false;
397
398  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
399
400  // Don't match base register only case. That is matched to a separate
401  // lower complexity pattern with explicit register operand.
402  if (ShOpcVal == ARM_AM::no_shift) return false;
403
404  BaseReg = N.getOperand(0);
405  unsigned ShImmVal = 0;
406  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
407  if (!RHS) return false;
408  ShImmVal = RHS->getZExtValue() & 31;
409  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
410                                  MVT::i32);
411  return true;
412}
413
414bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
415                                              SDValue &BaseReg,
416                                              SDValue &ShReg,
417                                              SDValue &Opc,
418                                              bool CheckProfitability) {
419  if (DisableShifterOp)
420    return false;
421
422  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
423
424  // Don't match base register only case. That is matched to a separate
425  // lower complexity pattern with explicit register operand.
426  if (ShOpcVal == ARM_AM::no_shift) return false;
427
428  BaseReg = N.getOperand(0);
429  unsigned ShImmVal = 0;
430  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
431  if (RHS) return false;
432
433  ShReg = N.getOperand(1);
434  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
435    return false;
436  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
437                                  MVT::i32);
438  return true;
439}
440
441
442bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
443                                          SDValue &Base,
444                                          SDValue &OffImm) {
445  // Match simple R + imm12 operands.
446
447  // Base only.
448  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
449      !CurDAG->isBaseWithConstantOffset(N)) {
450    if (N.getOpcode() == ISD::FrameIndex) {
451      // Match frame index.
452      int FI = cast<FrameIndexSDNode>(N)->getIndex();
453      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
454      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
455      return true;
456    }
457
458    if (N.getOpcode() == ARMISD::Wrapper &&
459        !(Subtarget->useMovt() &&
460                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
461      Base = N.getOperand(0);
462    } else
463      Base = N;
464    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
465    return true;
466  }
467
468  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
469    int RHSC = (int)RHS->getZExtValue();
470    if (N.getOpcode() == ISD::SUB)
471      RHSC = -RHSC;
472
473    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
474      Base   = N.getOperand(0);
475      if (Base.getOpcode() == ISD::FrameIndex) {
476        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
477        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
478      }
479      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
480      return true;
481    }
482  }
483
484  // Base only.
485  Base = N;
486  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
487  return true;
488}
489
490
491
492bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
493                                      SDValue &Opc) {
494  if (N.getOpcode() == ISD::MUL &&
495      (!Subtarget->isCortexA9() || N.hasOneUse())) {
496    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
497      // X * [3,5,9] -> X + X * [2,4,8] etc.
498      int RHSC = (int)RHS->getZExtValue();
499      if (RHSC & 1) {
500        RHSC = RHSC & ~1;
501        ARM_AM::AddrOpc AddSub = ARM_AM::add;
502        if (RHSC < 0) {
503          AddSub = ARM_AM::sub;
504          RHSC = - RHSC;
505        }
506        if (isPowerOf2_32(RHSC)) {
507          unsigned ShAmt = Log2_32(RHSC);
508          Base = Offset = N.getOperand(0);
509          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
510                                                            ARM_AM::lsl),
511                                          MVT::i32);
512          return true;
513        }
514      }
515    }
516  }
517
518  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
519      // ISD::OR that is equivalent to an ISD::ADD.
520      !CurDAG->isBaseWithConstantOffset(N))
521    return false;
522
523  // Leave simple R +/- imm12 operands for LDRi12
524  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
525    int RHSC;
526    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
527                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
528      return false;
529  }
530
531  // Otherwise this is R +/- [possibly shifted] R.
532  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
533  ARM_AM::ShiftOpc ShOpcVal =
534    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
535  unsigned ShAmt = 0;
536
537  Base   = N.getOperand(0);
538  Offset = N.getOperand(1);
539
540  if (ShOpcVal != ARM_AM::no_shift) {
541    // Check to see if the RHS of the shift is a constant, if not, we can't fold
542    // it.
543    if (ConstantSDNode *Sh =
544           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
545      ShAmt = Sh->getZExtValue();
546      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
547        Offset = N.getOperand(1).getOperand(0);
548      else {
549        ShAmt = 0;
550        ShOpcVal = ARM_AM::no_shift;
551      }
552    } else {
553      ShOpcVal = ARM_AM::no_shift;
554    }
555  }
556
557  // Try matching (R shl C) + (R).
558  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
559      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
560    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
561    if (ShOpcVal != ARM_AM::no_shift) {
562      // Check to see if the RHS of the shift is a constant, if not, we can't
563      // fold it.
564      if (ConstantSDNode *Sh =
565          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
566        ShAmt = Sh->getZExtValue();
567        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
568          Offset = N.getOperand(0).getOperand(0);
569          Base = N.getOperand(1);
570        } else {
571          ShAmt = 0;
572          ShOpcVal = ARM_AM::no_shift;
573        }
574      } else {
575        ShOpcVal = ARM_AM::no_shift;
576      }
577    }
578  }
579
580  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
581                                  MVT::i32);
582  return true;
583}
584
585
586
587
588//-----
589
590AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
591                                                     SDValue &Base,
592                                                     SDValue &Offset,
593                                                     SDValue &Opc) {
594  if (N.getOpcode() == ISD::MUL &&
595      (!Subtarget->isCortexA9() || N.hasOneUse())) {
596    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
597      // X * [3,5,9] -> X + X * [2,4,8] etc.
598      int RHSC = (int)RHS->getZExtValue();
599      if (RHSC & 1) {
600        RHSC = RHSC & ~1;
601        ARM_AM::AddrOpc AddSub = ARM_AM::add;
602        if (RHSC < 0) {
603          AddSub = ARM_AM::sub;
604          RHSC = - RHSC;
605        }
606        if (isPowerOf2_32(RHSC)) {
607          unsigned ShAmt = Log2_32(RHSC);
608          Base = Offset = N.getOperand(0);
609          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
610                                                            ARM_AM::lsl),
611                                          MVT::i32);
612          return AM2_SHOP;
613        }
614      }
615    }
616  }
617
618  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
619      // ISD::OR that is equivalent to an ADD.
620      !CurDAG->isBaseWithConstantOffset(N)) {
621    Base = N;
622    if (N.getOpcode() == ISD::FrameIndex) {
623      int FI = cast<FrameIndexSDNode>(N)->getIndex();
624      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
625    } else if (N.getOpcode() == ARMISD::Wrapper &&
626               !(Subtarget->useMovt() &&
627                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
628      Base = N.getOperand(0);
629    }
630    Offset = CurDAG->getRegister(0, MVT::i32);
631    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
632                                                      ARM_AM::no_shift),
633                                    MVT::i32);
634    return AM2_BASE;
635  }
636
637  // Match simple R +/- imm12 operands.
638  if (N.getOpcode() != ISD::SUB) {
639    int RHSC;
640    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
641                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
642      Base = N.getOperand(0);
643      if (Base.getOpcode() == ISD::FrameIndex) {
644        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
645        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
646      }
647      Offset = CurDAG->getRegister(0, MVT::i32);
648
649      ARM_AM::AddrOpc AddSub = ARM_AM::add;
650      if (RHSC < 0) {
651        AddSub = ARM_AM::sub;
652        RHSC = - RHSC;
653      }
654      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
655                                                        ARM_AM::no_shift),
656                                      MVT::i32);
657      return AM2_BASE;
658    }
659  }
660
661  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
662    // Compute R +/- (R << N) and reuse it.
663    Base = N;
664    Offset = CurDAG->getRegister(0, MVT::i32);
665    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
666                                                      ARM_AM::no_shift),
667                                    MVT::i32);
668    return AM2_BASE;
669  }
670
671  // Otherwise this is R +/- [possibly shifted] R.
672  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
673  ARM_AM::ShiftOpc ShOpcVal =
674    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
675  unsigned ShAmt = 0;
676
677  Base   = N.getOperand(0);
678  Offset = N.getOperand(1);
679
680  if (ShOpcVal != ARM_AM::no_shift) {
681    // Check to see if the RHS of the shift is a constant, if not, we can't fold
682    // it.
683    if (ConstantSDNode *Sh =
684           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
685      ShAmt = Sh->getZExtValue();
686      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
687        Offset = N.getOperand(1).getOperand(0);
688      else {
689        ShAmt = 0;
690        ShOpcVal = ARM_AM::no_shift;
691      }
692    } else {
693      ShOpcVal = ARM_AM::no_shift;
694    }
695  }
696
697  // Try matching (R shl C) + (R).
698  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
699      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
700    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
701    if (ShOpcVal != ARM_AM::no_shift) {
702      // Check to see if the RHS of the shift is a constant, if not, we can't
703      // fold it.
704      if (ConstantSDNode *Sh =
705          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
706        ShAmt = Sh->getZExtValue();
707        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
708          Offset = N.getOperand(0).getOperand(0);
709          Base = N.getOperand(1);
710        } else {
711          ShAmt = 0;
712          ShOpcVal = ARM_AM::no_shift;
713        }
714      } else {
715        ShOpcVal = ARM_AM::no_shift;
716      }
717    }
718  }
719
720  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
721                                  MVT::i32);
722  return AM2_SHOP;
723}
724
725bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
726                                            SDValue &Offset, SDValue &Opc) {
727  unsigned Opcode = Op->getOpcode();
728  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
729    ? cast<LoadSDNode>(Op)->getAddressingMode()
730    : cast<StoreSDNode>(Op)->getAddressingMode();
731  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
732    ? ARM_AM::add : ARM_AM::sub;
733  int Val;
734  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
735    return false;
736
737  Offset = N;
738  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
739  unsigned ShAmt = 0;
740  if (ShOpcVal != ARM_AM::no_shift) {
741    // Check to see if the RHS of the shift is a constant, if not, we can't fold
742    // it.
743    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
744      ShAmt = Sh->getZExtValue();
745      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
746        Offset = N.getOperand(0);
747      else {
748        ShAmt = 0;
749        ShOpcVal = ARM_AM::no_shift;
750      }
751    } else {
752      ShOpcVal = ARM_AM::no_shift;
753    }
754  }
755
756  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
757                                  MVT::i32);
758  return true;
759}
760
761bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
762                                            SDValue &Offset, SDValue &Opc) {
763  unsigned Opcode = Op->getOpcode();
764  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
765    ? cast<LoadSDNode>(Op)->getAddressingMode()
766    : cast<StoreSDNode>(Op)->getAddressingMode();
767  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
768    ? ARM_AM::add : ARM_AM::sub;
769  int Val;
770  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
771    if (AddSub == ARM_AM::sub) Val *= -1;
772    Offset = CurDAG->getRegister(0, MVT::i32);
773    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
774    return true;
775  }
776
777  return false;
778}
779
780
781bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
782                                            SDValue &Offset, SDValue &Opc) {
783  unsigned Opcode = Op->getOpcode();
784  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
785    ? cast<LoadSDNode>(Op)->getAddressingMode()
786    : cast<StoreSDNode>(Op)->getAddressingMode();
787  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
788    ? ARM_AM::add : ARM_AM::sub;
789  int Val;
790  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
791    Offset = CurDAG->getRegister(0, MVT::i32);
792    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
793                                                      ARM_AM::no_shift),
794                                    MVT::i32);
795    return true;
796  }
797
798  return false;
799}
800
801bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
802  Base = N;
803  return true;
804}
805
806bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
807                                      SDValue &Base, SDValue &Offset,
808                                      SDValue &Opc) {
809  if (N.getOpcode() == ISD::SUB) {
810    // X - C  is canonicalize to X + -C, no need to handle it here.
811    Base = N.getOperand(0);
812    Offset = N.getOperand(1);
813    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
814    return true;
815  }
816
817  if (!CurDAG->isBaseWithConstantOffset(N)) {
818    Base = N;
819    if (N.getOpcode() == ISD::FrameIndex) {
820      int FI = cast<FrameIndexSDNode>(N)->getIndex();
821      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
822    }
823    Offset = CurDAG->getRegister(0, MVT::i32);
824    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
825    return true;
826  }
827
828  // If the RHS is +/- imm8, fold into addr mode.
829  int RHSC;
830  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
831                              -256 + 1, 256, RHSC)) { // 8 bits.
832    Base = N.getOperand(0);
833    if (Base.getOpcode() == ISD::FrameIndex) {
834      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
835      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
836    }
837    Offset = CurDAG->getRegister(0, MVT::i32);
838
839    ARM_AM::AddrOpc AddSub = ARM_AM::add;
840    if (RHSC < 0) {
841      AddSub = ARM_AM::sub;
842      RHSC = -RHSC;
843    }
844    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
845    return true;
846  }
847
848  Base = N.getOperand(0);
849  Offset = N.getOperand(1);
850  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
851  return true;
852}
853
854bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
855                                            SDValue &Offset, SDValue &Opc) {
856  unsigned Opcode = Op->getOpcode();
857  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
858    ? cast<LoadSDNode>(Op)->getAddressingMode()
859    : cast<StoreSDNode>(Op)->getAddressingMode();
860  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
861    ? ARM_AM::add : ARM_AM::sub;
862  int Val;
863  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
864    Offset = CurDAG->getRegister(0, MVT::i32);
865    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
866    return true;
867  }
868
869  Offset = N;
870  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
871  return true;
872}
873
874bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
875                                      SDValue &Base, SDValue &Offset) {
876  if (!CurDAG->isBaseWithConstantOffset(N)) {
877    Base = N;
878    if (N.getOpcode() == ISD::FrameIndex) {
879      int FI = cast<FrameIndexSDNode>(N)->getIndex();
880      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
881    } else if (N.getOpcode() == ARMISD::Wrapper &&
882               !(Subtarget->useMovt() &&
883                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
884      Base = N.getOperand(0);
885    }
886    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
887                                       MVT::i32);
888    return true;
889  }
890
891  // If the RHS is +/- imm8, fold into addr mode.
892  int RHSC;
893  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
894                              -256 + 1, 256, RHSC)) {
895    Base = N.getOperand(0);
896    if (Base.getOpcode() == ISD::FrameIndex) {
897      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
898      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
899    }
900
901    ARM_AM::AddrOpc AddSub = ARM_AM::add;
902    if (RHSC < 0) {
903      AddSub = ARM_AM::sub;
904      RHSC = -RHSC;
905    }
906    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
907                                       MVT::i32);
908    return true;
909  }
910
911  Base = N;
912  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
913                                     MVT::i32);
914  return true;
915}
916
917bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
918                                      SDValue &Align) {
919  Addr = N;
920
921  unsigned Alignment = 0;
922  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
923    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
924    // The maximum alignment is equal to the memory size being referenced.
925    unsigned LSNAlign = LSN->getAlignment();
926    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
927    if (LSNAlign >= MemSize && MemSize > 1)
928      Alignment = MemSize;
929  } else {
930    // All other uses of addrmode6 are for intrinsics.  For now just record
931    // the raw alignment value; it will be refined later based on the legal
932    // alignment operands for the intrinsic.
933    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
934  }
935
936  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
937  return true;
938}
939
940bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
941                                            SDValue &Offset) {
942  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
943  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
944  if (AM != ISD::POST_INC)
945    return false;
946  Offset = N;
947  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
948    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
949      Offset = CurDAG->getRegister(0, MVT::i32);
950  }
951  return true;
952}
953
954bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
955                                       SDValue &Offset, SDValue &Label) {
956  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
957    Offset = N.getOperand(0);
958    SDValue N1 = N.getOperand(1);
959    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
960                                      MVT::i32);
961    return true;
962  }
963
964  return false;
965}
966
967
968//===----------------------------------------------------------------------===//
969//                         Thumb Addressing Modes
970//===----------------------------------------------------------------------===//
971
972bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
973                                            SDValue &Base, SDValue &Offset){
974  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
975    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
976    if (!NC || !NC->isNullValue())
977      return false;
978
979    Base = Offset = N;
980    return true;
981  }
982
983  Base = N.getOperand(0);
984  Offset = N.getOperand(1);
985  return true;
986}
987
988bool
989ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
990                                       SDValue &Offset, unsigned Scale) {
991  if (Scale == 4) {
992    SDValue TmpBase, TmpOffImm;
993    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
994      return false;  // We want to select tLDRspi / tSTRspi instead.
995
996    if (N.getOpcode() == ARMISD::Wrapper &&
997        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
998      return false;  // We want to select tLDRpci instead.
999  }
1000
1001  if (!CurDAG->isBaseWithConstantOffset(N))
1002    return false;
1003
1004  // Thumb does not have [sp, r] address mode.
1005  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1006  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1007  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1008      (RHSR && RHSR->getReg() == ARM::SP))
1009    return false;
1010
1011  // FIXME: Why do we explicitly check for a match here and then return false?
1012  // Presumably to allow something else to match, but shouldn't this be
1013  // documented?
1014  int RHSC;
1015  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1016    return false;
1017
1018  Base = N.getOperand(0);
1019  Offset = N.getOperand(1);
1020  return true;
1021}
1022
1023bool
1024ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1025                                          SDValue &Base,
1026                                          SDValue &Offset) {
1027  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1028}
1029
1030bool
1031ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1032                                          SDValue &Base,
1033                                          SDValue &Offset) {
1034  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1035}
1036
1037bool
1038ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1039                                          SDValue &Base,
1040                                          SDValue &Offset) {
1041  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1042}
1043
1044bool
1045ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1046                                          SDValue &Base, SDValue &OffImm) {
1047  if (Scale == 4) {
1048    SDValue TmpBase, TmpOffImm;
1049    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1050      return false;  // We want to select tLDRspi / tSTRspi instead.
1051
1052    if (N.getOpcode() == ARMISD::Wrapper &&
1053        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1054      return false;  // We want to select tLDRpci instead.
1055  }
1056
1057  if (!CurDAG->isBaseWithConstantOffset(N)) {
1058    if (N.getOpcode() == ARMISD::Wrapper &&
1059        !(Subtarget->useMovt() &&
1060          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1061      Base = N.getOperand(0);
1062    } else {
1063      Base = N;
1064    }
1065
1066    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1067    return true;
1068  }
1069
1070  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1071  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1072  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1073      (RHSR && RHSR->getReg() == ARM::SP)) {
1074    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1075    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1076    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1077    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1078
1079    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1080    if (LHSC != 0 || RHSC != 0) return false;
1081
1082    Base = N;
1083    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1084    return true;
1085  }
1086
1087  // If the RHS is + imm5 * scale, fold into addr mode.
1088  int RHSC;
1089  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1090    Base = N.getOperand(0);
1091    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1092    return true;
1093  }
1094
1095  Base = N.getOperand(0);
1096  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1097  return true;
1098}
1099
1100bool
1101ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1102                                           SDValue &OffImm) {
1103  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1104}
1105
1106bool
1107ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1108                                           SDValue &OffImm) {
1109  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1110}
1111
1112bool
1113ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1114                                           SDValue &OffImm) {
1115  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1116}
1117
1118bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1119                                            SDValue &Base, SDValue &OffImm) {
1120  if (N.getOpcode() == ISD::FrameIndex) {
1121    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1122    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1123    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1124    return true;
1125  }
1126
1127  if (!CurDAG->isBaseWithConstantOffset(N))
1128    return false;
1129
1130  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1131  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1132      (LHSR && LHSR->getReg() == ARM::SP)) {
1133    // If the RHS is + imm8 * scale, fold into addr mode.
1134    int RHSC;
1135    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1136      Base = N.getOperand(0);
1137      if (Base.getOpcode() == ISD::FrameIndex) {
1138        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1139        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1140      }
1141      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1142      return true;
1143    }
1144  }
1145
1146  return false;
1147}
1148
1149
1150//===----------------------------------------------------------------------===//
1151//                        Thumb 2 Addressing Modes
1152//===----------------------------------------------------------------------===//
1153
1154
1155bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1156                                                SDValue &Opc) {
1157  if (DisableShifterOp)
1158    return false;
1159
1160  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1161
1162  // Don't match base register only case. That is matched to a separate
1163  // lower complexity pattern with explicit register operand.
1164  if (ShOpcVal == ARM_AM::no_shift) return false;
1165
1166  BaseReg = N.getOperand(0);
1167  unsigned ShImmVal = 0;
1168  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1169    ShImmVal = RHS->getZExtValue() & 31;
1170    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1171    return true;
1172  }
1173
1174  return false;
1175}
1176
1177bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1178                                            SDValue &Base, SDValue &OffImm) {
1179  // Match simple R + imm12 operands.
1180
1181  // Base only.
1182  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1183      !CurDAG->isBaseWithConstantOffset(N)) {
1184    if (N.getOpcode() == ISD::FrameIndex) {
1185      // Match frame index.
1186      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1187      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1188      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1189      return true;
1190    }
1191
1192    if (N.getOpcode() == ARMISD::Wrapper &&
1193               !(Subtarget->useMovt() &&
1194                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1195      Base = N.getOperand(0);
1196      if (Base.getOpcode() == ISD::TargetConstantPool)
1197        return false;  // We want to select t2LDRpci instead.
1198    } else
1199      Base = N;
1200    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1201    return true;
1202  }
1203
1204  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1205    if (SelectT2AddrModeImm8(N, Base, OffImm))
1206      // Let t2LDRi8 handle (R - imm8).
1207      return false;
1208
1209    int RHSC = (int)RHS->getZExtValue();
1210    if (N.getOpcode() == ISD::SUB)
1211      RHSC = -RHSC;
1212
1213    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1214      Base   = N.getOperand(0);
1215      if (Base.getOpcode() == ISD::FrameIndex) {
1216        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1217        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1218      }
1219      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1220      return true;
1221    }
1222  }
1223
1224  // Base only.
1225  Base = N;
1226  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1227  return true;
1228}
1229
1230bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1231                                           SDValue &Base, SDValue &OffImm) {
1232  // Match simple R - imm8 operands.
1233  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1234      !CurDAG->isBaseWithConstantOffset(N))
1235    return false;
1236
1237  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1238    int RHSC = (int)RHS->getSExtValue();
1239    if (N.getOpcode() == ISD::SUB)
1240      RHSC = -RHSC;
1241
1242    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1243      Base = N.getOperand(0);
1244      if (Base.getOpcode() == ISD::FrameIndex) {
1245        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1246        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1247      }
1248      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1249      return true;
1250    }
1251  }
1252
1253  return false;
1254}
1255
1256bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1257                                                 SDValue &OffImm){
1258  unsigned Opcode = Op->getOpcode();
1259  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1260    ? cast<LoadSDNode>(Op)->getAddressingMode()
1261    : cast<StoreSDNode>(Op)->getAddressingMode();
1262  int RHSC;
1263  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1264    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1265      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1266      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1267    return true;
1268  }
1269
1270  return false;
1271}
1272
1273bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1274                                            SDValue &Base,
1275                                            SDValue &OffReg, SDValue &ShImm) {
1276  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1277  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1278    return false;
1279
1280  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1281  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1282    int RHSC = (int)RHS->getZExtValue();
1283    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1284      return false;
1285    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1286      return false;
1287  }
1288
1289  // Look for (R + R) or (R + (R << [1,2,3])).
1290  unsigned ShAmt = 0;
1291  Base   = N.getOperand(0);
1292  OffReg = N.getOperand(1);
1293
1294  // Swap if it is ((R << c) + R).
1295  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1296  if (ShOpcVal != ARM_AM::lsl) {
1297    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1298    if (ShOpcVal == ARM_AM::lsl)
1299      std::swap(Base, OffReg);
1300  }
1301
1302  if (ShOpcVal == ARM_AM::lsl) {
1303    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1304    // it.
1305    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1306      ShAmt = Sh->getZExtValue();
1307      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1308        OffReg = OffReg.getOperand(0);
1309      else {
1310        ShAmt = 0;
1311        ShOpcVal = ARM_AM::no_shift;
1312      }
1313    } else {
1314      ShOpcVal = ARM_AM::no_shift;
1315    }
1316  }
1317
1318  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1319
1320  return true;
1321}
1322
1323//===--------------------------------------------------------------------===//
1324
1325/// getAL - Returns a ARMCC::AL immediate node.
1326static inline SDValue getAL(SelectionDAG *CurDAG) {
1327  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1328}
1329
1330SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1331  LoadSDNode *LD = cast<LoadSDNode>(N);
1332  ISD::MemIndexedMode AM = LD->getAddressingMode();
1333  if (AM == ISD::UNINDEXED)
1334    return NULL;
1335
1336  EVT LoadedVT = LD->getMemoryVT();
1337  SDValue Offset, AMOpc;
1338  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1339  unsigned Opcode = 0;
1340  bool Match = false;
1341  if (LoadedVT == MVT::i32 && isPre &&
1342      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1343    Opcode = ARM::LDR_PRE_IMM;
1344    Match = true;
1345  } else if (LoadedVT == MVT::i32 && !isPre &&
1346      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1347    Opcode = ARM::LDR_POST_IMM;
1348    Match = true;
1349  } else if (LoadedVT == MVT::i32 &&
1350      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1351    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1352    Match = true;
1353
1354  } else if (LoadedVT == MVT::i16 &&
1355             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1356    Match = true;
1357    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1358      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1359      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1360  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1361    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1362      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1363        Match = true;
1364        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1365      }
1366    } else {
1367      if (isPre &&
1368          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1369        Match = true;
1370        Opcode = ARM::LDRB_PRE_IMM;
1371      } else if (!isPre &&
1372                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1373        Match = true;
1374        Opcode = ARM::LDRB_POST_IMM;
1375      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1376        Match = true;
1377        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1378      }
1379    }
1380  }
1381
1382  if (Match) {
1383    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1384      SDValue Chain = LD->getChain();
1385      SDValue Base = LD->getBasePtr();
1386      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1387                       CurDAG->getRegister(0, MVT::i32), Chain };
1388      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1389                                    MVT::i32, MVT::Other, Ops, 5);
1390    } else {
1391      SDValue Chain = LD->getChain();
1392      SDValue Base = LD->getBasePtr();
1393      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1394                       CurDAG->getRegister(0, MVT::i32), Chain };
1395      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1396                                    MVT::i32, MVT::Other, Ops, 6);
1397    }
1398  }
1399
1400  return NULL;
1401}
1402
1403SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1404  LoadSDNode *LD = cast<LoadSDNode>(N);
1405  ISD::MemIndexedMode AM = LD->getAddressingMode();
1406  if (AM == ISD::UNINDEXED)
1407    return NULL;
1408
1409  EVT LoadedVT = LD->getMemoryVT();
1410  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1411  SDValue Offset;
1412  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1413  unsigned Opcode = 0;
1414  bool Match = false;
1415  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1416    switch (LoadedVT.getSimpleVT().SimpleTy) {
1417    case MVT::i32:
1418      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1419      break;
1420    case MVT::i16:
1421      if (isSExtLd)
1422        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1423      else
1424        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1425      break;
1426    case MVT::i8:
1427    case MVT::i1:
1428      if (isSExtLd)
1429        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1430      else
1431        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1432      break;
1433    default:
1434      return NULL;
1435    }
1436    Match = true;
1437  }
1438
1439  if (Match) {
1440    SDValue Chain = LD->getChain();
1441    SDValue Base = LD->getBasePtr();
1442    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1443                     CurDAG->getRegister(0, MVT::i32), Chain };
1444    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1445                                  MVT::Other, Ops, 5);
1446  }
1447
1448  return NULL;
1449}
1450
1451/// PairSRegs - Form a D register from a pair of S registers.
1452///
1453SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1454  DebugLoc dl = V0.getNode()->getDebugLoc();
1455  SDValue RegClass =
1456    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1457  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1458  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1459  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1460  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1461}
1462
1463/// PairDRegs - Form a quad register from a pair of D registers.
1464///
1465SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1466  DebugLoc dl = V0.getNode()->getDebugLoc();
1467  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1468  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1469  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1470  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1471  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1472}
1473
1474/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1475///
1476SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1477  DebugLoc dl = V0.getNode()->getDebugLoc();
1478  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1479  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1480  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1481  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1482  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1483}
1484
1485/// QuadSRegs - Form 4 consecutive S registers.
1486///
1487SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1488                                   SDValue V2, SDValue V3) {
1489  DebugLoc dl = V0.getNode()->getDebugLoc();
1490  SDValue RegClass =
1491    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1492  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1493  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1494  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1495  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1496  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1497                                    V2, SubReg2, V3, SubReg3 };
1498  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1499}
1500
1501/// QuadDRegs - Form 4 consecutive D registers.
1502///
1503SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1504                                   SDValue V2, SDValue V3) {
1505  DebugLoc dl = V0.getNode()->getDebugLoc();
1506  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1507  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1508  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1509  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1510  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1511  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1512                                    V2, SubReg2, V3, SubReg3 };
1513  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1514}
1515
1516/// QuadQRegs - Form 4 consecutive Q registers.
1517///
1518SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1519                                   SDValue V2, SDValue V3) {
1520  DebugLoc dl = V0.getNode()->getDebugLoc();
1521  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1522  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1523  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1524  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1525  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1526  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1527                                    V2, SubReg2, V3, SubReg3 };
1528  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1529}
1530
1531/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1532/// of a NEON VLD or VST instruction.  The supported values depend on the
1533/// number of registers being loaded.
1534SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1535                                       bool is64BitVector) {
1536  unsigned NumRegs = NumVecs;
1537  if (!is64BitVector && NumVecs < 3)
1538    NumRegs *= 2;
1539
1540  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1541  if (Alignment >= 32 && NumRegs == 4)
1542    Alignment = 32;
1543  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1544    Alignment = 16;
1545  else if (Alignment >= 8)
1546    Alignment = 8;
1547  else
1548    Alignment = 0;
1549
1550  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1551}
1552
1553// Get the register stride update opcode of a VLD/VST instruction that
1554// is otherwise equivalent to the given fixed stride updating instruction.
1555static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1556  switch (Opc) {
1557  default: break;
1558  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1559  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1560  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1561  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1562  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1563  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1564  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1565  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1566
1567  case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1568  case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1569  case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1570  case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1571  case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1572  case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1573  case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1574  case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1575  case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1576  case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1577
1578  case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1579  case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1580  case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1581  case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1582  case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1583  case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1584
1585  case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1586  case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1587  case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1588  case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1589  case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1590  case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1591
1592  case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1593  case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1594  case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1595  }
1596  return Opc; // If not one we handle, return it unchanged.
1597}
1598
1599SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1600                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1601                                   unsigned *QOpcodes1) {
1602  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1603  DebugLoc dl = N->getDebugLoc();
1604
1605  SDValue MemAddr, Align;
1606  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1607  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1608    return NULL;
1609
1610  SDValue Chain = N->getOperand(0);
1611  EVT VT = N->getValueType(0);
1612  bool is64BitVector = VT.is64BitVector();
1613  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1614
1615  unsigned OpcodeIndex;
1616  switch (VT.getSimpleVT().SimpleTy) {
1617  default: llvm_unreachable("unhandled vld type");
1618    // Double-register operations:
1619  case MVT::v8i8:  OpcodeIndex = 0; break;
1620  case MVT::v4i16: OpcodeIndex = 1; break;
1621  case MVT::v2f32:
1622  case MVT::v2i32: OpcodeIndex = 2; break;
1623  case MVT::v1i64: OpcodeIndex = 3; break;
1624    // Quad-register operations:
1625  case MVT::v16i8: OpcodeIndex = 0; break;
1626  case MVT::v8i16: OpcodeIndex = 1; break;
1627  case MVT::v4f32:
1628  case MVT::v4i32: OpcodeIndex = 2; break;
1629  case MVT::v2i64: OpcodeIndex = 3;
1630    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1631    break;
1632  }
1633
1634  EVT ResTy;
1635  if (NumVecs == 1)
1636    ResTy = VT;
1637  else {
1638    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1639    if (!is64BitVector)
1640      ResTyElts *= 2;
1641    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1642  }
1643  std::vector<EVT> ResTys;
1644  ResTys.push_back(ResTy);
1645  if (isUpdating)
1646    ResTys.push_back(MVT::i32);
1647  ResTys.push_back(MVT::Other);
1648
1649  SDValue Pred = getAL(CurDAG);
1650  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1651  SDNode *VLd;
1652  SmallVector<SDValue, 7> Ops;
1653
1654  // Double registers and VLD1/VLD2 quad registers are directly supported.
1655  if (is64BitVector || NumVecs <= 2) {
1656    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1657                    QOpcodes0[OpcodeIndex]);
1658    Ops.push_back(MemAddr);
1659    Ops.push_back(Align);
1660    if (isUpdating) {
1661      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1662      // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1663      // case entirely when the rest are updated to that form, too.
1664      if ((NumVecs == 1 || NumVecs == 2) && !isa<ConstantSDNode>(Inc.getNode()))
1665        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1666      // We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1667      // check for that explicitly too. Horribly hacky, but temporary.
1668      if ((NumVecs != 1 && NumVecs != 2 && Opc != ARM::VLD1q64wb_fixed) ||
1669          !isa<ConstantSDNode>(Inc.getNode()))
1670        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1671    }
1672    Ops.push_back(Pred);
1673    Ops.push_back(Reg0);
1674    Ops.push_back(Chain);
1675    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1676
1677  } else {
1678    // Otherwise, quad registers are loaded with two separate instructions,
1679    // where one loads the even registers and the other loads the odd registers.
1680    EVT AddrTy = MemAddr.getValueType();
1681
1682    // Load the even subregs.  This is always an updating load, so that it
1683    // provides the address to the second load for the odd subregs.
1684    SDValue ImplDef =
1685      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1686    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1687    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1688                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1689    Chain = SDValue(VLdA, 2);
1690
1691    // Load the odd subregs.
1692    Ops.push_back(SDValue(VLdA, 1));
1693    Ops.push_back(Align);
1694    if (isUpdating) {
1695      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1696      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1697             "only constant post-increment update allowed for VLD3/4");
1698      (void)Inc;
1699      Ops.push_back(Reg0);
1700    }
1701    Ops.push_back(SDValue(VLdA, 0));
1702    Ops.push_back(Pred);
1703    Ops.push_back(Reg0);
1704    Ops.push_back(Chain);
1705    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1706                                 Ops.data(), Ops.size());
1707  }
1708
1709  // Transfer memoperands.
1710  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1711  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1712  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1713
1714  if (NumVecs == 1)
1715    return VLd;
1716
1717  // Extract out the subregisters.
1718  SDValue SuperReg = SDValue(VLd, 0);
1719  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1720         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1721  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1722  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1723    ReplaceUses(SDValue(N, Vec),
1724                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1725  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1726  if (isUpdating)
1727    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1728  return NULL;
1729}
1730
1731SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1732                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1733                                   unsigned *QOpcodes1) {
1734  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1735  DebugLoc dl = N->getDebugLoc();
1736
1737  SDValue MemAddr, Align;
1738  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1739  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1740  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1741    return NULL;
1742
1743  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1744  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1745
1746  SDValue Chain = N->getOperand(0);
1747  EVT VT = N->getOperand(Vec0Idx).getValueType();
1748  bool is64BitVector = VT.is64BitVector();
1749  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1750
1751  unsigned OpcodeIndex;
1752  switch (VT.getSimpleVT().SimpleTy) {
1753  default: llvm_unreachable("unhandled vst type");
1754    // Double-register operations:
1755  case MVT::v8i8:  OpcodeIndex = 0; break;
1756  case MVT::v4i16: OpcodeIndex = 1; break;
1757  case MVT::v2f32:
1758  case MVT::v2i32: OpcodeIndex = 2; break;
1759  case MVT::v1i64: OpcodeIndex = 3; break;
1760    // Quad-register operations:
1761  case MVT::v16i8: OpcodeIndex = 0; break;
1762  case MVT::v8i16: OpcodeIndex = 1; break;
1763  case MVT::v4f32:
1764  case MVT::v4i32: OpcodeIndex = 2; break;
1765  case MVT::v2i64: OpcodeIndex = 3;
1766    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1767    break;
1768  }
1769
1770  std::vector<EVT> ResTys;
1771  if (isUpdating)
1772    ResTys.push_back(MVT::i32);
1773  ResTys.push_back(MVT::Other);
1774
1775  SDValue Pred = getAL(CurDAG);
1776  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1777  SmallVector<SDValue, 7> Ops;
1778
1779  // Double registers and VST1/VST2 quad registers are directly supported.
1780  if (is64BitVector || NumVecs <= 2) {
1781    SDValue SrcReg;
1782    if (NumVecs == 1) {
1783      SrcReg = N->getOperand(Vec0Idx);
1784    } else if (is64BitVector) {
1785      // Form a REG_SEQUENCE to force register allocation.
1786      SDValue V0 = N->getOperand(Vec0Idx + 0);
1787      SDValue V1 = N->getOperand(Vec0Idx + 1);
1788      if (NumVecs == 2)
1789        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1790      else {
1791        SDValue V2 = N->getOperand(Vec0Idx + 2);
1792        // If it's a vst3, form a quad D-register and leave the last part as
1793        // an undef.
1794        SDValue V3 = (NumVecs == 3)
1795          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1796          : N->getOperand(Vec0Idx + 3);
1797        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1798      }
1799    } else {
1800      // Form a QQ register.
1801      SDValue Q0 = N->getOperand(Vec0Idx);
1802      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1803      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1804    }
1805
1806    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1807                    QOpcodes0[OpcodeIndex]);
1808    Ops.push_back(MemAddr);
1809    Ops.push_back(Align);
1810    if (isUpdating) {
1811      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1812      // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1813      // case entirely when the rest are updated to that form, too.
1814      if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1815        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1816      // We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1817      // check for that explicitly too. Horribly hacky, but temporary.
1818      if ((NumVecs > 2 && Opc != ARM::VST1q64wb_fixed) ||
1819          !isa<ConstantSDNode>(Inc.getNode()))
1820        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1821    }
1822    Ops.push_back(SrcReg);
1823    Ops.push_back(Pred);
1824    Ops.push_back(Reg0);
1825    Ops.push_back(Chain);
1826    SDNode *VSt =
1827      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1828
1829    // Transfer memoperands.
1830    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1831
1832    return VSt;
1833  }
1834
1835  // Otherwise, quad registers are stored with two separate instructions,
1836  // where one stores the even registers and the other stores the odd registers.
1837
1838  // Form the QQQQ REG_SEQUENCE.
1839  SDValue V0 = N->getOperand(Vec0Idx + 0);
1840  SDValue V1 = N->getOperand(Vec0Idx + 1);
1841  SDValue V2 = N->getOperand(Vec0Idx + 2);
1842  SDValue V3 = (NumVecs == 3)
1843    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1844    : N->getOperand(Vec0Idx + 3);
1845  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1846
1847  // Store the even D registers.  This is always an updating store, so that it
1848  // provides the address to the second store for the odd subregs.
1849  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1850  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1851                                        MemAddr.getValueType(),
1852                                        MVT::Other, OpsA, 7);
1853  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1854  Chain = SDValue(VStA, 1);
1855
1856  // Store the odd D registers.
1857  Ops.push_back(SDValue(VStA, 0));
1858  Ops.push_back(Align);
1859  if (isUpdating) {
1860    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1861    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1862           "only constant post-increment update allowed for VST3/4");
1863    (void)Inc;
1864    Ops.push_back(Reg0);
1865  }
1866  Ops.push_back(RegSeq);
1867  Ops.push_back(Pred);
1868  Ops.push_back(Reg0);
1869  Ops.push_back(Chain);
1870  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1871                                        Ops.data(), Ops.size());
1872  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1873  return VStB;
1874}
1875
1876SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1877                                         bool isUpdating, unsigned NumVecs,
1878                                         unsigned *DOpcodes,
1879                                         unsigned *QOpcodes) {
1880  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1881  DebugLoc dl = N->getDebugLoc();
1882
1883  SDValue MemAddr, Align;
1884  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1885  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1886  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1887    return NULL;
1888
1889  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1890  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1891
1892  SDValue Chain = N->getOperand(0);
1893  unsigned Lane =
1894    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1895  EVT VT = N->getOperand(Vec0Idx).getValueType();
1896  bool is64BitVector = VT.is64BitVector();
1897
1898  unsigned Alignment = 0;
1899  if (NumVecs != 3) {
1900    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1901    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1902    if (Alignment > NumBytes)
1903      Alignment = NumBytes;
1904    if (Alignment < 8 && Alignment < NumBytes)
1905      Alignment = 0;
1906    // Alignment must be a power of two; make sure of that.
1907    Alignment = (Alignment & -Alignment);
1908    if (Alignment == 1)
1909      Alignment = 0;
1910  }
1911  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1912
1913  unsigned OpcodeIndex;
1914  switch (VT.getSimpleVT().SimpleTy) {
1915  default: llvm_unreachable("unhandled vld/vst lane type");
1916    // Double-register operations:
1917  case MVT::v8i8:  OpcodeIndex = 0; break;
1918  case MVT::v4i16: OpcodeIndex = 1; break;
1919  case MVT::v2f32:
1920  case MVT::v2i32: OpcodeIndex = 2; break;
1921    // Quad-register operations:
1922  case MVT::v8i16: OpcodeIndex = 0; break;
1923  case MVT::v4f32:
1924  case MVT::v4i32: OpcodeIndex = 1; break;
1925  }
1926
1927  std::vector<EVT> ResTys;
1928  if (IsLoad) {
1929    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1930    if (!is64BitVector)
1931      ResTyElts *= 2;
1932    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1933                                      MVT::i64, ResTyElts));
1934  }
1935  if (isUpdating)
1936    ResTys.push_back(MVT::i32);
1937  ResTys.push_back(MVT::Other);
1938
1939  SDValue Pred = getAL(CurDAG);
1940  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1941
1942  SmallVector<SDValue, 8> Ops;
1943  Ops.push_back(MemAddr);
1944  Ops.push_back(Align);
1945  if (isUpdating) {
1946    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1947    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1948  }
1949
1950  SDValue SuperReg;
1951  SDValue V0 = N->getOperand(Vec0Idx + 0);
1952  SDValue V1 = N->getOperand(Vec0Idx + 1);
1953  if (NumVecs == 2) {
1954    if (is64BitVector)
1955      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1956    else
1957      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1958  } else {
1959    SDValue V2 = N->getOperand(Vec0Idx + 2);
1960    SDValue V3 = (NumVecs == 3)
1961      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1962      : N->getOperand(Vec0Idx + 3);
1963    if (is64BitVector)
1964      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1965    else
1966      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1967  }
1968  Ops.push_back(SuperReg);
1969  Ops.push_back(getI32Imm(Lane));
1970  Ops.push_back(Pred);
1971  Ops.push_back(Reg0);
1972  Ops.push_back(Chain);
1973
1974  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1975                                  QOpcodes[OpcodeIndex]);
1976  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1977                                         Ops.data(), Ops.size());
1978  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1979  if (!IsLoad)
1980    return VLdLn;
1981
1982  // Extract the subregisters.
1983  SuperReg = SDValue(VLdLn, 0);
1984  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1985         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1986  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1987  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1988    ReplaceUses(SDValue(N, Vec),
1989                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1990  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1991  if (isUpdating)
1992    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1993  return NULL;
1994}
1995
1996SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1997                                      unsigned NumVecs, unsigned *Opcodes) {
1998  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1999  DebugLoc dl = N->getDebugLoc();
2000
2001  SDValue MemAddr, Align;
2002  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2003    return NULL;
2004
2005  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2006  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2007
2008  SDValue Chain = N->getOperand(0);
2009  EVT VT = N->getValueType(0);
2010
2011  unsigned Alignment = 0;
2012  if (NumVecs != 3) {
2013    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2014    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2015    if (Alignment > NumBytes)
2016      Alignment = NumBytes;
2017    if (Alignment < 8 && Alignment < NumBytes)
2018      Alignment = 0;
2019    // Alignment must be a power of two; make sure of that.
2020    Alignment = (Alignment & -Alignment);
2021    if (Alignment == 1)
2022      Alignment = 0;
2023  }
2024  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2025
2026  unsigned OpcodeIndex;
2027  switch (VT.getSimpleVT().SimpleTy) {
2028  default: llvm_unreachable("unhandled vld-dup type");
2029  case MVT::v8i8:  OpcodeIndex = 0; break;
2030  case MVT::v4i16: OpcodeIndex = 1; break;
2031  case MVT::v2f32:
2032  case MVT::v2i32: OpcodeIndex = 2; break;
2033  }
2034
2035  SDValue Pred = getAL(CurDAG);
2036  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2037  SDValue SuperReg;
2038  unsigned Opc = Opcodes[OpcodeIndex];
2039  SmallVector<SDValue, 6> Ops;
2040  Ops.push_back(MemAddr);
2041  Ops.push_back(Align);
2042  if (isUpdating) {
2043    // fixed-stride update instructions don't have an explicit writeback
2044    // operand. It's implicit in the opcode itself.
2045    SDValue Inc = N->getOperand(2);
2046    if (!isa<ConstantSDNode>(Inc.getNode()))
2047      Ops.push_back(Inc);
2048    // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2049    else if (NumVecs > 2)
2050      Ops.push_back(Reg0);
2051  }
2052  Ops.push_back(Pred);
2053  Ops.push_back(Reg0);
2054  Ops.push_back(Chain);
2055
2056  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2057  std::vector<EVT> ResTys;
2058  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2059  if (isUpdating)
2060    ResTys.push_back(MVT::i32);
2061  ResTys.push_back(MVT::Other);
2062  SDNode *VLdDup =
2063    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2064  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2065  SuperReg = SDValue(VLdDup, 0);
2066
2067  // Extract the subregisters.
2068  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2069  unsigned SubIdx = ARM::dsub_0;
2070  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2071    ReplaceUses(SDValue(N, Vec),
2072                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2073  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2074  if (isUpdating)
2075    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2076  return NULL;
2077}
2078
2079SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2080                                    unsigned Opc) {
2081  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2082  DebugLoc dl = N->getDebugLoc();
2083  EVT VT = N->getValueType(0);
2084  unsigned FirstTblReg = IsExt ? 2 : 1;
2085
2086  // Form a REG_SEQUENCE to force register allocation.
2087  SDValue RegSeq;
2088  SDValue V0 = N->getOperand(FirstTblReg + 0);
2089  SDValue V1 = N->getOperand(FirstTblReg + 1);
2090  if (NumVecs == 2)
2091    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2092  else {
2093    SDValue V2 = N->getOperand(FirstTblReg + 2);
2094    // If it's a vtbl3, form a quad D-register and leave the last part as
2095    // an undef.
2096    SDValue V3 = (NumVecs == 3)
2097      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2098      : N->getOperand(FirstTblReg + 3);
2099    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2100  }
2101
2102  SmallVector<SDValue, 6> Ops;
2103  if (IsExt)
2104    Ops.push_back(N->getOperand(1));
2105  Ops.push_back(RegSeq);
2106  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2107  Ops.push_back(getAL(CurDAG)); // predicate
2108  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2109  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2110}
2111
2112SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2113                                                     bool isSigned) {
2114  if (!Subtarget->hasV6T2Ops())
2115    return NULL;
2116
2117  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2118    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2119
2120
2121  // For unsigned extracts, check for a shift right and mask
2122  unsigned And_imm = 0;
2123  if (N->getOpcode() == ISD::AND) {
2124    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2125
2126      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2127      if (And_imm & (And_imm + 1))
2128        return NULL;
2129
2130      unsigned Srl_imm = 0;
2131      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2132                                Srl_imm)) {
2133        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2134
2135        // Note: The width operand is encoded as width-1.
2136        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2137        unsigned LSB = Srl_imm;
2138        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2139        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2140                          CurDAG->getTargetConstant(LSB, MVT::i32),
2141                          CurDAG->getTargetConstant(Width, MVT::i32),
2142          getAL(CurDAG), Reg0 };
2143        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2144      }
2145    }
2146    return NULL;
2147  }
2148
2149  // Otherwise, we're looking for a shift of a shift
2150  unsigned Shl_imm = 0;
2151  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2152    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2153    unsigned Srl_imm = 0;
2154    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2155      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2156      // Note: The width operand is encoded as width-1.
2157      unsigned Width = 32 - Srl_imm - 1;
2158      int LSB = Srl_imm - Shl_imm;
2159      if (LSB < 0)
2160        return NULL;
2161      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2162      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2163                        CurDAG->getTargetConstant(LSB, MVT::i32),
2164                        CurDAG->getTargetConstant(Width, MVT::i32),
2165                        getAL(CurDAG), Reg0 };
2166      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2167    }
2168  }
2169  return NULL;
2170}
2171
2172SDNode *ARMDAGToDAGISel::
2173SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2174                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2175  SDValue CPTmp0;
2176  SDValue CPTmp1;
2177  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2178    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2179    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2180    unsigned Opc = 0;
2181    switch (SOShOp) {
2182    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2183    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2184    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2185    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2186    default:
2187      llvm_unreachable("Unknown so_reg opcode!");
2188    }
2189    SDValue SOShImm =
2190      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2191    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2192    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2193    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2194  }
2195  return 0;
2196}
2197
2198SDNode *ARMDAGToDAGISel::
2199SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2200                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2201  SDValue CPTmp0;
2202  SDValue CPTmp1;
2203  SDValue CPTmp2;
2204  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2205    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2206    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2207    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2208  }
2209
2210  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2211    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2212    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2213    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2214  }
2215  return 0;
2216}
2217
2218SDNode *ARMDAGToDAGISel::
2219SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2220                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2221  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2222  if (!T)
2223    return 0;
2224
2225  unsigned Opc = 0;
2226  unsigned TrueImm = T->getZExtValue();
2227  if (is_t2_so_imm(TrueImm)) {
2228    Opc = ARM::t2MOVCCi;
2229  } else if (TrueImm <= 0xffff) {
2230    Opc = ARM::t2MOVCCi16;
2231  } else if (is_t2_so_imm_not(TrueImm)) {
2232    TrueImm = ~TrueImm;
2233    Opc = ARM::t2MVNCCi;
2234  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2235    // Large immediate.
2236    Opc = ARM::t2MOVCCi32imm;
2237  }
2238
2239  if (Opc) {
2240    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2241    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2242    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2243    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2244  }
2245
2246  return 0;
2247}
2248
2249SDNode *ARMDAGToDAGISel::
2250SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2251                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2252  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2253  if (!T)
2254    return 0;
2255
2256  unsigned Opc = 0;
2257  unsigned TrueImm = T->getZExtValue();
2258  bool isSoImm = is_so_imm(TrueImm);
2259  if (isSoImm) {
2260    Opc = ARM::MOVCCi;
2261  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2262    Opc = ARM::MOVCCi16;
2263  } else if (is_so_imm_not(TrueImm)) {
2264    TrueImm = ~TrueImm;
2265    Opc = ARM::MVNCCi;
2266  } else if (TrueVal.getNode()->hasOneUse() &&
2267             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2268    // Large immediate.
2269    Opc = ARM::MOVCCi32imm;
2270  }
2271
2272  if (Opc) {
2273    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2274    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2275    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2276    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2277  }
2278
2279  return 0;
2280}
2281
2282SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2283  EVT VT = N->getValueType(0);
2284  SDValue FalseVal = N->getOperand(0);
2285  SDValue TrueVal  = N->getOperand(1);
2286  SDValue CC = N->getOperand(2);
2287  SDValue CCR = N->getOperand(3);
2288  SDValue InFlag = N->getOperand(4);
2289  assert(CC.getOpcode() == ISD::Constant);
2290  assert(CCR.getOpcode() == ISD::Register);
2291  ARMCC::CondCodes CCVal =
2292    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2293
2294  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2295    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2296    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2297    // Pattern complexity = 18  cost = 1  size = 0
2298    if (Subtarget->isThumb()) {
2299      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2300                                        CCVal, CCR, InFlag);
2301      if (!Res)
2302        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2303                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2304      if (Res)
2305        return Res;
2306    } else {
2307      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2308                                         CCVal, CCR, InFlag);
2309      if (!Res)
2310        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2311                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2312      if (Res)
2313        return Res;
2314    }
2315
2316    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2317    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2318    //             (imm:i32):$cc)
2319    // Emits: (MOVCCi:i32 GPR:i32:$false,
2320    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2321    // Pattern complexity = 10  cost = 1  size = 0
2322    if (Subtarget->isThumb()) {
2323      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2324                                        CCVal, CCR, InFlag);
2325      if (!Res)
2326        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2327                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2328      if (Res)
2329        return Res;
2330    } else {
2331      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2332                                         CCVal, CCR, InFlag);
2333      if (!Res)
2334        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2335                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2336      if (Res)
2337        return Res;
2338    }
2339  }
2340
2341  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2342  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2343  // Pattern complexity = 6  cost = 1  size = 0
2344  //
2345  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2346  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2347  // Pattern complexity = 6  cost = 11  size = 0
2348  //
2349  // Also VMOVScc and VMOVDcc.
2350  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2351  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2352  unsigned Opc = 0;
2353  switch (VT.getSimpleVT().SimpleTy) {
2354  default: llvm_unreachable("Illegal conditional move type!");
2355  case MVT::i32:
2356    Opc = Subtarget->isThumb()
2357      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2358      : ARM::MOVCCr;
2359    break;
2360  case MVT::f32:
2361    Opc = ARM::VMOVScc;
2362    break;
2363  case MVT::f64:
2364    Opc = ARM::VMOVDcc;
2365    break;
2366  }
2367  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2368}
2369
2370SDNode *ARMDAGToDAGISel::SelectConditionalOp(SDNode *N) {
2371  SDValue FalseVal = N->getOperand(0);
2372  SDValue TrueVal  = N->getOperand(1);
2373  ARMCC::CondCodes CCVal =
2374    (ARMCC::CondCodes)cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
2375  SDValue CCR = N->getOperand(3);
2376  assert(CCR.getOpcode() == ISD::Register);
2377  SDValue InFlag = N->getOperand(4);
2378  SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2379  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2380
2381  if (Subtarget->isThumb()) {
2382    SDValue CPTmp0;
2383    SDValue CPTmp1;
2384    if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2385      unsigned Opc;
2386      switch (N->getOpcode()) {
2387      default: llvm_unreachable("Unexpected node");
2388      case ARMISD::CAND: Opc = ARM::t2ANDCCrs; break;
2389      case ARMISD::COR:  Opc = ARM::t2ORRCCrs; break;
2390      case ARMISD::CXOR: Opc = ARM::t2EORCCrs; break;
2391      }
2392      SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CC, CCR, Reg0, InFlag };
2393      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
2394    }
2395
2396    ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2397    if (T) {
2398      unsigned TrueImm = T->getZExtValue();
2399      if (is_t2_so_imm(TrueImm)) {
2400        unsigned Opc;
2401        switch (N->getOpcode()) {
2402        default: llvm_unreachable("Unexpected node");
2403        case ARMISD::CAND: Opc = ARM::t2ANDCCri; break;
2404        case ARMISD::COR:  Opc = ARM::t2ORRCCri; break;
2405        case ARMISD::CXOR: Opc = ARM::t2EORCCri; break;
2406        }
2407        SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2408        SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
2409        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2410      }
2411    }
2412
2413    unsigned Opc;
2414    switch (N->getOpcode()) {
2415    default: llvm_unreachable("Unexpected node");
2416    case ARMISD::CAND: Opc = ARM::t2ANDCCrr; break;
2417    case ARMISD::COR:  Opc = ARM::t2ORRCCrr; break;
2418    case ARMISD::CXOR: Opc = ARM::t2EORCCrr; break;
2419    }
2420    SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
2421    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2422  }
2423
2424  SDValue CPTmp0;
2425  SDValue CPTmp1;
2426  SDValue CPTmp2;
2427  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2428    unsigned Opc;
2429    switch (N->getOpcode()) {
2430    default: llvm_unreachable("Unexpected node");
2431    case ARMISD::CAND: Opc = ARM::ANDCCrsi; break;
2432    case ARMISD::COR:  Opc = ARM::ORRCCrsi; break;
2433    case ARMISD::CXOR: Opc = ARM::EORCCrsi; break;
2434    }
2435    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, Reg0, InFlag };
2436    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 7);
2437  }
2438
2439  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2440    unsigned Opc;
2441    switch (N->getOpcode()) {
2442    default: llvm_unreachable("Unexpected node");
2443    case ARMISD::CAND: Opc = ARM::ANDCCrsr; break;
2444    case ARMISD::COR:  Opc = ARM::ORRCCrsr; break;
2445    case ARMISD::CXOR: Opc = ARM::EORCCrsr; break;
2446    }
2447    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, Reg0, InFlag };
2448    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 8);
2449  }
2450
2451  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2452  if (T) {
2453    unsigned TrueImm = T->getZExtValue();
2454    if (is_so_imm(TrueImm)) {
2455      unsigned Opc;
2456      switch (N->getOpcode()) {
2457      default: llvm_unreachable("Unexpected node");
2458      case ARMISD::CAND: Opc = ARM::ANDCCri; break;
2459      case ARMISD::COR:  Opc = ARM::ORRCCri; break;
2460      case ARMISD::CXOR: Opc = ARM::EORCCri; break;
2461      }
2462      SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2463      SDValue Ops[] = { FalseVal, True, CC, CCR, Reg0, InFlag };
2464      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2465    }
2466  }
2467
2468  unsigned Opc;
2469  switch (N->getOpcode()) {
2470  default: llvm_unreachable("Unexpected node");
2471  case ARMISD::CAND: Opc = ARM::ANDCCrr; break;
2472  case ARMISD::COR:  Opc = ARM::ORRCCrr; break;
2473  case ARMISD::CXOR: Opc = ARM::EORCCrr; break;
2474  }
2475  SDValue Ops[] = { FalseVal, TrueVal, CC, CCR, Reg0, InFlag };
2476  return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 6);
2477}
2478
2479/// Target-specific DAG combining for ISD::XOR.
2480/// Target-independent combining lowers SELECT_CC nodes of the form
2481/// select_cc setg[ge] X,  0,  X, -X
2482/// select_cc setgt    X, -1,  X, -X
2483/// select_cc setl[te] X,  0, -X,  X
2484/// select_cc setlt    X,  1, -X,  X
2485/// which represent Integer ABS into:
2486/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2487/// ARM instruction selection detects the latter and matches it to
2488/// ARM::ABS or ARM::t2ABS machine node.
2489SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2490  SDValue XORSrc0 = N->getOperand(0);
2491  SDValue XORSrc1 = N->getOperand(1);
2492  EVT VT = N->getValueType(0);
2493
2494  if (DisableARMIntABS)
2495    return NULL;
2496
2497  if (Subtarget->isThumb1Only())
2498    return NULL;
2499
2500  if (XORSrc0.getOpcode() != ISD::ADD ||
2501    XORSrc1.getOpcode() != ISD::SRA)
2502    return NULL;
2503
2504  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2505  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2506  SDValue SRASrc0 = XORSrc1.getOperand(0);
2507  SDValue SRASrc1 = XORSrc1.getOperand(1);
2508  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2509  EVT XType = SRASrc0.getValueType();
2510  unsigned Size = XType.getSizeInBits() - 1;
2511
2512  if (ADDSrc1 == XORSrc1  &&
2513      ADDSrc0 == SRASrc0 &&
2514      XType.isInteger() &&
2515      SRAConstant != NULL &&
2516      Size == SRAConstant->getZExtValue()) {
2517
2518    unsigned Opcode = ARM::ABS;
2519    if (Subtarget->isThumb2())
2520      Opcode = ARM::t2ABS;
2521
2522    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2523  }
2524
2525  return NULL;
2526}
2527
2528SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2529  // The only time a CONCAT_VECTORS operation can have legal types is when
2530  // two 64-bit vectors are concatenated to a 128-bit vector.
2531  EVT VT = N->getValueType(0);
2532  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2533    llvm_unreachable("unexpected CONCAT_VECTORS");
2534  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2535}
2536
2537SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2538  SmallVector<SDValue, 6> Ops;
2539  Ops.push_back(Node->getOperand(1)); // Ptr
2540  Ops.push_back(Node->getOperand(2)); // Low part of Val1
2541  Ops.push_back(Node->getOperand(3)); // High part of Val1
2542  if (Opc == ARM::ATOMCMPXCHG6432) {
2543    Ops.push_back(Node->getOperand(4)); // Low part of Val2
2544    Ops.push_back(Node->getOperand(5)); // High part of Val2
2545  }
2546  Ops.push_back(Node->getOperand(0)); // Chain
2547  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2548  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2549  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2550                                           MVT::i32, MVT::i32, MVT::Other,
2551                                           Ops.data() ,Ops.size());
2552  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2553  return ResNode;
2554}
2555
2556SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2557  DebugLoc dl = N->getDebugLoc();
2558
2559  if (N->isMachineOpcode())
2560    return NULL;   // Already selected.
2561
2562  switch (N->getOpcode()) {
2563  default: break;
2564  case ISD::XOR: {
2565    // Select special operations if XOR node forms integer ABS pattern
2566    SDNode *ResNode = SelectABSOp(N);
2567    if (ResNode)
2568      return ResNode;
2569    // Other cases are autogenerated.
2570    break;
2571  }
2572  case ISD::Constant: {
2573    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2574    bool UseCP = true;
2575    if (Subtarget->hasThumb2())
2576      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2577      // be done with MOV + MOVT, at worst.
2578      UseCP = 0;
2579    else {
2580      if (Subtarget->isThumb()) {
2581        UseCP = (Val > 255 &&                          // MOV
2582                 ~Val > 255 &&                         // MOV + MVN
2583                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2584      } else
2585        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2586                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2587                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2588    }
2589
2590    if (UseCP) {
2591      SDValue CPIdx =
2592        CurDAG->getTargetConstantPool(ConstantInt::get(
2593                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2594                                      TLI.getPointerTy());
2595
2596      SDNode *ResNode;
2597      if (Subtarget->isThumb1Only()) {
2598        SDValue Pred = getAL(CurDAG);
2599        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2600        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2601        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2602                                         Ops, 4);
2603      } else {
2604        SDValue Ops[] = {
2605          CPIdx,
2606          CurDAG->getTargetConstant(0, MVT::i32),
2607          getAL(CurDAG),
2608          CurDAG->getRegister(0, MVT::i32),
2609          CurDAG->getEntryNode()
2610        };
2611        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2612                                       Ops, 5);
2613      }
2614      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2615      return NULL;
2616    }
2617
2618    // Other cases are autogenerated.
2619    break;
2620  }
2621  case ISD::FrameIndex: {
2622    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2623    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2624    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2625    if (Subtarget->isThumb1Only()) {
2626      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2627                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2628      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2629    } else {
2630      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2631                      ARM::t2ADDri : ARM::ADDri);
2632      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2633                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2634                        CurDAG->getRegister(0, MVT::i32) };
2635      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2636    }
2637  }
2638  case ISD::SRL:
2639    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2640      return I;
2641    break;
2642  case ISD::SRA:
2643    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2644      return I;
2645    break;
2646  case ISD::MUL:
2647    if (Subtarget->isThumb1Only())
2648      break;
2649    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2650      unsigned RHSV = C->getZExtValue();
2651      if (!RHSV) break;
2652      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2653        unsigned ShImm = Log2_32(RHSV-1);
2654        if (ShImm >= 32)
2655          break;
2656        SDValue V = N->getOperand(0);
2657        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2658        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2659        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2660        if (Subtarget->isThumb()) {
2661          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2662          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2663        } else {
2664          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2665          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2666        }
2667      }
2668      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2669        unsigned ShImm = Log2_32(RHSV+1);
2670        if (ShImm >= 32)
2671          break;
2672        SDValue V = N->getOperand(0);
2673        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2674        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2675        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2676        if (Subtarget->isThumb()) {
2677          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2678          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2679        } else {
2680          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2681          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2682        }
2683      }
2684    }
2685    break;
2686  case ISD::AND: {
2687    // Check for unsigned bitfield extract
2688    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2689      return I;
2690
2691    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2692    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2693    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2694    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2695    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2696    EVT VT = N->getValueType(0);
2697    if (VT != MVT::i32)
2698      break;
2699    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2700      ? ARM::t2MOVTi16
2701      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2702    if (!Opc)
2703      break;
2704    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2705    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2706    if (!N1C)
2707      break;
2708    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2709      SDValue N2 = N0.getOperand(1);
2710      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2711      if (!N2C)
2712        break;
2713      unsigned N1CVal = N1C->getZExtValue();
2714      unsigned N2CVal = N2C->getZExtValue();
2715      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2716          (N1CVal & 0xffffU) == 0xffffU &&
2717          (N2CVal & 0xffffU) == 0x0U) {
2718        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2719                                                  MVT::i32);
2720        SDValue Ops[] = { N0.getOperand(0), Imm16,
2721                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2722        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2723      }
2724    }
2725    break;
2726  }
2727  case ARMISD::VMOVRRD:
2728    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2729                                  N->getOperand(0), getAL(CurDAG),
2730                                  CurDAG->getRegister(0, MVT::i32));
2731  case ISD::UMUL_LOHI: {
2732    if (Subtarget->isThumb1Only())
2733      break;
2734    if (Subtarget->isThumb()) {
2735      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2736                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2737                        CurDAG->getRegister(0, MVT::i32) };
2738      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2739    } else {
2740      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2741                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2742                        CurDAG->getRegister(0, MVT::i32) };
2743      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2744                                    ARM::UMULL : ARM::UMULLv5,
2745                                    dl, MVT::i32, MVT::i32, Ops, 5);
2746    }
2747  }
2748  case ISD::SMUL_LOHI: {
2749    if (Subtarget->isThumb1Only())
2750      break;
2751    if (Subtarget->isThumb()) {
2752      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2753                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2754      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2755    } else {
2756      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2757                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2758                        CurDAG->getRegister(0, MVT::i32) };
2759      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2760                                    ARM::SMULL : ARM::SMULLv5,
2761                                    dl, MVT::i32, MVT::i32, Ops, 5);
2762    }
2763  }
2764  case ISD::LOAD: {
2765    SDNode *ResNode = 0;
2766    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2767      ResNode = SelectT2IndexedLoad(N);
2768    else
2769      ResNode = SelectARMIndexedLoad(N);
2770    if (ResNode)
2771      return ResNode;
2772    // Other cases are autogenerated.
2773    break;
2774  }
2775  case ARMISD::BRCOND: {
2776    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2777    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2778    // Pattern complexity = 6  cost = 1  size = 0
2779
2780    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2781    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2782    // Pattern complexity = 6  cost = 1  size = 0
2783
2784    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2785    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2786    // Pattern complexity = 6  cost = 1  size = 0
2787
2788    unsigned Opc = Subtarget->isThumb() ?
2789      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2790    SDValue Chain = N->getOperand(0);
2791    SDValue N1 = N->getOperand(1);
2792    SDValue N2 = N->getOperand(2);
2793    SDValue N3 = N->getOperand(3);
2794    SDValue InFlag = N->getOperand(4);
2795    assert(N1.getOpcode() == ISD::BasicBlock);
2796    assert(N2.getOpcode() == ISD::Constant);
2797    assert(N3.getOpcode() == ISD::Register);
2798
2799    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2800                               cast<ConstantSDNode>(N2)->getZExtValue()),
2801                               MVT::i32);
2802    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2803    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2804                                             MVT::Glue, Ops, 5);
2805    Chain = SDValue(ResNode, 0);
2806    if (N->getNumValues() == 2) {
2807      InFlag = SDValue(ResNode, 1);
2808      ReplaceUses(SDValue(N, 1), InFlag);
2809    }
2810    ReplaceUses(SDValue(N, 0),
2811                SDValue(Chain.getNode(), Chain.getResNo()));
2812    return NULL;
2813  }
2814  case ARMISD::CMOV:
2815    return SelectCMOVOp(N);
2816  case ARMISD::CAND:
2817  case ARMISD::COR:
2818  case ARMISD::CXOR:
2819    return SelectConditionalOp(N);
2820  case ARMISD::VZIP: {
2821    unsigned Opc = 0;
2822    EVT VT = N->getValueType(0);
2823    switch (VT.getSimpleVT().SimpleTy) {
2824    default: return NULL;
2825    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2826    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2827    case MVT::v2f32:
2828    // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2829    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2830    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2831    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2832    case MVT::v4f32:
2833    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2834    }
2835    SDValue Pred = getAL(CurDAG);
2836    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2837    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2838    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2839  }
2840  case ARMISD::VUZP: {
2841    unsigned Opc = 0;
2842    EVT VT = N->getValueType(0);
2843    switch (VT.getSimpleVT().SimpleTy) {
2844    default: return NULL;
2845    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2846    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2847    case MVT::v2f32:
2848    // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2849    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2850    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2851    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2852    case MVT::v4f32:
2853    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2854    }
2855    SDValue Pred = getAL(CurDAG);
2856    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2857    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2858    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2859  }
2860  case ARMISD::VTRN: {
2861    unsigned Opc = 0;
2862    EVT VT = N->getValueType(0);
2863    switch (VT.getSimpleVT().SimpleTy) {
2864    default: return NULL;
2865    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2866    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2867    case MVT::v2f32:
2868    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2869    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2870    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2871    case MVT::v4f32:
2872    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2873    }
2874    SDValue Pred = getAL(CurDAG);
2875    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2876    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2877    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2878  }
2879  case ARMISD::BUILD_VECTOR: {
2880    EVT VecVT = N->getValueType(0);
2881    EVT EltVT = VecVT.getVectorElementType();
2882    unsigned NumElts = VecVT.getVectorNumElements();
2883    if (EltVT == MVT::f64) {
2884      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2885      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2886    }
2887    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2888    if (NumElts == 2)
2889      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2890    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2891    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2892                     N->getOperand(2), N->getOperand(3));
2893  }
2894
2895  case ARMISD::VLD2DUP: {
2896    unsigned Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2897                           ARM::VLD2DUPd32 };
2898    return SelectVLDDup(N, false, 2, Opcodes);
2899  }
2900
2901  case ARMISD::VLD3DUP: {
2902    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2903                           ARM::VLD3DUPd32Pseudo };
2904    return SelectVLDDup(N, false, 3, Opcodes);
2905  }
2906
2907  case ARMISD::VLD4DUP: {
2908    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2909                           ARM::VLD4DUPd32Pseudo };
2910    return SelectVLDDup(N, false, 4, Opcodes);
2911  }
2912
2913  case ARMISD::VLD2DUP_UPD: {
2914    unsigned Opcodes[] = { ARM::VLD2DUPd8wb_fixed, ARM::VLD2DUPd16wb_fixed,
2915                           ARM::VLD2DUPd32wb_fixed };
2916    return SelectVLDDup(N, true, 2, Opcodes);
2917  }
2918
2919  case ARMISD::VLD3DUP_UPD: {
2920    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2921                           ARM::VLD3DUPd32Pseudo_UPD };
2922    return SelectVLDDup(N, true, 3, Opcodes);
2923  }
2924
2925  case ARMISD::VLD4DUP_UPD: {
2926    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2927                           ARM::VLD4DUPd32Pseudo_UPD };
2928    return SelectVLDDup(N, true, 4, Opcodes);
2929  }
2930
2931  case ARMISD::VLD1_UPD: {
2932    unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
2933                            ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2934    unsigned QOpcodes[] = { ARM::VLD1q8wb_fixed,
2935                            ARM::VLD1q16wb_fixed,
2936                            ARM::VLD1q32wb_fixed,
2937                            ARM::VLD1q64wb_fixed };
2938    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2939  }
2940
2941  case ARMISD::VLD2_UPD: {
2942    unsigned DOpcodes[] = { ARM::VLD2d8wb_fixed,
2943                            ARM::VLD2d16wb_fixed,
2944                            ARM::VLD2d32wb_fixed,
2945                            ARM::VLD1q64wb_fixed};
2946    unsigned QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2947                            ARM::VLD2q16PseudoWB_fixed,
2948                            ARM::VLD2q32PseudoWB_fixed };
2949    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2950  }
2951
2952  case ARMISD::VLD3_UPD: {
2953    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2954                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64wb_fixed};
2955    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2956                             ARM::VLD3q16Pseudo_UPD,
2957                             ARM::VLD3q32Pseudo_UPD };
2958    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2959                             ARM::VLD3q16oddPseudo_UPD,
2960                             ARM::VLD3q32oddPseudo_UPD };
2961    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2962  }
2963
2964  case ARMISD::VLD4_UPD: {
2965    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2966                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64wb_fixed};
2967    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2968                             ARM::VLD4q16Pseudo_UPD,
2969                             ARM::VLD4q32Pseudo_UPD };
2970    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2971                             ARM::VLD4q16oddPseudo_UPD,
2972                             ARM::VLD4q32oddPseudo_UPD };
2973    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2974  }
2975
2976  case ARMISD::VLD2LN_UPD: {
2977    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2978                            ARM::VLD2LNd32Pseudo_UPD };
2979    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2980                            ARM::VLD2LNq32Pseudo_UPD };
2981    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2982  }
2983
2984  case ARMISD::VLD3LN_UPD: {
2985    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2986                            ARM::VLD3LNd32Pseudo_UPD };
2987    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2988                            ARM::VLD3LNq32Pseudo_UPD };
2989    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2990  }
2991
2992  case ARMISD::VLD4LN_UPD: {
2993    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2994                            ARM::VLD4LNd32Pseudo_UPD };
2995    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2996                            ARM::VLD4LNq32Pseudo_UPD };
2997    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2998  }
2999
3000  case ARMISD::VST1_UPD: {
3001    unsigned DOpcodes[] = { ARM::VST1d8wb_fixed, ARM::VST1d16wb_fixed,
3002                            ARM::VST1d32wb_fixed, ARM::VST1d64wb_fixed };
3003    unsigned QOpcodes[] = { ARM::VST1q8wb_fixed,
3004                            ARM::VST1q16wb_fixed,
3005                            ARM::VST1q32wb_fixed,
3006                            ARM::VST1q64wb_fixed };
3007    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
3008  }
3009
3010  case ARMISD::VST2_UPD: {
3011    unsigned DOpcodes[] = { ARM::VST2d8wb_fixed,
3012                            ARM::VST2d16wb_fixed,
3013                            ARM::VST2d32wb_fixed,
3014                            ARM::VST1q64wb_fixed};
3015    unsigned QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
3016                            ARM::VST2q16PseudoWB_fixed,
3017                            ARM::VST2q32PseudoWB_fixed };
3018    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
3019  }
3020
3021  case ARMISD::VST3_UPD: {
3022    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
3023                            ARM::VST3d32Pseudo_UPD,ARM::VST1d64TPseudoWB_fixed};
3024    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3025                             ARM::VST3q16Pseudo_UPD,
3026                             ARM::VST3q32Pseudo_UPD };
3027    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
3028                             ARM::VST3q16oddPseudo_UPD,
3029                             ARM::VST3q32oddPseudo_UPD };
3030    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
3031  }
3032
3033  case ARMISD::VST4_UPD: {
3034    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
3035                            ARM::VST4d32Pseudo_UPD,ARM::VST1d64QPseudoWB_fixed};
3036    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3037                             ARM::VST4q16Pseudo_UPD,
3038                             ARM::VST4q32Pseudo_UPD };
3039    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
3040                             ARM::VST4q16oddPseudo_UPD,
3041                             ARM::VST4q32oddPseudo_UPD };
3042    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
3043  }
3044
3045  case ARMISD::VST2LN_UPD: {
3046    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
3047                            ARM::VST2LNd32Pseudo_UPD };
3048    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
3049                            ARM::VST2LNq32Pseudo_UPD };
3050    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
3051  }
3052
3053  case ARMISD::VST3LN_UPD: {
3054    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
3055                            ARM::VST3LNd32Pseudo_UPD };
3056    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
3057                            ARM::VST3LNq32Pseudo_UPD };
3058    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
3059  }
3060
3061  case ARMISD::VST4LN_UPD: {
3062    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
3063                            ARM::VST4LNd32Pseudo_UPD };
3064    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3065                            ARM::VST4LNq32Pseudo_UPD };
3066    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3067  }
3068
3069  case ISD::INTRINSIC_VOID:
3070  case ISD::INTRINSIC_W_CHAIN: {
3071    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3072    switch (IntNo) {
3073    default:
3074      break;
3075
3076    case Intrinsic::arm_ldrexd: {
3077      SDValue MemAddr = N->getOperand(2);
3078      DebugLoc dl = N->getDebugLoc();
3079      SDValue Chain = N->getOperand(0);
3080
3081      unsigned NewOpc = ARM::LDREXD;
3082      if (Subtarget->isThumb() && Subtarget->hasThumb2())
3083        NewOpc = ARM::t2LDREXD;
3084
3085      // arm_ldrexd returns a i64 value in {i32, i32}
3086      std::vector<EVT> ResTys;
3087      ResTys.push_back(MVT::i32);
3088      ResTys.push_back(MVT::i32);
3089      ResTys.push_back(MVT::Other);
3090
3091      // place arguments in the right order
3092      SmallVector<SDValue, 7> Ops;
3093      Ops.push_back(MemAddr);
3094      Ops.push_back(getAL(CurDAG));
3095      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3096      Ops.push_back(Chain);
3097      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3098                                          Ops.size());
3099      // Transfer memoperands.
3100      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3101      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3102      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3103
3104      // Until there's support for specifing explicit register constraints
3105      // like the use of even/odd register pair, hardcode ldrexd to always
3106      // use the pair [R0, R1] to hold the load result.
3107      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
3108                                   SDValue(Ld, 0), SDValue(0,0));
3109      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
3110                                   SDValue(Ld, 1), Chain.getValue(1));
3111
3112      // Remap uses.
3113      SDValue Glue = Chain.getValue(1);
3114      if (!SDValue(N, 0).use_empty()) {
3115        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3116                                                ARM::R0, MVT::i32, Glue);
3117        Glue = Result.getValue(2);
3118        ReplaceUses(SDValue(N, 0), Result);
3119      }
3120      if (!SDValue(N, 1).use_empty()) {
3121        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3122                                                ARM::R1, MVT::i32, Glue);
3123        Glue = Result.getValue(2);
3124        ReplaceUses(SDValue(N, 1), Result);
3125      }
3126
3127      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
3128      return NULL;
3129    }
3130
3131    case Intrinsic::arm_strexd: {
3132      DebugLoc dl = N->getDebugLoc();
3133      SDValue Chain = N->getOperand(0);
3134      SDValue Val0 = N->getOperand(2);
3135      SDValue Val1 = N->getOperand(3);
3136      SDValue MemAddr = N->getOperand(4);
3137
3138      // Until there's support for specifing explicit register constraints
3139      // like the use of even/odd register pair, hardcode strexd to always
3140      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
3141      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
3142                                   SDValue(0, 0));
3143      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
3144
3145      SDValue Glue = Chain.getValue(1);
3146      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3147                                    ARM::R2, MVT::i32, Glue);
3148      Glue = Val0.getValue(1);
3149      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
3150                                    ARM::R3, MVT::i32, Glue);
3151
3152      // Store exclusive double return a i32 value which is the return status
3153      // of the issued store.
3154      std::vector<EVT> ResTys;
3155      ResTys.push_back(MVT::i32);
3156      ResTys.push_back(MVT::Other);
3157
3158      // place arguments in the right order
3159      SmallVector<SDValue, 7> Ops;
3160      Ops.push_back(Val0);
3161      Ops.push_back(Val1);
3162      Ops.push_back(MemAddr);
3163      Ops.push_back(getAL(CurDAG));
3164      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3165      Ops.push_back(Chain);
3166
3167      unsigned NewOpc = ARM::STREXD;
3168      if (Subtarget->isThumb() && Subtarget->hasThumb2())
3169        NewOpc = ARM::t2STREXD;
3170
3171      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3172                                          Ops.size());
3173      // Transfer memoperands.
3174      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3175      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3176      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3177
3178      return St;
3179    }
3180
3181    case Intrinsic::arm_neon_vld1: {
3182      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3183                              ARM::VLD1d32, ARM::VLD1d64 };
3184      unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3185                              ARM::VLD1q32, ARM::VLD1q64};
3186      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3187    }
3188
3189    case Intrinsic::arm_neon_vld2: {
3190      unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3191                              ARM::VLD2d32, ARM::VLD1q64 };
3192      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3193                              ARM::VLD2q32Pseudo };
3194      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3195    }
3196
3197    case Intrinsic::arm_neon_vld3: {
3198      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3199                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3200      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3201                               ARM::VLD3q16Pseudo_UPD,
3202                               ARM::VLD3q32Pseudo_UPD };
3203      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3204                               ARM::VLD3q16oddPseudo,
3205                               ARM::VLD3q32oddPseudo };
3206      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3207    }
3208
3209    case Intrinsic::arm_neon_vld4: {
3210      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3211                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3212      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3213                               ARM::VLD4q16Pseudo_UPD,
3214                               ARM::VLD4q32Pseudo_UPD };
3215      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3216                               ARM::VLD4q16oddPseudo,
3217                               ARM::VLD4q32oddPseudo };
3218      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3219    }
3220
3221    case Intrinsic::arm_neon_vld2lane: {
3222      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3223                              ARM::VLD2LNd32Pseudo };
3224      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3225      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3226    }
3227
3228    case Intrinsic::arm_neon_vld3lane: {
3229      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3230                              ARM::VLD3LNd32Pseudo };
3231      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3232      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3233    }
3234
3235    case Intrinsic::arm_neon_vld4lane: {
3236      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3237                              ARM::VLD4LNd32Pseudo };
3238      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3239      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3240    }
3241
3242    case Intrinsic::arm_neon_vst1: {
3243      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3244                              ARM::VST1d32, ARM::VST1d64 };
3245      unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3246                              ARM::VST1q32, ARM::VST1q64 };
3247      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3248    }
3249
3250    case Intrinsic::arm_neon_vst2: {
3251      unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3252                              ARM::VST2d32, ARM::VST1q64 };
3253      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3254                              ARM::VST2q32Pseudo };
3255      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3256    }
3257
3258    case Intrinsic::arm_neon_vst3: {
3259      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3260                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3261      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3262                               ARM::VST3q16Pseudo_UPD,
3263                               ARM::VST3q32Pseudo_UPD };
3264      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3265                               ARM::VST3q16oddPseudo,
3266                               ARM::VST3q32oddPseudo };
3267      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3268    }
3269
3270    case Intrinsic::arm_neon_vst4: {
3271      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3272                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3273      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3274                               ARM::VST4q16Pseudo_UPD,
3275                               ARM::VST4q32Pseudo_UPD };
3276      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3277                               ARM::VST4q16oddPseudo,
3278                               ARM::VST4q32oddPseudo };
3279      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3280    }
3281
3282    case Intrinsic::arm_neon_vst2lane: {
3283      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3284                              ARM::VST2LNd32Pseudo };
3285      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3286      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3287    }
3288
3289    case Intrinsic::arm_neon_vst3lane: {
3290      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3291                              ARM::VST3LNd32Pseudo };
3292      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3293      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3294    }
3295
3296    case Intrinsic::arm_neon_vst4lane: {
3297      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3298                              ARM::VST4LNd32Pseudo };
3299      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3300      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3301    }
3302    }
3303    break;
3304  }
3305
3306  case ISD::INTRINSIC_WO_CHAIN: {
3307    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3308    switch (IntNo) {
3309    default:
3310      break;
3311
3312    case Intrinsic::arm_neon_vtbl2:
3313      return SelectVTBL(N, false, 2, ARM::VTBL2);
3314    case Intrinsic::arm_neon_vtbl3:
3315      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3316    case Intrinsic::arm_neon_vtbl4:
3317      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3318
3319    case Intrinsic::arm_neon_vtbx2:
3320      return SelectVTBL(N, true, 2, ARM::VTBX2);
3321    case Intrinsic::arm_neon_vtbx3:
3322      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3323    case Intrinsic::arm_neon_vtbx4:
3324      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3325    }
3326    break;
3327  }
3328
3329  case ARMISD::VTBL1: {
3330    DebugLoc dl = N->getDebugLoc();
3331    EVT VT = N->getValueType(0);
3332    SmallVector<SDValue, 6> Ops;
3333
3334    Ops.push_back(N->getOperand(0));
3335    Ops.push_back(N->getOperand(1));
3336    Ops.push_back(getAL(CurDAG));                    // Predicate
3337    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3338    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3339  }
3340  case ARMISD::VTBL2: {
3341    DebugLoc dl = N->getDebugLoc();
3342    EVT VT = N->getValueType(0);
3343
3344    // Form a REG_SEQUENCE to force register allocation.
3345    SDValue V0 = N->getOperand(0);
3346    SDValue V1 = N->getOperand(1);
3347    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3348
3349    SmallVector<SDValue, 6> Ops;
3350    Ops.push_back(RegSeq);
3351    Ops.push_back(N->getOperand(2));
3352    Ops.push_back(getAL(CurDAG));                    // Predicate
3353    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3354    return CurDAG->getMachineNode(ARM::VTBL2, dl, VT,
3355                                  Ops.data(), Ops.size());
3356  }
3357
3358  case ISD::CONCAT_VECTORS:
3359    return SelectConcatVector(N);
3360
3361  case ARMISD::ATOMOR64_DAG:
3362    return SelectAtomic64(N, ARM::ATOMOR6432);
3363  case ARMISD::ATOMXOR64_DAG:
3364    return SelectAtomic64(N, ARM::ATOMXOR6432);
3365  case ARMISD::ATOMADD64_DAG:
3366    return SelectAtomic64(N, ARM::ATOMADD6432);
3367  case ARMISD::ATOMSUB64_DAG:
3368    return SelectAtomic64(N, ARM::ATOMSUB6432);
3369  case ARMISD::ATOMNAND64_DAG:
3370    return SelectAtomic64(N, ARM::ATOMNAND6432);
3371  case ARMISD::ATOMAND64_DAG:
3372    return SelectAtomic64(N, ARM::ATOMAND6432);
3373  case ARMISD::ATOMSWAP64_DAG:
3374    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3375  case ARMISD::ATOMCMPXCHG64_DAG:
3376    return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3377  }
3378
3379  return SelectCode(N);
3380}
3381
3382bool ARMDAGToDAGISel::
3383SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3384                             std::vector<SDValue> &OutOps) {
3385  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3386  // Require the address to be in a register.  That is safe for all ARM
3387  // variants and it is hard to do anything much smarter without knowing
3388  // how the operand is used.
3389  OutOps.push_back(Op);
3390  return false;
3391}
3392
3393/// createARMISelDag - This pass converts a legalized DAG into a
3394/// ARM-specific DAG, ready for instruction scheduling.
3395///
3396FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3397                                     CodeGenOpt::Level OptLevel) {
3398  return new ARMDAGToDAGISel(TM, OptLevel);
3399}
3400