/external/llvm/lib/Target/PTX/ |
H A D | PTXTargetMachine.cpp | 110 PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM) argument 111 : TargetPassConfig(TM, PM) {}
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H A D | PTXISelDAGToDAG.cpp | 30 PTXDAGToDAGISel(PTXTargetMachine &TM, CodeGenOpt::Level OptLevel); 65 FunctionPass *llvm::createPTXISelDag(PTXTargetMachine &TM, argument 67 return new PTXDAGToDAGISel(TM, OptLevel); 70 PTXDAGToDAGISel::PTXDAGToDAGISel(PTXTargetMachine &TM, argument 72 : SelectionDAGISel(TM, OptLevel) {} 354 return TM.getSubtarget<PTXSubtarget>();
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCCodeEmitter.cpp | 31 TargetMachine &TM; member in class:__anon7645::PPCCodeEmitter 48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {} 88 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM, argument 90 return new PPCCodeEmitter(TM, JCE); 129 assert(TM.getRelocationModel() == Reloc::PIC_); 155 if (TM.getRelocationModel() == Reloc::PIC_) {
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H A D | PPCInstrInfo.cpp | 45 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 50 const TargetMachine *TM, 52 unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective(); 54 const InstrItineraryData *II = TM->getInstrItineraryData(); 58 return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG); 66 unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective(); 70 const TargetInstrInfo *TII = TM.getInstrInfo(); 400 if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) || 401 (!DisablePPC64RS && TM 49 CreateTargetHazardRecognizer( const TargetMachine *TM, const ScheduleDAG *DAG) const argument [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 41 TargetMachine &TM; member in struct:__anon7652::Filler 46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { } 285 for (const uint16_t *Alias = TM.getRegisterInfo()->getAliasSet(Reg);
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H A D | FPMover.cpp | 35 TargetMachine &TM; member in struct:__anon7653::FPMover 39 : MachineFunctionPass(ID), TM(tm) { } 105 const TargetInstrInfo *TII = TM.getInstrInfo(); 120 MI = BuildMI(MBB, I, dl, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg) 133 if (TM.getSubtarget<SparcSubtarget>().isV9())
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H A D | SparcAsmPrinter.cpp | 33 explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 34 : AsmPrinter(TM, Streamer) {}
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H A D | SparcISelDAGToDAG.cpp | 36 SparcTargetMachine& TM; member in class:__anon7655::SparcDAGToDAGISel 41 TM(tm) { 69 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF); 209 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) { argument 210 return new SparcDAGToDAGISel(TM);
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/external/llvm/lib/Target/ |
H A D | TargetLoweringObjectFile.cpp | 41 const TargetMachine &TM) { 43 InitMCObjectFileInfo(TM.getTargetTriple(), 44 TM.getRelocationModel(), TM.getCodeModel(), *Ctx); 107 const TargetMachine &TM, 113 /// a global variable. Given an global variable and information from TM, it 118 const TargetMachine &TM){ 122 Reloc::Model ReloModel = TM.getRelocationModel(); 131 if (isSuitableForBSS(GVar, TM.Options.NoZerosInBSS)) 141 if (isSuitableForBSS(GVar, TM 40 Initialize(MCContext &ctx, const TargetMachine &TM) argument 106 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument 117 getKindForGlobal(const GlobalValue *GV, const TargetMachine &TM) argument [all...] |
H A D | TargetMachineC.cpp | 154 TargetMachine* TM = unwrap(T); local 161 const TargetData* td = TM->getTargetData(); 186 if (TM->addPassesToEmitFile(pass, destf, ft)) {
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/external/clang/lib/CodeGen/ |
H A D | BackendUtil.cpp | 349 TargetMachine *TM = TheTarget->createTargetMachine(Triple, TargetOpts.CPU, local 354 TM->setMCRelaxAll(true); 356 TM->setMCSaveTempLabels(true); 358 TM->setMCUseCFI(false); 360 TM->setMCUseDwarfDirectory(true); 362 TM->setMCNoExecStack(true); 390 if (TM->addPassesToEmitFile(*PM, OS, CGFT,
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/external/llvm/lib/CodeGen/ |
H A D | GCStrategy.cpp | 68 const TargetMachine *TM; member in class:__anon7350::GCMachineCodeAnalysis 387 const TargetFrameLowering *TFI = TM->getFrameLowering(); 404 TM = &MF.getTarget(); 406 TII = TM->getInstrInfo();
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H A D | MachineRegisterInfo.cpp | 66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument 67 const TargetInstrInfo *TII = TM.getInstrInfo();
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H A D | PeepholeOptimizer.cpp | 75 const TargetMachine *TM; member in class:__anon7381::PeepholeOptimizer 400 TM = &MF.getTarget(); 401 TII = TM->getInstrInfo();
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H A D | RegisterScavenging.cpp | 78 const TargetMachine &TM = MF.getTarget(); local 79 TII = TM.getInstrInfo(); 80 TRI = TM.getRegisterInfo();
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H A D | TargetLoweringObjectFileImpl.cpp | 65 const TargetMachine &TM, 80 unsigned Size = TM.getTargetData()->getPointerSize(); 82 Streamer.EmitValueToAlignment(TM.getTargetData()->getPointerABIAlignment()); 175 Mangler *Mang, const TargetMachine &TM) const { 208 Mangler *Mang, const TargetMachine &TM) const { 213 EmitUniquedSection = TM.getFunctionSections(); 215 EmitUniquedSection = TM.getDataSections(); 249 TM.getTargetData()->getPreferredAlignment(cast<GlobalVariable>(GV)); 380 Mangler *Mang, const TargetMachine &TM) const { 433 Mangler *Mang, const TargetMachine &TM) cons 64 emitPersonalityValue(MCStreamer &Streamer, const TargetMachine &TM, const MCSymbol *Sym) const argument [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 253 const TargetMachine &TM = Fn.getTarget(); local 255 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo()); 256 TRI = TM.getRegisterInfo();
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 57 TM(tm), 58 RI(*TM.getSubtargetImpl(), *this) 64 const TargetMachine *TM, 66 const TargetInstrInfo *TII = TM->getInstrInfo(); 63 CreateTargetHazardRecognizer( const TargetMachine *TM, const ScheduleDAG *DAG) const argument
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeAsmPrinter.cpp | 52 explicit MBlazeAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) argument 53 : AsmPrinter(TM, Streamer) { 54 Subtarget = &TM.getSubtarget<MBlazeSubtarget>(); 126 const TargetFrameLowering *TFI = TM.getFrameLowering(); 127 const TargetRegisterInfo &RI = *TM.getRegisterInfo(); 158 const TargetRegisterInfo &RI = *TM.getRegisterInfo();
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H A D | MBlazeDelaySlotFiller.cpp | 41 TargetMachine &TM; member in struct:__anon7599::Filler 46 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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H A D | MBlazeInstrInfo.h | 170 MBlazeTargetMachine &TM; member in class:llvm::MBlazeInstrInfo 173 explicit MBlazeInstrInfo(MBlazeTargetMachine &TM);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 97 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) argument 98 : SelectionDAGISel(TM, OptLevel), 99 Lowering(*TM.getTargetLowering()), 100 Subtarget(*TM.getSubtargetImpl()) { } 130 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM, argument 132 return new MSP430DAGToDAGISel(TM, OptLevel);
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/external/llvm/lib/Target/Mips/ |
H A D | MipsCodeEmitter.cpp | 53 TargetMachine &TM; member in class:__anon7622::MipsCodeEmitter 70 TD(tm.getTargetData()), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), 71 IsPIC(TM.getRelocationModel() == Reloc::PIC_) { 133 Subtarget = &TM.getSubtarget<MipsSubtarget> (); 422 FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM, argument 424 return new MipsCodeEmitter(TM, JCE);
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/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 47 X86TargetMachine &TM; member in class:__anon7696::Emitter 56 : MachineFunctionPass(ID), II(0), TD(0), TM(tm), 58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 61 : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm), 63 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 109 FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, argument 111 return new Emitter<JITCodeEmitter>(TM, JCE); 119 II = TM.getInstrInfo(); 120 TD = TM.getTargetData(); 121 Is64BitMode = TM [all...] |
H A D | X86InstrInfo.h | 128 X86TargetMachine &TM; member in class:llvm::X86InstrInfo
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