Searched refs:R0 (Results 51 - 58 of 58) sorted by relevance
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/external/libvpx/vp8/common/ppc/ |
H A D | filter_altivec.asm | 17 .macro load_c V, LABEL, OFF, R0, R1 18 lis \R0, \LABEL@ha 19 la \R1, \LABEL@l(\R0)
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 939 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 987 // Otherwise, do it the hard way, using R0 as the base register. 988 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 1051 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, 4770 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5133 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0; 5613 case 'r': // R0-R31
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/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 89 ARM::R0, ARM::R1, ARM::R2, ARM::R3 668 setExceptionPointerRegister(ARM::R0); 1652 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 2522 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 5667 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5671 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5678 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5684 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
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H A D | ARMISelDAGToDAG.cpp | 3106 // use the pair [R0, R1] to hold the load result. 3107 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0, 3116 ARM::R0, MVT::i32, Glue);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1156 XCore::R0, XCore::R1, XCore::R2, XCore::R3
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/external/valgrind/main/memcheck/ |
H A D | mc_machine.c | 834 if (o == GOF(R0) && sz == 4) return o;
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 856 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 897 Register = ARM::R0;
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2447 .Case("a1", ARM::R0) 2786 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2793 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
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