| /external/clang/test/CodeGen/ |
| H A D | mips64-class-return.cpp | 7 class D0 : public B0 { class in inherits:B0
23 extern D0 gd0;
28 D0 foo1(void) {
42 // CHECK: define void @_Z4foo42D0(%class.D0* nocapture byval %a0)
43 void foo4(D0 a0) {
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| /external/llvm/test/MC/MachO/ |
| H A D | x86_32-symbols.s | 5 D0: label
701 // CHECK: ('_string', 'D0')
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| H A D | x86_64-symbols.s | 5 D0: label
658 // CHECK: ('_string', 'D0')
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVarargsCallingConvention.h | 66 Hexagon::D0, Hexagon::D1, Hexagon::D2
122 Hexagon::D0, Hexagon::D1, Hexagon::D2
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| H A D | HexagonCallingConvLower.cpp | 110 unsigned Reg = Hexagon::D0;
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| H A D | HexagonISelLowering.cpp | 179 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
251 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMExpandPseudoInsts.cpp | 351 const TargetRegisterInfo *TRI, unsigned &D0,
354 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
359 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
365 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
389 unsigned D0, D1, D2, D3; local
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
463 unsigned D0, D1, D2, D3; local
464 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
465 MIB.addReg(D0);
350 GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3) argument
593 unsigned D0, D1, D2, D3; local
960 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); local
991 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); local
[all...] |
| H A D | ARMBaseRegisterInfo.cpp | 613 case ARM::D1: return ARM::D0;
666 case ARM::D0: return ARM::D1;
|
| /external/speex/libspeex/ |
| H A D | math_approx.h | 245 #define D0 16384 macro
260 frac = ADD16(D0, MULT16_16_Q14(frac, ADD16(D1, MULT16_16_Q14(frac, ADD16(D2 , MULT16_16_Q14(D3,frac))))));
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| /external/llvm/lib/Target/Sparc/ |
| H A D | FPMover.cpp | 71 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8,
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMBaseInfo.h | 155 case R0: case S0: case D0: case Q0: return 0;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsBaseInfo.h | 120 case Mips::D0:
|
| /external/qemu/target-mips/ |
| H A D | helper.c | 88 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
91 if (n ? tlb->D1 : tlb->D0)
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| H A D | machine.c | 68 (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
227 env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
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| H A D | cpu.h | 34 uint_fast16_t D0:1; member in struct:r4k_tlb_t
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| /external/valgrind/main/memcheck/ |
| H A D | mc_machine.c | 878 if (o >= GOF(D0) && o+sz <= GOF(D0) +SZB(D0)) return GOF(D0);
914 if (o >= GOF(D0) && o+sz <= GOF(D0) +2*SZB(D0)) return GOF(D0); // Q0
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| /external/icu4c/data/sprep/ |
| H A D | rfc3491.txt | 502 00D0; 00F0; MAP
625 01CF; 01D0; MAP
715 03D0; 03B2; MAP
838 04D0; 04D1; MAP
1230 24B6; 24D0; MAP
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| H A D | rfc3530csci.txt | 501 00D0; 00F0; MAP
624 01CF; 01D0; MAP
714 03D0; 03B2; MAP
837 04D0; 04D1; MAP
1229 24B6; 24D0; MAP
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| H A D | rfc3722.txt | 502 00D0; 00F0; MAP
625 01CF; 01D0; MAP
715 03D0; 03B2; MAP
838 04D0; 04D1; MAP
1230 24B6; 24D0; MAP
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| H A D | rfc3920node.txt | 502 00D0; 00F0; MAP
625 01CF; 01D0; MAP
715 03D0; 03B2; MAP
838 04D0; 04D1; MAP
1230 24B6; 24D0; MAP
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| H A D | rfc4518ci.txt | 469 00D0; 00F0; MAP
592 01CF; 01D0; MAP
682 03D0; 03B2; MAP
805 04D0; 04D1; MAP
1197 24B6; 24D0; MAP
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| /external/icu4c/test/testdata/ |
| H A D | nfs4_cis_prep.txt | 492 00D0; 00F0; MAP
615 01CF; 01D0; MAP
705 03D0; 03B2; MAP
828 04D0; 04D1; MAP
1220 24B6; 24D0; MAP
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| H A D | nfs4_cs_prep_ci.txt | 492 00D0; 00F0; MAP
615 01CF; 01D0; MAP
705 03D0; 03B2; MAP
828 04D0; 04D1; MAP
1220 24B6; 24D0; MAP
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| H A D | nfs4_mixed_prep_s.txt | 492 00D0; 00F0; MAP
615 01CF; 01D0; MAP
705 03D0; 03B2; MAP
828 04D0; 04D1; MAP
1220 24B6; 24D0; MAP
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 141 Mips::D0, Mips::D1, Mips::D2, Mips::D3,
|