/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 28 namespace RegState { namespace in namespace:llvm 63 flags & RegState::Define, 64 flags & RegState::Implicit, 65 flags & RegState::Kill, 66 flags & RegState::Dead, 67 flags & RegState::Undef, 68 flags & RegState::EarlyClobber, 70 flags & RegState::Debug)); 201 .addReg(DestReg, RegState::Define); 215 return MachineInstrBuilder(MI).addReg(DestReg, RegState [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 219 .addReg(StackReg, RegState::Kill) 226 .addReg(TmpReg, RegState::Kill) 229 .addReg(StackReg, RegState::Kill) 325 .addReg(Reg, RegState::Kill) 326 .addReg(PPC::X1, RegState::Define) 330 .addReg(PPC::X0, RegState::Kill) 331 .addReg(PPC::X1, RegState::Define) 343 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 346 .addReg(Reg, RegState::Kill) 347 .addReg(PPC::R1, RegState [all...] |
H A D | PPCFrameLowering.cpp | 141 .addReg(SrcReg, RegState::Kill) 150 .addReg(SrcReg, RegState::Kill) 159 .addReg(SrcReg, RegState::Kill) 163 .addReg(DstReg, RegState::Kill) 367 .addReg(PPC::R0, RegState::Kill) 370 .addReg(PPC::R1, RegState::Kill) 371 .addReg(PPC::R1, RegState::Define) 382 .addReg(PPC::R0, RegState::Kill) 385 .addReg(PPC::R1, RegState::Kill) 386 .addReg(PPC::R1, RegState [all...] |
H A D | PPCInstrInfo.cpp | 161 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 621 .addReg(Reg, RegState::Debug).addImm(Offset) 655 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 1164 .addReg(Op0, Op0IsKill * RegState::Kill); 1167 .addReg(Op0, Op0IsKill * RegState::Kill); 1184 .addReg(Op0, Op0IsKill * RegState::Kill) 1185 .addReg(Op1, Op1IsKill * RegState::Kill); 1188 .addReg(Op0, Op0IsKill * RegState::Kill) 1189 .addReg(Op1, Op1IsKill * RegState::Kill); 1206 .addReg(Op0, Op0IsKill * RegState::Kill) 1207 .addReg(Op1, Op1IsKill * RegState [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.cpp | 122 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags); 134 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); 136 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); 244 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); 247 .addReg(BaseReg, RegState::Kill)) 292 .addReg(DestReg, RegState::Kill) 361 .addReg(DestReg, RegState::Kill)); 560 .addReg(ARM::R12, RegState::Define) 561 .addReg(Reg, RegState::Kill)); 590 addReg(Reg, RegState [all...] |
H A D | ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 521 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 523 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 525 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 527 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 569 MIB.addReg(DstReg, RegState [all...] |
H A D | ARMFrameLowering.cpp | 292 .addReg(ARM::SP, RegState::Kill) 302 .addReg(ARM::SP, RegState::Kill)); 305 .addReg(ARM::R4, RegState::Kill) 308 .addReg(ARM::R4, RegState::Kill)); 450 addReg(JumpTarget.getReg(), RegState::Kill); 698 .addReg(ARM::SP, RegState::Define) 771 .addReg(ARM::R4, RegState::Kill) 797 .addReg(ARM::R4, RegState::Kill).addImm(16) 799 .addReg(SupReg, RegState::ImplicitKill)); 815 .addReg(SupReg, RegState [all...] |
H A D | Thumb2InstrInfo.cpp | 209 .addReg(BaseReg, RegState::Kill) 210 .addReg(DestReg, RegState::Kill) 215 .addReg(DestReg, RegState::Kill) 216 .addReg(BaseReg, RegState::Kill) 281 .addReg(BaseReg, RegState::Kill)
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H A D | ARMFastISel.cpp | 305 .addReg(Op0, Op0IsKill * RegState::Kill)); 308 .addReg(Op0, Op0IsKill * RegState::Kill)); 325 .addReg(Op0, Op0IsKill * RegState::Kill) 326 .addReg(Op1, Op1IsKill * RegState::Kill)); 329 .addReg(Op0, Op0IsKill * RegState::Kill) 330 .addReg(Op1, Op1IsKill * RegState::Kill)); 348 .addReg(Op0, Op0IsKill * RegState::Kill) 349 .addReg(Op1, Op1IsKill * RegState::Kill) 350 .addReg(Op2, Op2IsKill * RegState::Kill)); 353 .addReg(Op0, Op0IsKill * RegState [all...] |
H A D | Thumb1FrameLowering.cpp | 276 .addReg(ARM::R3, RegState::Define); 282 .addReg(ARM::R3, RegState::Kill);
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H A D | ARMBaseInstrInfo.cpp | 956 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 957 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 958 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 959 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 961 MIB.addReg(DestReg, RegState::ImplicitDefine); 972 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); 973 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); 974 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); 975 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); 976 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); 944 .addReg(Base, RegState::Define) 949 .addReg(Base, RegState::Define) 956 .addReg(Base, RegState::Define) 1749 .addReg(EvenReg, RegState::Define) 1750 .addReg(OddReg, RegState::Define)
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H A D | ARMISelLowering.cpp | 5644 .addReg(ARM::R2, RegState::Define) 5645 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5752 .addReg(NewVReg1, RegState::Kill) 5756 .addReg(NewVReg2, RegState::Kill) 5759 .addReg(NewVReg3, RegState::Kill) 5777 .addReg(NewVReg1, RegState::Kill) 5782 .addReg(ARM::CPSR, RegState::Define) 5786 .addReg(ARM::CPSR, RegState::Define) 5787 .addReg(NewVReg2, RegState::Kill) 5788 .addReg(NewVReg3, RegState [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 227 .addReg(ScratchReg, RegState::Kill); 233 .addReg(ScratchReg, RegState::Kill); 238 .addReg(ScratchReg, RegState::Kill);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 200 .addReg(Reg, RegState::Kill);
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/external/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 736 .addReg(FramePtr, RegState::Kill) 873 .addReg(X86::EAX, RegState::Kill) 894 .addReg(StackPtr, RegState::Define | RegState::Implicit) 895 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) 1120 addReg(JumpTarget.getReg(), RegState::Kill); 1123 addReg(JumpTarget.getReg(), RegState::Kill); 1208 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) 1477 .addReg(ScratchReg2, RegState [all...] |
H A D | X86FloatingPoint.cpp | 1661 .addReg(X86::ST0, RegState::ImplicitKill) 1662 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 1663 .addReg(X86::EDX, RegState::Define | RegState::Implicit) 1664 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
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H A D | X86InstrInfo.cpp | 1579 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1590 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1624 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1637 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1638 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1694 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1712 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1729 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1749 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1764 .addReg(Dest, RegState [all...] |
H A D | X86ISelLowering.cpp | 12312 .addReg(X86::RAX, RegState::ImplicitDefine); 12320 .addReg(X86::EAX, RegState::ImplicitDefine); 12368 .addReg(X86::RAX, RegState::Implicit) 12369 .addReg(X86::RSP, RegState::Implicit) 12370 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 12371 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 12372 .addReg(X86::EFLAGS, RegState::Define | RegState [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPURegisterInfo.cpp | 303 .addReg(tmpReg, RegState::Kill)
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/external/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 93 // RegState - Track the state of a physical register. 94 enum RegState { enum in class:__anon7386::RAFast 113 // PhysRegState - One of the RegState enums, or a virtreg. 160 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 236 "Broken RegState mapping"); 266 assert(PhysRegState[LR.PhysReg] == LRI->VirtReg && "Broken RegState mapping"); 395 RegState NewState) {
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H A D | TargetInstrInfoImpl.cpp | 106 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead), SubReg0)
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H A D | TwoAddressInstructionPass.cpp | 1772 .addReg(DstReg, RegState::Define | 1891 .addReg(DstReg, RegState::Define, SubIdx)
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/external/llvm/lib/Target/Mips/ |
H A D | MipsInstrInfo.cpp | 162 MIB.addReg(DestReg, RegState::Define);
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