/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 27 case ISD::SRL: return ARM_AM::lsr;
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/external/openssl/crypto/sha/asm/ |
H A D | sha512-mips.pl | 84 $SRL="dsrl"; # shift right logical 98 $SRL="srl"; # shift right logical 159 $SRL $h,$e,@Sigma1[0] 163 $SRL $tmp0,$e,@Sigma1[1] 167 $SRL $tmp0,$e,@Sigma1[2] 174 $SRL $h,$a,@Sigma0[0] 179 $SRL $tmp0,$a,@Sigma0[1] 183 $SRL $tmp0,$a,@Sigma0[2] 210 $SRL $tmp2,@X[1],@sigma0[0] # Xupdate($i) 213 $SRL [all...] |
H A D | sha512-sparcv9.pl | 59 $SRL="srlx"; # shift right logical 85 $SRL="srl"; # shift right logical 222 $SRL $e,@Sigma1[0],$h !! $i 226 $SRL $e,@Sigma1[1],$tmp0 230 $SRL $e,@Sigma1[2],$tmp0 237 $SRL $a,@Sigma0[0],$h 242 $SRL $a,@Sigma0[1],$tmp0 246 $SRL $a,@Sigma0[2],$tmp0
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/external/libffi/src/mips/ |
H A D | ffitarget.h | 128 # define SRL srl macro 135 # define SRL dsrl
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H A D | n32.S | 119 SRL t4, t6, 1*FFI_FLAG_BITS 132 SRL t4, t6, 2*FFI_FLAG_BITS 145 SRL t4, t6, 3*FFI_FLAG_BITS 158 SRL t4, t6, 4*FFI_FLAG_BITS 171 SRL t4, t6, 5*FFI_FLAG_BITS 184 SRL t4, t6, 6*FFI_FLAG_BITS 197 SRL t4, t6, 7*FFI_FLAG_BITS 219 SRL t6, 8*FFI_FLAG_BITS
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H A D | o32.S | 80 SRL t2, t0, 4 # shift our arg info
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/external/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 310 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
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/external/v8/src/mips/ |
H A D | constants-mips.cc | 244 case SRL:
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H A D | constants-mips.h | 305 SRL = ((0 << 3) + 2),
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 350 } else if (Opcode == ISD::SRL) { 397 Op0.getOperand(0).getOpcode() == ISD::SRL) { 399 Op1.getOperand(0).getOpcode() != ISD::SRL) { 405 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 407 Op1.getOperand(0).getOpcode() != ISD::SRL) { 418 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 425 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 989 case ISD::SRL: {
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H A D | PPCISelLowering.h | 91 SRL, SRA, SHL, enumerator in enum:llvm::PPCISD::NodeType
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 667 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 792 case ISD::SRL: 1158 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1297 DAG.getNode(ISD::SRL, DL, NVT, InL, 1303 if (N->getOpcode() == ISD::SRL) { 1308 Lo = DAG.getNode(ISD::SRL, DL, 1316 DAG.getNode(ISD::SRL, D [all...] |
H A D | LegalizeVectorOps.cpp | 185 case ISD::SRL: 428 // Make sure that the SINT_TO_FP and SRL instructions are available. 430 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 450 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
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H A D | TargetLowering.cpp | 1451 if (InOp.getOpcode() == ISD::SRL && 1459 Opc = ISD::SRL; 1501 case ISD::SRL: 1519 unsigned Opc = ISD::SRL; 1552 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), 1584 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, 1748 case ISD::SRL: 1749 // Shrink SRL by a constant if none of the high bits shifted in are 1752 !isTypeDesirableForOp(ISD::SRL, Op.getValueType())) 1776 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, d [all...] |
H A D | LegalizeDAG.cpp | 393 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 825 case ISD::SRL: 1266 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1277 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 2091 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2112 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2146 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2299 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2305 Tmp1 = DAG.getNode(ISD::SRL, d [all...] |
H A D | DAGCombiner.cpp | 874 else if (Opc == ISD::SRL) 1115 case ISD::SRL: return visitSRL(N); 1194 case ISD::SRL: 1876 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, local 1879 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1880 AddToWorkList(SRL.getNode()); 1930 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1944 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 2088 N1 = DAG.getNode(ISD::SRL, D [all...] |
H A D | FastISel.cpp | 957 return SelectBinaryOp(I, ISD::SRL); 1116 Opcode = ISD::SRL; 1122 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL enumerator in enum:llvm::MSP430ISD::__anon7614
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H A D | MSP430ISelLowering.cpp | 97 setOperationAction(ISD::SRL, MVT::i8, Custom); 100 setOperationAction(ISD::SRL, MVT::i16, Custom); 184 case ISD::SRL: 603 case ISD::SRL: 604 return DAG.getNode(MSP430ISD::SRL, dl, 615 if (Opc == ISD::SRL && ShiftAmount) { 819 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
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/external/openssl/crypto/bn/asm/ |
H A D | mips.pl | 62 $SRL="dsrl"; 77 $SRL="srl"; 903 $SRL $at,$a1,$t1 917 $SRL $DH,$a2,4*$BNSZ # bits 925 $SRL $HH,$a0,4*$BNSZ # bits 926 $SRL $QT,4*$BNSZ # q=0xffffffff 933 $SRL $at,$a1,4*$BNSZ # bits 958 $SRL $HH,$a0,4*$BNSZ # bits 959 $SRL $QT,4*$BNSZ # q=0xffffffff 966 $SRL [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 241 setOperationAction(ISD::SRL, MVT::i8, Custom); 246 setOperationAction(ISD::SRL, MVT::i64, Legal); 2248 case ISD::SRL: 2392 DAG.getNode(ISD::SRL, dl, MVT::i16, 2423 DAG.getNode(ISD::SRL, dl, MVT::i32, 2435 DAG.getNode(ISD::SRL, dl, MVT::i32, 2528 DAG.getNode(ISD::SRL, dl, IntVT, 2562 DAG.getNode(ISD::SRL, dl, IntVT, 2808 case ISD::SRL:
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H A D | SPUISelDAGToDAG.cpp | 743 if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL) 765 if (Op0.getOpcode() == ISD::SRL) 779 } else if (Opc == ISD::SRL) {
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/external/llvm/lib/Target/Mips/ |
H A D | MipsMCInstLower.cpp | 300 Instr2.setOpcode(Mips::SRL);
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H A D | MipsISelLowering.cpp | 625 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 1801 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1802 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1848 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1849 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1889 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1914 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 983 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 984 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 993 setOperationAction(ISD::SRL, MVT::v2i64, Legal); 994 setOperationAction(ISD::SRL, MVT::v4i32, Legal); 1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1092 setOperationAction(ISD::SRL, MV 10288 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R, local 10331 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R, local [all...] |