1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are 5 * met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above 9 * copyright notice, this list of conditions and the following 10 * disclaimer in the documentation and/or other materials provided 11 * with the distribution. 12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its 13 * contributors may be used to endorse or promote products derived 14 * from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30#ifndef _MSM_VIDC_DEC_H_ 31#define _MSM_VIDC_DEC_H_ 32 33#include <linux/types.h> 34#include <linux/ioctl.h> 35 36/* STATUS CODES */ 37/* Base value for status codes */ 38#define VDEC_S_BASE 0x40000000 39/* Success */ 40#define VDEC_S_SUCCESS (VDEC_S_BASE) 41/* General failure */ 42#define VDEC_S_EFAIL (VDEC_S_BASE + 1) 43/* Fatal irrecoverable failure. Need to tear down session. */ 44#define VDEC_S_EFATAL (VDEC_S_BASE + 2) 45/* Error detected in the passed parameters */ 46#define VDEC_S_EBADPARAM (VDEC_S_BASE + 3) 47/* Command called in invalid state. */ 48#define VDEC_S_EINVALSTATE (VDEC_S_BASE + 4) 49 /* Insufficient OS resources - thread, memory etc. */ 50#define VDEC_S_ENOSWRES (VDEC_S_BASE + 5) 51 /* Insufficient HW resources - core capacity maxed out. */ 52#define VDEC_S_ENOHWRES (VDEC_S_BASE + 6) 53/* Invalid command called */ 54#define VDEC_S_EINVALCMD (VDEC_S_BASE + 7) 55/* Command timeout. */ 56#define VDEC_S_ETIMEOUT (VDEC_S_BASE + 8) 57/* Pre-requirement is not met for API. */ 58#define VDEC_S_ENOPREREQ (VDEC_S_BASE + 9) 59/* Command queue is full. */ 60#define VDEC_S_ECMDQFULL (VDEC_S_BASE + 10) 61/* Command is not supported by this driver */ 62#define VDEC_S_ENOTSUPP (VDEC_S_BASE + 11) 63/* Command is not implemented by thedriver. */ 64#define VDEC_S_ENOTIMPL (VDEC_S_BASE + 12) 65/* Command is not implemented by the driver. */ 66#define VDEC_S_BUSY (VDEC_S_BASE + 13) 67 68#define VDEC_INTF_VER 1 69#define VDEC_MSG_BASE 0x0000000 70/* Codes to identify asynchronous message responses and events that driver 71 wants to communicate to the app.*/ 72#define VDEC_MSG_INVALID (VDEC_MSG_BASE + 0) 73#define VDEC_MSG_RESP_INPUT_BUFFER_DONE (VDEC_MSG_BASE + 1) 74#define VDEC_MSG_RESP_OUTPUT_BUFFER_DONE (VDEC_MSG_BASE + 2) 75#define VDEC_MSG_RESP_INPUT_FLUSHED (VDEC_MSG_BASE + 3) 76#define VDEC_MSG_RESP_OUTPUT_FLUSHED (VDEC_MSG_BASE + 4) 77#define VDEC_MSG_RESP_FLUSH_INPUT_DONE (VDEC_MSG_BASE + 5) 78#define VDEC_MSG_RESP_FLUSH_OUTPUT_DONE (VDEC_MSG_BASE + 6) 79#define VDEC_MSG_RESP_START_DONE (VDEC_MSG_BASE + 7) 80#define VDEC_MSG_RESP_STOP_DONE (VDEC_MSG_BASE + 8) 81#define VDEC_MSG_RESP_PAUSE_DONE (VDEC_MSG_BASE + 9) 82#define VDEC_MSG_RESP_RESUME_DONE (VDEC_MSG_BASE + 10) 83#define VDEC_MSG_RESP_RESOURCE_LOADED (VDEC_MSG_BASE + 11) 84#define VDEC_EVT_RESOURCES_LOST (VDEC_MSG_BASE + 12) 85#define VDEC_MSG_EVT_CONFIG_CHANGED (VDEC_MSG_BASE + 13) 86#define VDEC_MSG_EVT_HW_ERROR (VDEC_MSG_BASE + 14) 87 88/*Buffer flags bits masks.*/ 89#define VDEC_BUFFERFLAG_EOS 0x00000001 90#define VDEC_BUFFERFLAG_DECODEONLY 0x00000004 91#define VDEC_BUFFERFLAG_DATACORRUPT 0x00000008 92#define VDEC_BUFFERFLAG_ENDOFFRAME 0x00000010 93#define VDEC_BUFFERFLAG_SYNCFRAME 0x00000020 94#define VDEC_BUFFERFLAG_EXTRADATA 0x00000040 95#define VDEC_BUFFERFLAG_CODECCONFIG 0x00000080 96 97/*Post processing flags bit masks*/ 98#define VDEC_EXTRADATA_QP 0x00000001 99#define VDEC_EXTRADATA_SEI 0x00000002 100#define VDEC_EXTRADATA_VUI 0x00000004 101#define VDEC_EXTRADATA_MB_ERROR_MAP 0x00000008 102 103#define VDEC_CMDBASE 0x800 104#define VDEC_CMD_SET_INTF_VERSION (VDEC_CMDBASE) 105 106#define VDEC_IOCTL_MAGIC 'v' 107 108struct vdec_ioctl_msg { 109 void *inputparam; 110 void *outputparam; 111}; 112 113/* CMD params: InputParam:enum vdec_codec 114 OutputParam: struct vdec_profile_level*/ 115#define VDEC_IOCTL_GET_PROFILE_LEVEL_SUPPORTED \ 116 _IOWR(VDEC_IOCTL_MAGIC, 0, struct vdec_ioctl_msg) 117 118/*CMD params:InputParam: NULL 119 OutputParam: uint32_t(bitmask)*/ 120#define VDEC_IOCTL_GET_INTERLACE_FORMAT \ 121 _IOR(VDEC_IOCTL_MAGIC, 1, struct vdec_ioctl_msg) 122 123/* CMD params: InputParam: enum vdec_codec 124 OutputParam: struct vdec_profile_level*/ 125#define VDEC_IOCTL_GET_CURRENT_PROFILE_LEVEL \ 126 _IOWR(VDEC_IOCTL_MAGIC, 2, struct vdec_ioctl_msg) 127 128/*CMD params: SET: InputParam: enum vdec_output_fromat OutputParam: NULL 129 GET: InputParam: NULL OutputParam: enum vdec_output_fromat*/ 130#define VDEC_IOCTL_SET_OUTPUT_FORMAT \ 131 _IOWR(VDEC_IOCTL_MAGIC, 3, struct vdec_ioctl_msg) 132#define VDEC_IOCTL_GET_OUTPUT_FORMAT \ 133 _IOWR(VDEC_IOCTL_MAGIC, 4, struct vdec_ioctl_msg) 134 135/*CMD params: SET: InputParam: enum vdec_codec OutputParam: NULL 136 GET: InputParam: NULL OutputParam: enum vdec_codec*/ 137#define VDEC_IOCTL_SET_CODEC \ 138 _IOW(VDEC_IOCTL_MAGIC, 5, struct vdec_ioctl_msg) 139#define VDEC_IOCTL_GET_CODEC \ 140 _IOR(VDEC_IOCTL_MAGIC, 6, struct vdec_ioctl_msg) 141 142/*CMD params: SET: InputParam: struct vdec_picsize outputparam: NULL 143 GET: InputParam: NULL outputparam: struct vdec_picsize*/ 144#define VDEC_IOCTL_SET_PICRES \ 145 _IOW(VDEC_IOCTL_MAGIC, 7, struct vdec_ioctl_msg) 146#define VDEC_IOCTL_GET_PICRES \ 147 _IOR(VDEC_IOCTL_MAGIC, 8, struct vdec_ioctl_msg) 148 149#define VDEC_IOCTL_SET_EXTRADATA \ 150 _IOW(VDEC_IOCTL_MAGIC, 9, struct vdec_ioctl_msg) 151#define VDEC_IOCTL_GET_EXTRADATA \ 152 _IOR(VDEC_IOCTL_MAGIC, 10, struct vdec_ioctl_msg) 153 154#define VDEC_IOCTL_SET_SEQUENCE_HEADER \ 155 _IOW(VDEC_IOCTL_MAGIC, 11, struct vdec_ioctl_msg) 156 157/* CMD params: SET: InputParam - vdec_allocatorproperty, OutputParam - NULL 158 GET: InputParam - NULL, OutputParam - vdec_allocatorproperty*/ 159#define VDEC_IOCTL_SET_BUFFER_REQ \ 160 _IOW(VDEC_IOCTL_MAGIC, 12, struct vdec_ioctl_msg) 161#define VDEC_IOCTL_GET_BUFFER_REQ \ 162 _IOR(VDEC_IOCTL_MAGIC, 13, struct vdec_ioctl_msg) 163/* CMD params: InputParam - vdec_buffer, OutputParam - uint8_t** */ 164#define VDEC_IOCTL_ALLOCATE_BUFFER \ 165 _IOWR(VDEC_IOCTL_MAGIC, 14, struct vdec_ioctl_msg) 166/* CMD params: InputParam - uint8_t *, OutputParam - NULL.*/ 167#define VDEC_IOCTL_FREE_BUFFER \ 168 _IOW(VDEC_IOCTL_MAGIC, 15, struct vdec_ioctl_msg) 169 170/*CMD params: CMD: InputParam - struct vdec_setbuffer_cmd, OutputParam - NULL*/ 171#define VDEC_IOCTL_SET_BUFFER \ 172 _IOW(VDEC_IOCTL_MAGIC, 16, struct vdec_ioctl_msg) 173 174/* CMD params: InputParam - struct vdec_fillbuffer_cmd, OutputParam - NULL*/ 175#define VDEC_IOCTL_FILL_OUTPUT_BUFFER \ 176 _IOW(VDEC_IOCTL_MAGIC, 17, struct vdec_ioctl_msg) 177 178/*CMD params: InputParam - struct vdec_frameinfo , OutputParam - NULL*/ 179#define VDEC_IOCTL_DECODE_FRAME \ 180 _IOW(VDEC_IOCTL_MAGIC, 18, struct vdec_ioctl_msg) 181 182#define VDEC_IOCTL_LOAD_RESOURCES _IO(VDEC_IOCTL_MAGIC, 19) 183#define VDEC_IOCTL_CMD_START _IO(VDEC_IOCTL_MAGIC, 20) 184#define VDEC_IOCTL_CMD_STOP _IO(VDEC_IOCTL_MAGIC, 21) 185#define VDEC_IOCTL_CMD_PAUSE _IO(VDEC_IOCTL_MAGIC, 22) 186#define VDEC_IOCTL_CMD_RESUME _IO(VDEC_IOCTL_MAGIC, 23) 187 188/*CMD params: InputParam - enum vdec_bufferflush , OutputParam - NULL */ 189#define VDEC_IOCTL_CMD_FLUSH _IOW(VDEC_IOCTL_MAGIC, 24, struct vdec_ioctl_msg) 190 191/* ======================================================== 192 * IOCTL for getting asynchronous notification from driver 193 * ========================================================*/ 194 195/*IOCTL params: InputParam - NULL, OutputParam - struct vdec_msginfo*/ 196#define VDEC_IOCTL_GET_NEXT_MSG \ 197 _IOR(VDEC_IOCTL_MAGIC, 25, struct vdec_ioctl_msg) 198 199#define VDEC_IOCTL_STOP_NEXT_MSG _IO(VDEC_IOCTL_MAGIC, 26) 200 201#define VDEC_IOCTL_GET_NUMBER_INSTANCES \ 202 _IOR(VDEC_IOCTL_MAGIC, 27, struct vdec_ioctl_msg) 203 204enum vdec_picture { 205 PICTURE_TYPE_I, 206 PICTURE_TYPE_P, 207 PICTURE_TYPE_B, 208 PICTURE_TYPE_BI, 209 PICTURE_TYPE_SKIP, 210 PICTURE_TYPE_UNKNOWN 211}; 212 213enum vdec_buffer { 214 VDEC_BUFFER_TYPE_INPUT, 215 VDEC_BUFFER_TYPE_OUTPUT 216}; 217 218struct vdec_allocatorproperty { 219 enum vdec_buffer buffer_type; 220 uint32_t mincount; 221 uint32_t maxcount; 222 uint32_t actualcount; 223 uint32_t buffer_size; 224 uint32_t alignment; 225 uint32_t buf_poolid; 226}; 227 228struct vdec_bufferpayload { 229 uint8_t *bufferaddr; 230 uint32_t buffer_len; 231 int pmem_fd; 232 uint32_t offset; 233 uint32_t mmaped_size; 234}; 235 236struct vdec_setbuffer_cmd { 237 enum vdec_buffer buffer_type; 238 struct vdec_bufferpayload buffer; 239}; 240 241struct vdec_fillbuffer_cmd { 242 struct vdec_bufferpayload buffer; 243 void *client_data; 244}; 245 246enum vdec_bufferflush { 247 VDEC_FLUSH_TYPE_INPUT, 248 VDEC_FLUSH_TYPE_OUTPUT, 249 VDEC_FLUSH_TYPE_ALL 250}; 251 252enum vdec_codec { 253 VDEC_CODECTYPE_H264 = 0x1, 254 VDEC_CODECTYPE_H263 = 0x2, 255 VDEC_CODECTYPE_MPEG4 = 0x3, 256 VDEC_CODECTYPE_DIVX_3 = 0x4, 257 VDEC_CODECTYPE_DIVX_4 = 0x5, 258 VDEC_CODECTYPE_DIVX_5 = 0x6, 259 VDEC_CODECTYPE_DIVX_6 = 0x7, 260 VDEC_CODECTYPE_XVID = 0x8, 261 VDEC_CODECTYPE_MPEG1 = 0x9, 262 VDEC_CODECTYPE_MPEG2 = 0xa, 263 VDEC_CODECTYPE_VC1 = 0xb, 264 VDEC_CODECTYPE_VC1_RCV = 0xc 265}; 266 267enum vdec_mpeg2_profile { 268 VDEC_MPEG2ProfileSimple = 0x1, 269 VDEC_MPEG2ProfileMain = 0x2, 270 VDEC_MPEG2Profile422 = 0x4, 271 VDEC_MPEG2ProfileSNR = 0x8, 272 VDEC_MPEG2ProfileSpatial = 0x10, 273 VDEC_MPEG2ProfileHigh = 0x20, 274 VDEC_MPEG2ProfileKhronosExtensions = 0x6F000000, 275 VDEC_MPEG2ProfileVendorStartUnused = 0x7F000000, 276 VDEC_MPEG2ProfileMax = 0x7FFFFFFF 277}; 278 279enum vdec_mpeg2_level { 280 281 VDEC_MPEG2LevelLL = 0x1, 282 VDEC_MPEG2LevelML = 0x2, 283 VDEC_MPEG2LevelH14 = 0x4, 284 VDEC_MPEG2LevelHL = 0x8, 285 VDEC_MPEG2LevelKhronosExtensions = 0x6F000000, 286 VDEC_MPEG2LevelVendorStartUnused = 0x7F000000, 287 VDEC_MPEG2LevelMax = 0x7FFFFFFF 288}; 289 290enum vdec_mpeg4_profile { 291 VDEC_MPEG4ProfileSimple = 0x01, 292 VDEC_MPEG4ProfileSimpleScalable = 0x02, 293 VDEC_MPEG4ProfileCore = 0x04, 294 VDEC_MPEG4ProfileMain = 0x08, 295 VDEC_MPEG4ProfileNbit = 0x10, 296 VDEC_MPEG4ProfileScalableTexture = 0x20, 297 VDEC_MPEG4ProfileSimpleFace = 0x40, 298 VDEC_MPEG4ProfileSimpleFBA = 0x80, 299 VDEC_MPEG4ProfileBasicAnimated = 0x100, 300 VDEC_MPEG4ProfileHybrid = 0x200, 301 VDEC_MPEG4ProfileAdvancedRealTime = 0x400, 302 VDEC_MPEG4ProfileCoreScalable = 0x800, 303 VDEC_MPEG4ProfileAdvancedCoding = 0x1000, 304 VDEC_MPEG4ProfileAdvancedCore = 0x2000, 305 VDEC_MPEG4ProfileAdvancedScalable = 0x4000, 306 VDEC_MPEG4ProfileAdvancedSimple = 0x8000, 307 VDEC_MPEG4ProfileKhronosExtensions = 0x6F000000, 308 VDEC_MPEG4ProfileVendorStartUnused = 0x7F000000, 309 VDEC_MPEG4ProfileMax = 0x7FFFFFFF 310}; 311 312enum vdec_mpeg4_level { 313 VDEC_MPEG4Level0 = 0x01, 314 VDEC_MPEG4Level0b = 0x02, 315 VDEC_MPEG4Level1 = 0x04, 316 VDEC_MPEG4Level2 = 0x08, 317 VDEC_MPEG4Level3 = 0x10, 318 VDEC_MPEG4Level4 = 0x20, 319 VDEC_MPEG4Level4a = 0x40, 320 VDEC_MPEG4Level5 = 0x80, 321 VDEC_MPEG4LevelKhronosExtensions = 0x6F000000, 322 VDEC_MPEG4LevelVendorStartUnused = 0x7F000000, 323 VDEC_MPEG4LevelMax = 0x7FFFFFFF 324}; 325 326enum vdec_avc_profile { 327 VDEC_AVCProfileBaseline = 0x01, 328 VDEC_AVCProfileMain = 0x02, 329 VDEC_AVCProfileExtended = 0x04, 330 VDEC_AVCProfileHigh = 0x08, 331 VDEC_AVCProfileHigh10 = 0x10, 332 VDEC_AVCProfileHigh422 = 0x20, 333 VDEC_AVCProfileHigh444 = 0x40, 334 VDEC_AVCProfileKhronosExtensions = 0x6F000000, 335 VDEC_AVCProfileVendorStartUnused = 0x7F000000, 336 VDEC_AVCProfileMax = 0x7FFFFFFF 337}; 338 339enum vdec_avc_level { 340 VDEC_AVCLevel1 = 0x01, 341 VDEC_AVCLevel1b = 0x02, 342 VDEC_AVCLevel11 = 0x04, 343 VDEC_AVCLevel12 = 0x08, 344 VDEC_AVCLevel13 = 0x10, 345 VDEC_AVCLevel2 = 0x20, 346 VDEC_AVCLevel21 = 0x40, 347 VDEC_AVCLevel22 = 0x80, 348 VDEC_AVCLevel3 = 0x100, 349 VDEC_AVCLevel31 = 0x200, 350 VDEC_AVCLevel32 = 0x400, 351 VDEC_AVCLevel4 = 0x800, 352 VDEC_AVCLevel41 = 0x1000, 353 VDEC_AVCLevel42 = 0x2000, 354 VDEC_AVCLevel5 = 0x4000, 355 VDEC_AVCLevel51 = 0x8000, 356 VDEC_AVCLevelKhronosExtensions = 0x6F000000, 357 VDEC_AVCLevelVendorStartUnused = 0x7F000000, 358 VDEC_AVCLevelMax = 0x7FFFFFFF 359}; 360 361enum vdec_divx_profile { 362 VDEC_DIVXProfile_qMobile = 0x01, 363 VDEC_DIVXProfile_Mobile = 0x02, 364 VDEC_DIVXProfile_HD = 0x04, 365 VDEC_DIVXProfile_Handheld = 0x08, 366 VDEC_DIVXProfile_Portable = 0x10, 367 VDEC_DIVXProfile_HomeTheater = 0x20 368}; 369 370enum vdec_xvid_profile { 371 VDEC_XVIDProfile_Simple = 0x1, 372 VDEC_XVIDProfile_Advanced_Realtime_Simple = 0x2, 373 VDEC_XVIDProfile_Advanced_Simple = 0x4 374}; 375 376enum vdec_xvid_level { 377 VDEC_XVID_LEVEL_S_L0 = 0x1, 378 VDEC_XVID_LEVEL_S_L1 = 0x2, 379 VDEC_XVID_LEVEL_S_L2 = 0x4, 380 VDEC_XVID_LEVEL_S_L3 = 0x8, 381 VDEC_XVID_LEVEL_ARTS_L1 = 0x10, 382 VDEC_XVID_LEVEL_ARTS_L2 = 0x20, 383 VDEC_XVID_LEVEL_ARTS_L3 = 0x40, 384 VDEC_XVID_LEVEL_ARTS_L4 = 0x80, 385 VDEC_XVID_LEVEL_AS_L0 = 0x100, 386 VDEC_XVID_LEVEL_AS_L1 = 0x200, 387 VDEC_XVID_LEVEL_AS_L2 = 0x400, 388 VDEC_XVID_LEVEL_AS_L3 = 0x800, 389 VDEC_XVID_LEVEL_AS_L4 = 0x1000 390}; 391 392enum vdec_h263profile { 393 VDEC_H263ProfileBaseline = 0x01, 394 VDEC_H263ProfileH320Coding = 0x02, 395 VDEC_H263ProfileBackwardCompatible = 0x04, 396 VDEC_H263ProfileISWV2 = 0x08, 397 VDEC_H263ProfileISWV3 = 0x10, 398 VDEC_H263ProfileHighCompression = 0x20, 399 VDEC_H263ProfileInternet = 0x40, 400 VDEC_H263ProfileInterlace = 0x80, 401 VDEC_H263ProfileHighLatency = 0x100, 402 VDEC_H263ProfileKhronosExtensions = 0x6F000000, 403 VDEC_H263ProfileVendorStartUnused = 0x7F000000, 404 VDEC_H263ProfileMax = 0x7FFFFFFF 405}; 406 407enum vdec_h263level { 408 VDEC_H263Level10 = 0x01, 409 VDEC_H263Level20 = 0x02, 410 VDEC_H263Level30 = 0x04, 411 VDEC_H263Level40 = 0x08, 412 VDEC_H263Level45 = 0x10, 413 VDEC_H263Level50 = 0x20, 414 VDEC_H263Level60 = 0x40, 415 VDEC_H263Level70 = 0x80, 416 VDEC_H263LevelKhronosExtensions = 0x6F000000, 417 VDEC_H263LevelVendorStartUnused = 0x7F000000, 418 VDEC_H263LevelMax = 0x7FFFFFFF 419}; 420 421enum vdec_wmv_format { 422 VDEC_WMVFormatUnused = 0x01, 423 VDEC_WMVFormat7 = 0x02, 424 VDEC_WMVFormat8 = 0x04, 425 VDEC_WMVFormat9 = 0x08, 426 VDEC_WMFFormatKhronosExtensions = 0x6F000000, 427 VDEC_WMFFormatVendorStartUnused = 0x7F000000, 428 VDEC_WMVFormatMax = 0x7FFFFFFF 429}; 430 431enum vdec_vc1_profile { 432 VDEC_VC1ProfileSimple = 0x1, 433 VDEC_VC1ProfileMain = 0x2, 434 VDEC_VC1ProfileAdvanced = 0x4 435}; 436 437enum vdec_vc1_level { 438 VDEC_VC1_LEVEL_S_Low = 0x1, 439 VDEC_VC1_LEVEL_S_Medium = 0x2, 440 VDEC_VC1_LEVEL_M_Low = 0x4, 441 VDEC_VC1_LEVEL_M_Medium = 0x8, 442 VDEC_VC1_LEVEL_M_High = 0x10, 443 VDEC_VC1_LEVEL_A_L0 = 0x20, 444 VDEC_VC1_LEVEL_A_L1 = 0x40, 445 VDEC_VC1_LEVEL_A_L2 = 0x80, 446 VDEC_VC1_LEVEL_A_L3 = 0x100, 447 VDEC_VC1_LEVEL_A_L4 = 0x200 448}; 449 450struct vdec_profile_level { 451 uint32_t profiles; 452 uint32_t levels; 453}; 454 455enum vdec_interlaced_format { 456 VDEC_InterlaceFrameProgressive = 0x1, 457 VDEC_InterlaceInterleaveFrameTopFieldFirst = 0x2, 458 VDEC_InterlaceInterleaveFrameBottomFieldFirst = 0x4 459}; 460 461enum vdec_output_fromat { 462 VDEC_YUV_FORMAT_NV12 = 0x1, 463 VDEC_YUV_FORMAT_TILE_4x2 = 0x2 464}; 465 466struct vdec_picsize { 467 uint32_t frame_width; 468 uint32_t frame_height; 469 uint32_t stride; 470 uint32_t scan_lines; 471}; 472 473struct vdec_seqheader { 474 uint8_t *ptr_seqheader; 475 uint32_t seq_header_len; 476 int pmem_fd; 477 uint32_t pmem_offset; 478}; 479 480struct vdec_mberror { 481 uint8_t *ptr_errormap; 482 uint32_t err_mapsize; 483}; 484 485struct vdec_input_frameinfo { 486 uint8_t *bufferaddr; 487 uint32_t offset; 488 uint32_t datalen; 489 uint32_t flags; 490 int64_t timestamp; 491 void *client_data; 492 int pmem_fd; 493 uint32_t pmem_offset; 494}; 495 496struct vdec_framesize { 497 uint32_t n_left; 498 uint32_t n_top; 499 uint32_t n_right; 500 uint32_t n_bottom; 501}; 502 503struct vdec_output_frameinfo { 504 uint8_t *phy_addr; 505 uint8_t *bufferaddr; 506 uint32_t offset; 507 uint32_t len; 508 uint32_t flags; 509 int64_t time_stamp; 510 void *client_data; 511 void *input_frame_clientdata; 512 struct vdec_framesize framesize; 513}; 514 515union vdec_msgdata { 516 struct vdec_output_frameinfo output_frame; 517 void *input_frame_clientdata; 518}; 519 520struct vdec_msginfo { 521 uint32_t status_code; 522 uint32_t msgcode; 523 union vdec_msgdata msgdata; 524 uint32_t msgdatasize; 525}; 526#endif /* end of macro _VDECDECODER_H_ */ 527