1//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file includes code for rendering MCInst instances as AT&T-style 11// assembly. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "asm-printer" 16#include "X86IntelInstPrinter.h" 17#include "X86InstComments.h" 18#include "MCTargetDesc/X86MCTargetDesc.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInstrInfo.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/FormattedStream.h" 24#include <cctype> 25using namespace llvm; 26 27#include "X86GenAsmWriter1.inc" 28 29void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 30 OS << getRegisterName(RegNo); 31} 32 33void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, 34 StringRef Annot) { 35 printInstruction(MI, OS); 36 37 // Next always print the annotation. 38 printAnnotation(OS, Annot); 39 40 // If verbose assembly is enabled, we can print some informative comments. 41 if (CommentStream) 42 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 43} 44 45void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, 46 raw_ostream &O) { 47 switch (MI->getOperand(Op).getImm()) { 48 default: llvm_unreachable("Invalid ssecc argument!"); 49 case 0: O << "eq"; break; 50 case 1: O << "lt"; break; 51 case 2: O << "le"; break; 52 case 3: O << "unord"; break; 53 case 4: O << "neq"; break; 54 case 5: O << "nlt"; break; 55 case 6: O << "nle"; break; 56 case 7: O << "ord"; break; 57 case 8: O << "eq_uq"; break; 58 case 9: O << "nge"; break; 59 case 0xa: O << "ngt"; break; 60 case 0xb: O << "false"; break; 61 case 0xc: O << "neq_oq"; break; 62 case 0xd: O << "ge"; break; 63 case 0xe: O << "gt"; break; 64 case 0xf: O << "true"; break; 65 case 0x10: O << "eq_os"; break; 66 case 0x11: O << "lt_oq"; break; 67 case 0x12: O << "le_oq"; break; 68 case 0x13: O << "unord_s"; break; 69 case 0x14: O << "neq_us"; break; 70 case 0x15: O << "nlt_uq"; break; 71 case 0x16: O << "nle_uq"; break; 72 case 0x17: O << "ord_s"; break; 73 case 0x18: O << "eq_us"; break; 74 case 0x19: O << "nge_uq"; break; 75 case 0x1a: O << "ngt_uq"; break; 76 case 0x1b: O << "false_os"; break; 77 case 0x1c: O << "neq_os"; break; 78 case 0x1d: O << "ge_oq"; break; 79 case 0x1e: O << "gt_oq"; break; 80 case 0x1f: O << "true_us"; break; 81 82 } 83} 84 85/// print_pcrel_imm - This is used to print an immediate value that ends up 86/// being encoded as a pc-relative value. 87void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, 88 raw_ostream &O) { 89 const MCOperand &Op = MI->getOperand(OpNo); 90 if (Op.isImm()) 91 O << Op.getImm(); 92 else { 93 assert(Op.isExpr() && "unknown pcrel immediate operand"); 94 // If a symbolic branch target was added as a constant expression then print 95 // that address in hex. 96 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 97 int64_t Address; 98 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 99 O << "0x"; 100 O.write_hex(Address); 101 } 102 else { 103 // Otherwise, just print the expression. 104 O << *Op.getExpr(); 105 } 106 } 107} 108 109static void PrintRegName(raw_ostream &O, StringRef RegName) { 110 for (unsigned i = 0, e = RegName.size(); i != e; ++i) 111 O << (char)toupper(RegName[i]); 112} 113 114void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 115 raw_ostream &O) { 116 const MCOperand &Op = MI->getOperand(OpNo); 117 if (Op.isReg()) { 118 PrintRegName(O, getRegisterName(Op.getReg())); 119 } else if (Op.isImm()) { 120 O << Op.getImm(); 121 } else { 122 assert(Op.isExpr() && "unknown operand kind in printOperand"); 123 O << *Op.getExpr(); 124 } 125} 126 127void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 128 raw_ostream &O) { 129 const MCOperand &BaseReg = MI->getOperand(Op); 130 unsigned ScaleVal = MI->getOperand(Op+1).getImm(); 131 const MCOperand &IndexReg = MI->getOperand(Op+2); 132 const MCOperand &DispSpec = MI->getOperand(Op+3); 133 const MCOperand &SegReg = MI->getOperand(Op+4); 134 135 // If this has a segment register, print it. 136 if (SegReg.getReg()) { 137 printOperand(MI, Op+4, O); 138 O << ':'; 139 } 140 141 O << '['; 142 143 bool NeedPlus = false; 144 if (BaseReg.getReg()) { 145 printOperand(MI, Op, O); 146 NeedPlus = true; 147 } 148 149 if (IndexReg.getReg()) { 150 if (NeedPlus) O << " + "; 151 if (ScaleVal != 1) 152 O << ScaleVal << '*'; 153 printOperand(MI, Op+2, O); 154 NeedPlus = true; 155 } 156 157 158 if (!DispSpec.isImm()) { 159 if (NeedPlus) O << " + "; 160 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 161 O << *DispSpec.getExpr(); 162 } else { 163 int64_t DispVal = DispSpec.getImm(); 164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { 165 if (NeedPlus) { 166 if (DispVal > 0) 167 O << " + "; 168 else { 169 O << " - "; 170 DispVal = -DispVal; 171 } 172 } 173 O << DispVal; 174 } 175 } 176 177 O << ']'; 178} 179