| 4185972e211b0c84b9fe7d90c56b28cc15e474fa |
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27-Sep-2011 |
buzbee <buzbee@google.com> |
Fix memory barriers (Issue 3338450)
Add extra memory barrier on volatile stores.
Change-Id: Id4a4750cdfc910eda2f0b44ead0af2a569b5735e
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| 919eb063ce4542d3698e10e20aba9a2dfbdd0f82 |
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12-Jul-2010 |
buzbee <buzbee@google.com> |
Interpreter & JIT support for write barriers
In this iteration, cards are marked on either the store address or
the object head (whichever leads to faster code). In all cases,
though, card marks are deferred until after the associated store
has completed.
Change-Id: I633d6e8c3bebdb80bde92efb4fa6fc7cc84f60fc
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| 0890e5bf0b2a502ca1030e9773fabc16ef1b5981 |
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18-Jun-2010 |
Andy McFadden <fadden@android.com> |
Fiddle with SMP_DMB.
This changes it from a macro that takes an argument to a simpler
macro that is named explicitly by the 8 instructions that want it.
Change-Id: Ie17a9722823d590851776b6b9b057eadf22fa6a8
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| c35a2ef53d0cccd6f924eeba36633220ec67c32e |
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17-Jun-2010 |
Andy McFadden <fadden@android.com> |
Add opcodes for volatile field accesses
This adds instructions for {i,s}{get,put}{,-object}-volatile, for a
total of eight new instructions.
On SMP systems, these instructions will be substituted in for existing
field access instructions, either by dexopt or during just-in-time
verification. Unlike the wide-volatile instructions, these will not be
used at all when the VM is not built for SMP.
(Ideally we'd omit the volatile instruction implementations entirely on
non-SMP builds, but that requires a little work in gen-mterp.py.)
The change defines and implements the opcodes and support methods, but
does not cause them to be used.
Also, changed dvmQuasiAtomicRead64's argument to be const.
Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e
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