Cross Reference: /external/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Lines Matching refs:SU
78   SUnit *SU = &SUnits.back();
83     SU->SchedulingPref = Sched::None;
85     SU->SchedulingPref = TLI.getSchedulingPreference(N);
86   return SU;
90   SUnit *SU = newSUnit(Old->getNode());
91   SU->OrigNode = Old->OrigNode;
92   SU->Latency = Old->Latency;
93   SU->isVRegCycle = Old->isVRegCycle;
94   SU->isCall = Old->isCall;
95   SU->isCallOp = Old->isCallOp;
96   SU->isTwoAddress = Old->isTwoAddress;
97   SU->isCommutable = Old->isCommutable;
98   SU->hasPhysRegDefs = Old->hasPhysRegDefs;
99   SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
100   SU->isScheduleHigh = Old->isScheduleHigh;
101   SU->isScheduleLow = Old->isScheduleLow;
102   SU->SchedulingPref = Old->SchedulingPref;
104   return SU;
408     SUnit *SU = CallSUnits.pop_back_val();
409     for (const SDNode *SUNode = SU->getNode(); SUNode;
429     SUnit *SU = &SUnits[su];
430     SDNode *MainNode = SU->getNode();
437           SU->isTwoAddress = true;
442         SU->isCommutable = true;
446     for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
449         SU->hasPhysRegClobbers = true;
454           SU->hasPhysRegDefs = true;
462         if (OpSU == SU) continue;           // In the same group.
492           ST.adjustSchedDependency(OpSU, SU, const_cast<SDep &>(dep));
495         if (!SU->addPred(dep) && !dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
551 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
553   : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
576 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
577   assert(SU->NumRegDefsLeft == 0 && "expect a new node");
578   for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
579     assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
580     ++SU->NumRegDefsLeft;
584 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
585   SDNode *N = SU->getNode();
591     SU->Latency = 0;
597     SU->Latency = 1;
604       SU->Latency = HighLatencyCycles;
606       SU->Latency = 1;
612   SU->Latency = 0;
613   for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
615       SU->Latency += TII->getInstrLatency(InstrItins, N);
645 void ScheduleDAGSDNodes::dumpNode(const SUnit *SU) const {
647   if (!SU->getNode()) {
652   SU->getNode()->dump(DAG);
655   for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
669     if (SUnit *SU = Sequence[i])
670       SU->dump(this);
758 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
760   for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
769       for (SUnit::const_succ_iterator II = SU->Succs.begin(),
770              EE = SU->Succs.end(); II != EE; ++II) {
782       unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
783       bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
818     SUnit *SU = Sequence[i];
819     if (!SU) {
827     if (!SU->getNode()) {
829       EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
834     for (SDNode *N = SU->getNode()->getGluedNode(); N;
839       Emitter.EmitNode(GluedNodes.back(), SU->OrigNode != SU, SU->isCloned,
846     Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
850       ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,