Lines Matching defs:OpIdx
103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
376 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
377 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
378 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
379 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
380 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
381 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
1013 unsigned OpIdx) {
1016 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
1017 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1111 unsigned OpIdx = 0;
1113 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1120 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1128 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1145 Binary |= getMachineOpValue(MI, OpIdx++);
1147 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1148 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1158 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1159 ++OpIdx;
1168 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1169 ++OpIdx;
1174 const MachineOperand &MO = MI.getOperand(OpIdx);
1177 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1219 unsigned OpIdx = 0;
1225 ++OpIdx;
1234 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1241 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1244 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1245 ++OpIdx;
1247 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1249 ? 0 : MI.getOperand(OpIdx+1).getImm();
1290 unsigned OpIdx = 0;
1296 ++OpIdx;
1301 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1305 ++OpIdx;
1312 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1315 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1316 ++OpIdx;
1318 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1320 ? 0 : MI.getOperand(OpIdx+1).getImm();
1380 unsigned OpIdx = 0;
1382 ++OpIdx;
1385 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1396 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1423 unsigned OpIdx = 0;
1425 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1428 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1431 Binary |= getMachineOpValue(MI, OpIdx++);
1434 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1438 if (MCID.getNumOperands() > OpIdx &&
1439 !MCID.OpInfo[OpIdx].isPredicate() &&
1440 !MCID.OpInfo[OpIdx].isOptionalDef())
1441 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1455 unsigned OpIdx = 0;
1458 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1460 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1461 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1469 ++OpIdx;
1475 if (MI.getOperand(OpIdx).isImm() &&
1476 !MCID.OpInfo[OpIdx].isPredicate() &&
1477 !MCID.OpInfo[OpIdx].isOptionalDef())
1478 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1498 unsigned OpIdx = 0;
1501 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1503 const MachineOperand &MO = MI.getOperand(OpIdx++);
1504 if (OpIdx == MCID.getNumOperands() ||
1505 MCID.OpInfo[OpIdx].isPredicate() ||
1506 MCID.OpInfo[OpIdx].isOptionalDef()) {
1517 Binary |= getMachineOpValue(MI, OpIdx++);
1520 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1656 unsigned OpIdx) const {
1657 unsigned RegD = MI.getOperand(OpIdx).getReg();
1672 unsigned OpIdx) const {
1673 unsigned RegN = MI.getOperand(OpIdx).getReg();
1688 unsigned OpIdx) const {
1689 unsigned RegM = MI.getOperand(OpIdx).getReg();
1712 unsigned OpIdx = 0;
1715 Binary |= encodeVFPRd(MI, OpIdx++);
1718 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1719 ++OpIdx;
1723 Binary |= encodeVFPRn(MI, OpIdx++);
1725 if (OpIdx == MCID.getNumOperands() ||
1726 MCID.OpInfo[OpIdx].isPredicate() ||
1727 MCID.OpInfo[OpIdx].isOptionalDef()) {
1734 Binary |= encodeVFPRm(MI, OpIdx);
1808 unsigned OpIdx = 0;
1811 Binary |= encodeVFPRd(MI, OpIdx++);
1814 const MachineOperand &Base = MI.getOperand(OpIdx++);
1819 const MachineOperand &Offset = MI.getOperand(OpIdx);
1847 unsigned OpIdx = 0;
1849 ++OpIdx;
1852 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1863 Binary |= encodeVFPRd(MI, OpIdx+2);
1867 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1904 unsigned OpIdx) const {
1905 unsigned RegD = MI.getOperand(OpIdx).getReg();
1914 unsigned OpIdx) const {
1915 unsigned RegN = MI.getOperand(OpIdx).getReg();
1924 unsigned OpIdx) const {
1925 unsigned RegM = MI.getOperand(OpIdx).getReg();
2017 unsigned OpIdx = 0;
2018 Binary |= encodeNEONRd(MI, OpIdx++);
2019 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2020 ++OpIdx;
2021 Binary |= encodeNEONRm(MI, OpIdx);
2032 unsigned OpIdx = 0;
2033 Binary |= encodeNEONRd(MI, OpIdx++);
2034 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2035 ++OpIdx;
2036 Binary |= encodeNEONRn(MI, OpIdx++);
2037 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2038 ++OpIdx;
2039 Binary |= encodeNEONRm(MI, OpIdx);