Lines Matching refs:VT
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
117 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
123 setOperationAction(ISD::SELECT, VT, Expand);
124 setOperationAction(ISD::SELECT_CC, VT, Expand);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
126 if (VT.isInteger()) {
127 setOperationAction(ISD::SHL, VT, Custom);
128 setOperationAction(ISD::SRA, VT, Custom);
129 setOperationAction(ISD::SRL, VT, Custom);
133 if (VT.isInteger() && VT != PromotedBitwiseVT) {
134 setOperationAction(ISD::AND, VT, Promote);
135 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
136 setOperationAction(ISD::OR, VT, Promote);
137 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
138 setOperationAction(ISD::XOR, VT, Promote);
139 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
143 setOperationAction(ISD::SDIV, VT, Expand);
144 setOperationAction(ISD::UDIV, VT, Expand);
145 setOperationAction(ISD::FDIV, VT, Expand);
146 setOperationAction(ISD::SREM, VT, Expand);
147 setOperationAction(ISD::UREM, VT, Expand);
148 setOperationAction(ISD::FREM, VT, Expand);
151 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
152 addRegisterClass(VT, &ARM::DPRRegClass);
153 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
156 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
157 addRegisterClass(VT, &ARM::QPRRegClass);
158 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
442 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
443 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
446 setTruncStoreAction((MVT::SimpleValueType)VT,
448 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
449 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
450 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
843 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
846 switch (VT.getSimpleVT().SimpleTy) {
848 return TargetLowering::findRepresentativeClass(VT);
1019 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
1020 if (!VT.isVector()) return getPointerTy();
1021 return VT.changeVectorElementTypeToInteger();
1026 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
1031 if (VT == MVT::v4i64)
1033 if (VT == MVT::v8i64)
1036 return TargetLowering::getRegClassFor(VT);
1058 EVT VT = N->getValueType(i);
1059 if (VT == MVT::Glue || VT == MVT::Other)
1061 if (VT.isFloatingPoint() || VT.isVector())
2881 EVT VT = Op.getValueType();
2885 assert(True.getValueType() == VT);
2886 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2902 EVT VT = Op.getValueType();
2914 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2923 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2929 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2945 EVT VT = Op.getValueType();
2946 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3137 EVT VT = Op.getValueType();
3148 if (VT != MVT::v4i16)
3152 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3156 EVT VT = Op.getValueType();
3157 if (VT.isVector())
3177 EVT VT = Op.getValueType();
3181 if (VT.getVectorElementType() == MVT::f32)
3188 if (VT != MVT::v4f32)
3206 return DAG.getNode(Opc, dl, VT, Op);
3210 EVT VT = Op.getValueType();
3211 if (VT.isVector())
3228 return DAG.getNode(Opc, dl, VT, Op);
3236 EVT VT = Op.getValueType();
3247 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3248 if (VT == MVT::f64)
3252 else /*if (VT == MVT::f32)*/
3256 if (VT == MVT::f64)
3260 } else if (VT == MVT::f32)
3276 if (VT == MVT::f32) {
3297 if (VT == MVT::f32) {
3318 EVT VT = Op.getValueType();
3324 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3325 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3331 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3338 EVT VT = Op.getValueType();
3343 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3345 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3395 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3396 assert(VT.isVector() && "Expected a vector type");
3399 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3401 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3409 EVT VT = Op.getValueType();
3410 unsigned VTBits = VT.getSizeInBits();
3422 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3425 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3426 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3427 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3432 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3433 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3445 EVT VT = Op.getValueType();
3446 unsigned VTBits = VT.getSizeInBits();
3456 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3459 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3460 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3462 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3466 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3467 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3494 EVT VT = N->getValueType(0);
3500 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3501 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3506 EVT VT = N->getValueType(0);
3509 if (!VT.isVector())
3517 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3534 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3541 EVT VT = N->getValueType(0);
3545 if (VT != MVT::i64)
3586 EVT VT = Op.getValueType();
3615 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3616 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3624 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3625 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3659 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3660 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3686 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3688 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3690 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3692 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3694 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3696 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3699 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3703 Result = DAG.getNOT(dl, Result, VT);
3713 EVT &VT, bool is128Bits, NEONModImmType type) {
3732 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3737 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3757 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3832 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3896 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
3898 unsigned NumElts = VT.getVectorNumElements();
3935 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
3939 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3943 unsigned NumElts = VT.getVectorNumElements();
3961 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
3965 return VT == MVT::v8i8 && M.size() == 8;
3968 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
3969 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3973 unsigned NumElts = VT.getVectorNumElements();
3986 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
3987 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3991 unsigned NumElts = VT.getVectorNumElements();
4001 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4002 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4006 unsigned NumElts = VT.getVectorNumElements();
4015 if (VT.is64BitVector() && EltSz == 32)
4024 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4025 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4029 unsigned Half = VT.getVectorNumElements() / 2;
4042 if (VT.is64BitVector() && EltSz == 32)
4048 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4049 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4053 unsigned NumElts = VT.getVectorNumElements();
4064 if (VT.is64BitVector() && EltSz == 32)
4073 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4074 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4078 unsigned NumElts = VT.getVectorNumElements();
4089 if (VT.is64BitVector() && EltSz == 32)
4121 EVT VT = Op.getValueType();
4132 DAG, VmovVT, VT.is128BitVector(),
4136 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4143 DAG, VmovVT, VT.is128BitVector(),
4147 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4151 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4155 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4168 unsigned NumElts = VT.getVectorNumElements();
4202 return DAG.getUNDEF(VT);
4205 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4207 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4219 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4222 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4234 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4239 if (VT.getVectorElementType().isFloatingPoint()) {
4248 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4253 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4282 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4293 EVT VT = Op.getValueType();
4294 unsigned NumElts = VT.getVectorNumElements();
4309 VT.getVectorElementType()) {
4350 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4356 if (SourceVecs[i].getValueType() == VT) {
4380 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4386 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4392 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4395 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4398 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4423 if (isShuffleMaskLegal(Mask, VT))
4424 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4436 EVT VT) const {
4437 if (VT.getVectorNumElements() == 4 &&
4438 (VT.is128BitVector() || VT.is64BitVector())) {
4460 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4462 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4463 isVREVMask(M, VT, 64) ||
4464 isVREVMask(M, VT, 32) ||
4465 isVREVMask(M, VT, 16) ||
4466 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4467 isVTBLMask(M, VT) ||
4468 isVTRNMask(M, VT, WhichResult) ||
4469 isVUZPMask(M, VT, WhichResult) ||
4470 isVZIPMask(M, VT, WhichResult) ||
4471 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4472 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4473 isVZIP_v_undef_Mask(M, VT, WhichResult));
4512 EVT VT = OpLHS.getValueType();
4518 if (VT.getVectorElementType() == MVT::i32 ||
4519 VT.getVectorElementType() == MVT::f32)
4520 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4522 if (VT.getVectorElementType() == MVT::i16)
4523 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4525 assert(VT.getVectorElementType() == MVT::i8);
4526 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4531 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4536 return DAG.getNode(ARMISD::VEXT, dl, VT,
4541 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4545 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4549 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4581 EVT VT = Op.getValueType();
4592 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4594 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4601 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4615 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4617 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4623 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4626 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4630 if (isVREVMask(ShuffleMask, VT, 64))
4631 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4632 if (isVREVMask(ShuffleMask, VT, 32))
4633 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4634 if (isVREVMask(ShuffleMask, VT, 16))
4635 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4643 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4644 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4646 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4647 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4649 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4650 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4653 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4654 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4656 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4657 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4659 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4660 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4666 unsigned NumElts = VT.getVectorNumElements();
4705 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4708 if (VT == MVT::v8i8) {
4768 EVT VT = N->getValueType(0);
4769 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4799 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4858 EVT VT = N->getValueType(0);
4859 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4860 unsigned NumElts = VT.getVectorNumElements();
4899 EVT VT = Op.getValueType();
4900 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4931 if (VT == MVT::v2i64)
4949 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4963 return DAG.getNode(N0->getOpcode(), DL, VT,
4964 DAG.getNode(NewOpc, DL, VT,
4966 DAG.getNode(NewOpc, DL, VT,
5037 EVT VT = Op.getValueType();
5038 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5046 if (VT == MVT::v8i8) {
5072 EVT VT = Op.getValueType();
5073 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5081 if (VT == MVT::v8i8) {
5146 EVT VT = Op.getNode()->getValueType(0);
5147 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
7071 EVT VT = N->getValueType(0);
7079 OtherOp = DAG.getConstant(0, VT);
7082 OtherOp = DAG.getConstant(1, VT);
7084 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7119 EVT VT = N->getValueType(0);
7129 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
7135 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
7172 EVT VT = N->getValueType(0);
7173 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7233 unsigned numElem = VT.getVectorNumElements();
7234 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
7244 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
7476 EVT VT = N->getValueType(0);
7480 return DAG.getNode(Opcode, DL, VT,
7481 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
7482 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
7496 EVT VT = N->getValueType(0);
7497 if (VT.is64BitVector() || VT.is128BitVector())
7499 if (VT != MVT::i32)
7519 Res = DAG.getNode(ISD::ADD, DL, VT,
7521 DAG.getNode(ISD::SHL, DL, VT,
7527 Res = DAG.getNode(ISD::SUB, DL, VT,
7528 DAG.getNode(ISD::SHL, DL, VT,
7539 Res = DAG.getNode(ISD::SUB, DL, VT,
7541 DAG.getNode(ISD::SHL, DL, VT,
7547 Res = DAG.getNode(ISD::ADD, DL, VT,
7549 DAG.getNode(ISD::SHL, DL, VT,
7553 Res = DAG.getNode(ISD::SUB, DL, VT,
7561 Res = DAG.getNode(ISD::SHL, DL, VT,
7576 EVT VT = N->getValueType(0);
7579 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7591 DAG, VbicVT, VT.is128BitVector(),
7597 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
7619 EVT VT = N->getValueType(0);
7622 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7634 DAG, VorrVT, VT.is128BitVector(),
7640 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
7661 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
7662 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
7677 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
7681 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
7704 if (VT != MVT::i32)
7730 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
7756 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
7758 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
7772 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
7774 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
7793 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
7806 EVT VT = N->getValueType(0);
7809 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7917 EVT VT = StVal.getValueType();
7918 if (St->isTruncatingStore() && VT.isVector()) {
7922 unsigned NumElems = VT.getVectorNumElements();
7923 assert(StVT != VT && "Cannot truncate to the same type");
7924 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
7935 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
7940 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
7970 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
7971 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8075 EVT VT = N->getValueType(0);
8076 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8080 unsigned NumElts = VT.getVectorNumElements();
8089 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8098 EVT VT = N->getValueType(0);
8100 if (VT.getVectorElementType() != MVT::i64 ||
8107 VT.getVectorNumElements());
8115 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8145 EVT VT = N->getValueType(0);
8146 if (!TLI.isTypeLegal(VT) ||
8151 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
8155 unsigned NumElts = VT.getVectorNumElements();
8167 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
8168 DAG.getUNDEF(VT), NewMask.data());
8309 EVT VT = N->getValueType(0);
8311 if (!VT.is64BitVector())
8353 Tys[n] = VT;
8409 EVT VT = N->getValueType(0);
8410 if (EltSize > VT.getVectorElementType().getSizeInBits())
8413 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
8537 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
8538 assert(VT.isVector() && "vector shift count is not a vector type");
8539 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8551 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
8553 assert(VT.isVector() && "vector shift count is not a vector type");
8554 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8592 EVT VT = N->getOperand(1).getValueType();
8599 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
8603 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
8612 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
8618 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
8624 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
8629 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
8642 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
8658 if (Cnt == VT.getVectorElementType().getSizeInBits())
8697 EVT VT = N->getOperand(1).getValueType();
8701 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
8703 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
8730 EVT VT = N->getValueType(0);
8731 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
8740 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1);
8746 if (!VT.isVector() || !TLI.isTypeLegal(VT))
8756 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
8757 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
8763 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
8766 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
8786 EVT VT = N->getValueType(0);
8790 if (VT == MVT::i32 &&
8806 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
8906 EVT VT = N->getValueType(0);
8935 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8940 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9023 EVT VT) const {
9024 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9027 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
9031 switch (VT.getSimpleVT().SimpleTy) {
9079 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9084 switch (VT.getSimpleVT().SimpleTy) {
9106 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
9114 switch (VT.getSimpleVT().SimpleTy) {
9139 static bool isLegalAddressImmediate(int64_t V, EVT VT,
9144 if (!VT.isSimple())
9148 return isLegalT1AddressImmediate(V, VT);
9150 return isLegalT2AddressImmediate(V, VT, Subtarget);
9155 switch (VT.getSimpleVT().SimpleTy) {
9177 EVT VT) const {
9182 switch (VT.getSimpleVT().SimpleTy) {
9213 EVT VT = getValueType(Ty, true);
9214 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9233 if (!VT.isSimple())
9237 return isLegalT2ScaledAddressingMode(AM, VT);
9240 switch (VT.getSimpleVT().SimpleTy) {
9299 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
9306 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
9321 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
9358 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
9394 EVT VT;
9399 VT = LD->getMemoryVT();
9403 VT = ST->getMemoryVT();
9410 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9413 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9433 EVT VT;
9437 VT = LD->getMemoryVT();
9441 VT = ST->getMemoryVT();
9449 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9452 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9594 EVT VT) const {
9609 if (VT == MVT::f32)
9611 if (VT.getSizeInBits() == 64)
9613 if (VT.getSizeInBits() == 128)
9617 if (VT == MVT::f32)
9619 if (VT.getSizeInBits() == 64)
9621 if (VT.getSizeInBits() == 128)
9625 if (VT == MVT::f32)
9633 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9827 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
9830 if (VT == MVT::f32)
9832 if (VT == MVT::f64)