Lines Matching refs:VT
39 int prefslotOffset(EVT VT) {
41 if (VT==MVT::i1) retval=3;
42 if (VT==MVT::i8) retval=3;
43 if (VT==MVT::i16) retval=2;
135 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
137 setOperationAction(ISD::LOAD, VT, Custom);
138 setOperationAction(ISD::STORE, VT, Custom);
139 setLoadExtAction(ISD::EXTLOAD, VT, Custom);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, Custom);
141 setLoadExtAction(ISD::SEXTLOAD, VT, Custom);
145 setTruncStoreAction(VT, StoreVT, Expand);
151 MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype;
153 setOperationAction(ISD::LOAD, VT, Custom);
154 setOperationAction(ISD::STORE, VT, Custom);
158 setTruncStoreAction(VT, StoreVT, Expand);
371 MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype;
373 setOperationAction(ISD::GlobalAddress, VT, Custom);
374 setOperationAction(ISD::ConstantPool, VT, Custom);
375 setOperationAction(ISD::JumpTable, VT, Custom);
411 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
414 if (!isTypeLegal(VT)) continue;
416 // add/sub are legal for all supported vector VT's.
417 setOperationAction(ISD::ADD, VT, Legal);
418 setOperationAction(ISD::SUB, VT, Legal);
420 setOperationAction(ISD::MUL, VT, Legal);
422 setOperationAction(ISD::AND, VT, Legal);
423 setOperationAction(ISD::OR, VT, Legal);
424 setOperationAction(ISD::XOR, VT, Legal);
425 setOperationAction(ISD::LOAD, VT, Custom);
426 setOperationAction(ISD::SELECT, VT, Legal);
427 setOperationAction(ISD::STORE, VT, Custom);
430 setOperationAction(ISD::SDIV, VT, Expand);
431 setOperationAction(ISD::SREM, VT, Expand);
432 setOperationAction(ISD::UDIV, VT, Expand);
433 setOperationAction(ISD::UREM, VT, Expand);
439 setTruncStoreAction(VT, TargetVT, Expand);
444 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
445 setOperationAction(ISD::ConstantPool, VT, Custom);
446 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
447 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
448 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
449 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
516 EVT SPUTargetLowering::getSetCCResultType(EVT VT) const {
520 switch(VT.getSimpleVT().SimpleTy){
772 EVT VT = Value.getValueType();
773 EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT());
876 if (StVT != VT
928 DAG.getConstant( VT.getSizeInBits()/8,
941 if (!VT.isVector()){
1096 EVT VT = Op.getValueType();
1100 if (VT == MVT::f64) {
1109 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
1144 EVT ObjectVT = Ins[ArgNo].VT;
1659 EVT VT = Op.getValueType();
1660 EVT EltVT = VT.getVectorElementType();
1680 switch (VT.getSimpleVT().SimpleTy) {
1682 report_fatal_error("CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " +
1683 Twine(VT.getEVTString()));
1709 return DAG.getNode(ISD::BITCAST, dl, VT,
1718 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1721 SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType());
1722 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T);
1725 return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl);
1967 EVT VT;
1974 case MVT::v16i8: n_copies = 16; VT = MVT::i8; break;
1975 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
1976 case MVT::v4i32: n_copies = 4; VT = MVT::i32; break;
1977 case MVT::v4f32: n_copies = 4; VT = MVT::f32; break;
1978 case MVT::v2i64: n_copies = 2; VT = MVT::i64; break;
1979 case MVT::v2f64: n_copies = 2; VT = MVT::f64; break;
1982 SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT);
2004 EVT VT = Op.getValueType();
2015 if (VT == MVT::i8 && EltNo >= 16)
2017 else if (VT == MVT::i16 && EltNo >= 8)
2019 else if (VT == MVT::i32 && EltNo >= 4)
2021 else if (VT == MVT::i64 && EltNo >= 2)
2024 if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) {
2026 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N);
2031 int elt_byte = EltNo * VT.getSizeInBits() / 8;
2033 switch (VT.getSimpleVT().SimpleTy) {
2090 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2124 switch (VT.getSimpleVT().SimpleTy) {
2158 retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT,
2171 EVT VT = Op.getValueType();
2188 EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(),
2189 128/ VT.getVectorElementType().getSizeInBits());
2193 DAG.getNode(SPUISD::SHUFB, dl, VT,
2194 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp),
2305 EVT VT = Op.getValueType();
2329 unsigned minSplatBits = VT.getVectorElementType().getSizeInBits();
2339 return DAG.getNode(Op.getNode()->getOpcode(), dl, VT, Arg,
2340 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &tcVec[0], tcVec.size()));
2356 EVT VT = Op.getValueType();
2358 VT, (128 / VT.getSizeInBits()));
2361 switch (VT.getSimpleVT().SimpleTy) {
2649 EVT VT = Op.getValueType();
2671 return DAG.getNode(SPUISD::SELB, dl, VT, falseval, trueval, compare);
2678 EVT VT = Op.getValueType();
2679 MVT simpleVT = VT.getSimpleVT();
2681 VT, (128 / VT.getSizeInBits()));
2702 return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, truncShuffle);
2782 EVT VT = Op.getValueType();
2818 if (VT == MVT::i8)
2851 if (VT == MVT::i8)
3141 EVT VT) const
3148 if (VT == MVT::i64)
3152 if (VT == MVT::f32)
3154 if (VT == MVT::f64)
3162 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3205 EVT VT = Op.getValueType();
3207 if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) {
3208 VT = MVT::i32;
3210 return VT.getSizeInBits();