Lines Matching defs:RegVT
1892 EVT RegVT = VA.getLocVT();
1894 if (RegVT == MVT::i32)
1896 else if (Is64Bit && RegVT == MVT::i64)
1898 else if (RegVT == MVT::f32)
1900 else if (RegVT == MVT::f64)
1902 else if (RegVT.is256BitVector())
1904 else if (RegVT.is128BitVector())
1906 else if (RegVT == MVT::x86mmx)
1912 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1918 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1921 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1928 if (RegVT.isVector()) {
2266 EVT RegVT = VA.getLocVT();
2276 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2279 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2282 if (RegVT.is128BitVector()) {
2288 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2291 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
15074 EVT RegVT = Ld->getValueType(0);
15085 if (RegVT.isVector() && RegVT.isInteger() &&
15087 assert(MemVT != RegVT && "Cannot extend to the same type");
15090 unsigned NumElems = RegVT.getVectorNumElements();
15091 unsigned RegSz = RegVT.getSizeInBits();
15178 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);