Cross Reference: /external/llvm/lib/Target/X86/X86ISelLowering.cpp

Lines Matching refs:EAX
538     setExceptionPointerRegister(X86::EAX);
2870     // only target EAX, EDX, or ECX since the tail call must be scheduled after
2884         case X86::EAX: case X86::EDX: case X86::ECX:
7488   return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7519     Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7661     unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8152     SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
9447     unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10400       // Pass 'nest' parameter in EAX.
10402       NestReg = X86::EAX;
11133   case MVT::i32: Reg = X86::EAX; size = 4; break;
11425     SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11446                              Regs64bit ? X86::RAX : X86::EAX,
11472                                         Regs64bit ? X86::RAX : X86::EAX,
11831   //     mov EAX = t1
11832   //     lcs dest = [bitinstr.addr], t3  [EAX is implicit]
11937   //     mov EAX, EDX <- t1, t2
11938   //     cmpxchg8b [bitinstr.addr]  [EAX, EDX, EBX, ECX implicit]
11939   //     mov t3, t4 <- EAX, EDX
12059   MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
12078   MIB.addReg(X86::EAX);
12101   //     mov EAX = t1
12102   //     lcs dest = [bitinstr.addr], t2  [EAX is implicit]
12163   MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
12186   MIB.addReg(X86::EAX);
12238   // Address into RAX/EAX, other two args into ECX, EDX.
12240   unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12782       .addReg(X86::EAX, RegState::ImplicitDefine);
12790     .addReg(Is64Bit ? X86::RAX : X86::EAX);
12854       .addReg(X86::EAX, RegState::Implicit)
12856       .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12870   // or EAX and doing an indirect call.  The return value will then
12898                                       TII->get(X86::MOV32rm), X86::EAX)
12905     addDirectMem(MIB, X86::EAX);
12906     MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12909                                       TII->get(X86::MOV32rm), X86::EAX)
12916     addDirectMem(MIB, X86::EAX);
12917     MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13130                                                X86::NOT32r, X86::EAX,
16785     // 'A' means EAX + EDX.
16787       Res.first = X86::EAX;
16822       case X86::AX: DestReg = X86::EAX; break;