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Searched defs:OpIdx (Results 1 - 11 of 11) sorted by relevance

/external/llvm/include/llvm/Analysis/
H A D	ConstantsScanner.h	`28 unsigned OpIdx; // Operand index member in class:llvm::constant_iterator 33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() && 35 return isa<Constant>(InstI->getOperand(OpIdx)); 39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) { 47 : InstI(inst_end(F)), OpIdx(0) { 50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx && 56 return cast<Constant>(InstI->getOperand(OpIdx)); 61 ++OpIdx; 64 while (OpIdx < NumOperand [all...]`
/external/llvm/utils/TableGen/
H A D	CodeEmitterGen.cpp	`130 unsigned OpIdx; local 131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { 133 OpIdx = CGI.Operands[OpIdx].MIOperandNo; 134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && 141 OpIdx = NumberedOp++; 144 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); 155 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); 162 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";`
H A D	CodeGenInstruction.cpp	`135 unsigned OpIdx; local 136 if (hasOperandNamed(Name, OpIdx)) return OpIdx; 142 /// given name. If so, return true and set OpIdx to the index of the 144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const { 148 OpIdx = i; 171 unsigned OpIdx = getOperandNamed(OpName); local 175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp && 181 return std::make_pair(OpIdx, 0U); 185 DagInit *MIOpInfo = OperandList[OpIdx] [all...]`
/external/llvm/include/llvm/CodeGen/
H A D	ScheduleDAGInstrs.h	`112 /// For non data-dependent uses, OpIdx == -1. 115 int OpIdx; member in struct:llvm::PhysRegSUOper 117 PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}`
/external/llvm/lib/CodeGen/
H A D	MachineLICM.cpp	`247 unsigned Reg, unsigned OpIdx, 780 unsigned Reg, unsigned OpIdx, 779 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument`
H A D	RegisterCoalescer.cpp	`628 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); local 629 NewMI->getOperand(OpIdx).setIsKill();`
/external/llvm/lib/Target/ARM/
H A D	ARMExpandPseudoInsts.cpp	385 unsigned OpIdx = 0; local 387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 400 MIB.addOperand(MI.getOperand(OpIdx++)); 403 MIB.addOperand(MI.getOperand(OpIdx++)); 404 MIB.addOperand(MI.getOperand(OpIdx++)); 407 MIB.addOperand(MI.getOperand(OpIdx++)); 414 SrcOpIdx = OpIdx++; 417 MIB.addOperand(MI.getOperand(OpIdx++)); 418 MIB.addOperand(MI.getOperand(OpIdx 450 unsigned OpIdx = 0; local 502 unsigned OpIdx = 0; local 585 unsigned OpIdx = 0; local 947 unsigned OpIdx = 0; local 978 unsigned OpIdx = 0; local 1010 unsigned OpIdx = 0; local [all...]
H A D	ARMCodeEmitter.cpp	103 unsigned OpIdx); 156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 157 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 376 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) cons 1010 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument 1111 unsigned OpIdx = 0; local 1219 unsigned OpIdx = 0; local 1290 unsigned OpIdx = 0; local 1380 unsigned OpIdx = 0; local [all...]
H A D	ARMBaseInstrInfo.cpp	`2328 unsigned OpIdx = Commute ? 2 : 1; local 2329 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg(); 2330 bool isKill = UseMI->getOperand(OpIdx).isKill();`
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A D	ARMMCCodeEmitter.cpp	80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, 83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, 89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, 94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, 98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, 102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, 106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, 111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, 169 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const argument 462 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups) argument 499 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 511 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 522 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 533 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 544 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 572 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 585 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 600 getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 614 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 626 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 649 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 676 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 695 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 707 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &) const argument 721 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 770 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 801 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 841 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 866 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 925 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 954 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 968 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 990 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1001 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1020 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1056 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1071 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1085 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1095 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1133 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument 1180 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument [all...]
/external/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	`4653 /// starting from its index OpIdx. Also tell OpNum which source vector operand. 4656 unsigned MaskI, unsigned MaskE, unsigned OpIdx, 4661 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) { 4673 if ((Idx % NumElems != OpIdx) \|\| (SeenV1 && SeenV2)) 4655 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, unsigned MaskI, unsigned MaskE, unsigned OpIdx, unsigned NumElems, unsigned &OpNum) argument`

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