Searched defs:Opc (Results 1 - 25 of 75) sorted by relevance

123

/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMips16InstrInfo.cpp61 unsigned Opc = 0, ZeroReg = 0; local
65 Opc = Mips::Mov32R16;
68 assert(Opc && "Cannot copy registers");
70 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
115 unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
120 unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
126 unsigned Opc) const {
127 BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
H A DMipsInstrInfo.cpp77 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, argument
80 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch");
86 Cond.push_back(MachineOperand::CreateImm(Opc));
176 unsigned Opc = Cond[0].getImm(); local
177 const MCInstrDesc &MCID = get(Opc);
H A DMipsSEInstrInfo.cpp44 unsigned Opc = MI->getOpcode(); local
46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) ||
49 (Opc
69 unsigned Opc = MI->getOpcode(); local
89 unsigned Opc = 0, ZeroReg = 0; local
163 unsigned Opc = 0; local
190 unsigned Opc = 0; local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp76 int Opc = MI->getOpcode(); local
77 if (Opc == Hexagon::STriw_pred) {
121 } else if (Opc == Hexagon::LDriw_pred) {
H A DHexagonCFGOptimizer.cpp53 static bool IsConditionalBranch(int Opc) { argument
54 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot)
55 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt);
59 static bool IsUnconditionalJump(int Opc) { argument
60 return (Opc == Hexagon::JMP);
106 int Opc = MI->getOpcode(); local
107 if (IsConditionalBranch(Opc)) {
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
335 bool isUncondBranchOpcode(int Opc) { argument
336 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
340 bool isCondBranchOpcode(int Opc) { argument
341 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
345 isJumpTableBranchOpcode(int Opc) argument
351 isIndirectBranchOpcode(int Opc) argument
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H A DThumb1RegisterInfo.cpp129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); local
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
132 if (Opc != ARM::tADDhirr)
143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, argument
148 if (Opc == ARM::tADDrSPi) {
182 int Opc = 0;
190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
203 Opc = ARM::tADDrSPi;
212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
217 Opc
328 unsigned Opc = Old->getOpcode(); local
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp142 unsigned Opc = PI->getOpcode(); local
143 if (Opc != MSP430::POP16r && !PI->isTerminator())
H A DMSP430InstrInfo.cpp92 unsigned Opc; local
94 Opc = MSP430::MOV16rr;
96 Opc = MSP430::MOV8rr;
100 BuildMI(MBB, I, DL, get(Opc), DestReg)
H A DMSP430ISelDAGToDAG.cpp364 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); local
369 CurDAG->SelectNodeTo(Op, Opc,
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp101 unsigned Opc = N->getOpcode(); local
102 if (Opc != ISD::Constant)
213 unsigned Opc = MBlaze::ADDIK; local
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
H A DMBlazeInstrInfo.cpp196 unsigned Opc = MBlaze::BRID; local
198 Opc = (unsigned)Cond[0].getImm();
202 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
204 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
208 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()).addMBB(TBB);
H A DMBlazeInstrInfo.h144 inline static bool isUncondBranchOpcode(int Opc) { argument
145 switch (Opc) {
155 inline static bool isCondBranchOpcode(int Opc) { argument
156 switch (Opc) {
/external/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp107 unsigned Opc = MBBI->getOpcode(); local
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(Is64Bit);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc
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H A DX86RegisterInfo.cpp485 unsigned Opc = getADDriOpcode(Is64Bit, Amount); local
486 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
506 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt); local
507 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
541 unsigned Opc = MI.getOpcode();
542 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
/external/llvm/include/llvm/Support/
H A DConstantFolder.h97 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
99 return ConstantExpr::get(Opc, LHS, RHS);
H A DTargetFolder.h109 Constant *CreateBinOp(Instruction::BinaryOps Opc, argument
111 return Fold(ConstantExpr::get(Opc, LHS, RHS));
H A DNoFolder.h147 Instruction *CreateBinOp(Instruction::BinaryOps Opc, argument
149 return BinaryOperator::Create(Opc, LHS, RHS);
/external/llvm/lib/MC/
H A DMCExpr.cpp148 const MCBinaryExpr *MCBinaryExpr::Create(Opcode Opc, const MCExpr *LHS, argument
150 return new (Ctx) MCBinaryExpr(Opc, LHS, RHS);
153 const MCUnaryExpr *MCUnaryExpr::Create(Opcode Opc, const MCExpr *Expr, argument
155 return new (Ctx) MCUnaryExpr(Opc, Expr);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, argument
410 bool isSub = Opc == sub;
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
493 bool isSub = Opc == sub;
/external/llvm/lib/Target/CellSPU/
H A DSPUInstrInfo.cpp426 unsigned Opc; //! The incoming opcode member in struct:__anon9483
439 unsigned Opc = unsigned(Cond[0].getImm()); local
442 if (revconds[i].Opc == Opc) {
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); local
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); local
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp417 unsigned Opc; local
419 Opc = PPC::OR;
421 Opc = PPC::OR8;
423 Opc = PPC::FMR;
425 Opc = PPC::MCRF;
427 Opc = PPC::VOR;
429 Opc = PPC::CROR;
433 const MCInstrDesc &MCID = get(Opc);
/external/llvm/include/llvm/
H A DInstrTypes.h196 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
198 BinaryOperator *BO = Create(Opc, V1, V2, Name);
202 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
204 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
208 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
210 BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
215 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
217 BinaryOperator *BO = Create(Opc, V1, V2, Name);
221 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
223 BinaryOperator *BO = Create(Opc, V
227 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
234 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = Ó) argument
240 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
246 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
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