fc4eafa0f490bd06d8191a2f007514b9e3ce0387 |
|
23-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make function loadImmediate a member of MipsSEInstrInfo and change it to return the temporary register that was used to load the immediate. Currently, it always returns register $at, but this will change if, in the future, we decide to use another register. No changes in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
af2662606745bdebaa2cb43096274ce3d33b665f |
|
02-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Move the code that creates instances of MipsInstrInfo and MipsFrameLowering out of MipsTargetMachine.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
8589010e3d1d5a902992a5039cffa9d4116982c5 |
|
01-Aug-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
0bc1adbbc4fdc6d85a671ed70a1bbd345dba445d |
|
31-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16), and MipsSEInstrInfo (for mips32/64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
3ee306cbc0a295409c464ffaad5ef694de8eb09a |
|
24-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add basic ability to setup call frame, and make procedure calls. Hello world will compile and execute with this patch. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
fef904d0e824a2c587f8c1063b6c4fbf47fec898 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Revert accidental commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160598 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
b7dd9fc678ab4b4c57d333cd9940b0e0d7952ea6 |
|
21-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add VK_Mips_HIGHER and VK_Mips_HIGHEST to MCSymbolRefExpr::VariantKind. Test case will be added later when long branch patch is checked in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 |
|
10-Jul-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Make register Mips::RA allocatable if not in mips16 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
864f66085cd9543070ef01b9f7371c110ecd7898 |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Fix coding style violations. Remove white spaces and tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
d4b48b283c3939962f0cd3c17aedc40209d82b1a |
|
14-Jun-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Define function MipsInstrInfo::GetInstSizeInBytes, which will be called to compute the size of basic blocks in a function. Also, define a function which emits a series of instructions to load an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
6c823822cdab902e8ecc52603f9c24a0e4b95d42 |
|
30-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix some uses of getSubRegisters() to use getSubReg() instead. It is better to address sub-registers directly by name instead of relying on their position in the sub-register list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
564f69072c4569e2d603c335a6ddc61adf94ebb2 |
|
25-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Move the code in MipsExpandPseudo to MipsInstrInfo::expandPostRAPseudo. Delete MipsExpandPseudo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
66e19c3e9db6e2727be21074a52f5c9fa187050f |
|
17-May-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
This patch adds the register class for MIPS16 as well as the ability for llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
bb481f882093fb738d2bb15610c79364bada5496 |
|
28-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove blanks, and some code format git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
648f00c2f0eb29c0ae2a333fa0bfa55970059f08 |
|
24-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add an option to use a virtual register as the global base register instead of reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
c5707112e7635d1dd2f2cc9c4f42e79a51302cca |
|
17-Feb-2012 |
Jia Liu <proljc@gmail.com> |
remove Emacs-tag form .cpp files in Mips Backend, and fix some typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
6c2cf8b1fbcf70fd9db6fe44032c1ceaa2299760 |
|
03-Feb-2012 |
Akira Hatanaka <ahatanaka@mips.com> |
Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
fd1d9250b2b85ae4c6e7ae1a512bf6ea56af3c97 |
|
24-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add MachineMemOperands to instructions generated in storeRegToStackSlot or loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
82099683060abb1f74453d06e78a3729a75ef7ee |
|
19-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Tidy up. Simplify logic. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
6e55ff56b88c3334d5847f2cb26f3001b92c489b |
|
12-Dec-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Emit B (unconditional branch) when -relocation-model=pic and J (jump) when -relocation-model=static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146432 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
ff452f53498229668af8e7476efc151c5a227be5 |
|
06-Dec-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Use branches instead of jumps + variable cleanup. Testcase coming next. Patch by Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145912 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
29d525a3edf6df1e7797ecb60ebfa445a27e37c6 |
|
07-Nov-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add code needed for copying between 64-bit integer and floating pointer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
3e3427a5c3fe8303723129207ce1864bee8fa481 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Add support for conditional branch instructions with 64-bit register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
1acb7df498485249d92f62febeaefd91cae3d98c |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Make changes necessary for supporting floating point load and store instructions that have 64-bit pointers or access the 32 x 64-bit floating pointer register file. Update functions in MipsInstrInfo.cpp too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
43aed32e20cea35bbe74bc5a460fb8b3f6e930b1 |
|
11-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141613 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
4391bb75ecce0fe06dc6af8ad05b737da6a088e0 |
|
08-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Simplify definition of FP move instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
2ad766851d881f8700f8392ed626e343fddb8140 |
|
03-Oct-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
5cd4ee7770d5e7dad78398b78cd7b1f5812d21e1 |
|
29-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert r140731, "Define classes for unary and binary FP instructions and use them to define" It broke the unit tests. Please reapply with tests fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
d42ca4607b840b65141b42788b5fef6c08e22aa6 |
|
28-Sep-2011 |
Akira Hatanaka <ahatanaka@mips.com> |
Define classes for unary and binary FP instructions and use them to define multiclasses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
|
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong. These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
614051a1c534aff052152b0162a414b3271e8fca |
|
16-Aug-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix handling of double precision loads and stores when Mips1 is targeted. Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
59ee62d2418df8db499eca1ae17f5900dc2dcbba |
|
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
794bf17cbe0bac301ef9e52fb4a0295bfdfe0cab |
|
08-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Lower MachineInstr to MC Inst and print to .s files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
d3ac47f80551d95c64cb41c3f94e888d7e13275b |
|
07-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse order of operands of address operand mem so that the base operand comes before the offset. This change will enable simplification of function MipsRegisterInfo::eliminateFrameIndex. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
c4f24eb584f6b4dba3caba2ed766c7c4bf1bf8af |
|
01-Jul-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Improve Mips back-end's handling of DBG_VALUE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
d5b03f252c0db6b49a242abab63d7c5a260fceae |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
22fee2dff4c43b551aefa44a96ca74fcade6bfac |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
4552c9a3b34ad9b2085635266348d0d9b95514a6 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
0bf3dfbef60e36827df9c7e12b62503f1e345cd0 |
|
15-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
20ada98de82cb23c3f075acbb09436760ef0923c |
|
01-Apr-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Add code for analyzing FP branches. Clean up branch Analysis functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
1d6b38d9d37d5de471f5954b23b46dac58136fec |
|
31-Mar-2011 |
Akira Hatanaka <ahatanak@gmail.com> |
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
81092dc20abe5253a5b4d48a75997baa84dde196 |
|
04-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
78e6e009223a38739797629ca2d217acf86dda93 |
|
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
600f171486708734e2b9c9c617528cfc51c16850 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free. The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
273c14f5300ccf94459bed02964b4161a7338e79 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
3ecf1f0179b678437600da322d029ab77726409c |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use COPY in targets git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
3bf912593301152b65accb9d9c37a95172f1df5a |
|
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
9f2cda73e470673ab63509adc9d096b0a1d13c54 |
|
05-May-2010 |
Dan Gohman <gohman@apple.com> |
No-ops emitted for scheduling don't correspond with anything in the user's source, so don't arbitrarily assign them a debug location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
93d6a7e9c21204c52d6efec6c672163e7de79660 |
|
02-Apr-2010 |
Dale Johannesen <dalej@apple.com> |
Teach AnalyzeBranch, RemoveBranch and the branch folder to be tolerant of debug info following the branch(es) at the end of a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
ea982789354af0d24ea55021a5fc2178d4647980 |
|
19-Jan-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
load f64 +0.0 in a cleaner way. This fix part of PR5445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
302525b2346e23e00272263ff061258f476c95a2 |
|
25-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add proper emission of load/store double to stack slots for mips1 targets! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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a8173b934fdfdc7a3ca543a0734b7c8fa1969366 |
|
13-Nov-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support fp64 immediate zero, this fixes only part of PR5445 because the testcase is triggering one more bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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23ed52752bb40a9085c9d36bbc6603972c3e0080 |
|
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE. Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
430506924dd2afe4f118e785ae8b38f8677c2428 |
|
03-Jul-2009 |
Duncan Sands <baldrick@free.fr> |
Silence a warning when assertions are turned off. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
2578ba26e72e36dde64be0f52a2788480aad3378 |
|
01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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9911405183f8596fe9d521467f83f6652a296cf4 |
|
03-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Convert Alpha and Mips to use a MachineFunctionInfo subclass to carry GlobalBaseReg, and GlobalRetAddr too in Alpha's case. This eliminates the need for them to search through the MachineRegisterInfo livein list in order to identify these virtual registers. EmitLiveInCopies is now the only user of the virtual register portion of MachineRegisterInfo's livein data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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d3bdf19ce7a37e23a6c4d877fb681eb010be74f7 |
|
27-May-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added support for fround, fextend and FP_TO_SINT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
|
587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
|
13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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e3a85838dafdc510c4cbb45c01305b612f23b20e |
|
26-Mar-2009 |
Chris Lattner <sabre@nondot.org> |
fix some warnings in release-asserts mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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bdfbb74d34dafba3c5638fdddd561043823ebdd2 |
|
21-Mar-2009 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Removed AFGR32 register class Handle odd registers allocation in FGR32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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97357614b5957cc167c261d3be54713802715d9a |
|
18-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Factor out the code to add a MachineOperand to a MachineInstrBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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948175785d1e5e7d3d627d11dbb0392b976d135d |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc versions of BuildMI from IA64, Mips. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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21b5541814d57d0a31f353948e4e933dbb1af6a4 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate a couple of non-DebugLoc BuildMI variants. Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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d1c321a89ab999b9bb602b0f398ecd4c2022262c |
|
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
|
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
|
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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c54baa2d43730f1804acfb4f4e738fba72f966bd |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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8e8b8a223c2b0e69f44c0639f846260c8011668f |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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d735b8019b0f297d7c14b55adcd887af24d8e602 |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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940f83e772ca2007d62faffc83094bd7e8da6401 |
|
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
|
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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91ef849e6cb01a019dc50ed4e95c058e01616062 |
|
02-Aug-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Improved asm inline for hi,lo results Added hi,lo registers to be used,def implicitly. This provides better handle of instructions which use hi/lo. Fixes a small BranchAnalysis bug git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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85e31e3a5301c31947e35258dce7efa8e788bd51 |
|
28-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added floating point lowering for setcc and brcond. Fixed COMM asm directive usage. ConstantPool using custom FourByteConstantSection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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43d526d162c69f29a1cc6734014576eade49529b |
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14-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added Subtarget support into RegisterInfo Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and -mno-shared). HasAbsoluteCall is not implemented but HasABICall is the default for o32 ABI. Now, both should help into a more accurate relocation types implementation. Added IsLinux is needed to choose between asm directives. Instruction name strings cleanup. AsmPrinter improved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53551 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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7b76da145be2b3b7518ca42b43a903eabd52e1b7 |
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09-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fixe typos and 80 column size problems git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
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08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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225ca9cdd70de3d12641b0aba7daf6cb568a7ebd |
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05-Jul-2008 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Several changes to Mips backend, experimental fp support being the most important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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9f1c8317a4676945b4961ddb9827ef2412551620 |
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03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
- Remove calls to copyKillDeadInfo which is an N^2 function. Instead, propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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5fd79d0560570fed977788a86fa038b898564dfa |
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08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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749c6f6b5ed301c84aac562e414486549d7b98eb |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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349c4952009525b27383e2120a6b3c998f39bd09 |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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69244300b8a0112efb44b6273ecea4ca6264b8cf |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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43dbe05279b753aabda571d9c83eaeb36987001a |
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07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo. Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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f6372aa1cc568df19da7c5023e83c75aa9404a07 |
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01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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641055225092833197efe8e5bce01d50bcf1daae |
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01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
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31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the Machine-level API cleanup instigated by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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8aa797aa51cd4ea1ec6f46f4891a6897944b75b2 |
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31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Add new shorter predicates for testing machine operands for various types: e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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9a1ceaedc282f0cae31f2723f4d6c00c7b88fe90 |
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30-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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4ee451de366474b9c228b4e5fa573795a715216d |
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29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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718cb665ca6ce2bc4d8e8479f46a45db91b49f86 |
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07-Sep-2007 |
Owen Anderson <resistor@mac.com> |
Add lengthof and endof templates that hide a lot of sizeof computations. Patch by Sterling Stein! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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35d2a47994af0694b4301bcfdf9cf8bbd726b487 |
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18-Aug-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Added Branch Analysis support Added InsertNoop support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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972f5896e417d8e81cf400083fab15a37b6d4277 |
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06-Jun-2007 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Initial Mips support, here we go! =) - Modifications from the last patch included (issues pointed by Evan Cheng are now fixed). - Added more MipsI instructions. - Added more patterns to match branch instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37461 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/Mips/MipsInstrInfo.cpp
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