MipsInstrInfo.cpp revision d3ac47f80551d95c64cb41c3f94e888d7e13275b
1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsInstrInfo.h" 15#include "MipsTargetMachine.h" 16#include "MipsMachineFunction.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineRegisterInfo.h" 20#include "llvm/Support/ErrorHandling.h" 21 22#define GET_INSTRINFO_CTOR 23#define GET_INSTRINFO_MC_DESC 24#include "MipsGenInstrInfo.inc" 25 26using namespace llvm; 27 28MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) 29 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), 30 TM(tm), RI(*TM.getSubtargetImpl(), *this) {} 31 32static bool isZeroImm(const MachineOperand &op) { 33 return op.isImm() && op.getImm() == 0; 34} 35 36/// isLoadFromStackSlot - If the specified machine instruction is a direct 37/// load from a stack slot, return the virtual or physical register number of 38/// the destination along with the FrameIndex of the loaded stack slot. If 39/// not, return 0. This predicate must return 0 if the instruction has 40/// any side effects other than loading from the stack slot. 41unsigned MipsInstrInfo:: 42isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const 43{ 44 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || 45 (MI->getOpcode() == Mips::LDC1)) { 46 if ((MI->getOperand(1).isFI()) && // is a stack slot 47 (MI->getOperand(2).isImm()) && // the imm is zero 48 (isZeroImm(MI->getOperand(2)))) { 49 FrameIndex = MI->getOperand(1).getIndex(); 50 return MI->getOperand(0).getReg(); 51 } 52 } 53 54 return 0; 55} 56 57/// isStoreToStackSlot - If the specified machine instruction is a direct 58/// store to a stack slot, return the virtual or physical register number of 59/// the source reg along with the FrameIndex of the loaded stack slot. If 60/// not, return 0. This predicate must return 0 if the instruction has 61/// any side effects other than storing to the stack slot. 62unsigned MipsInstrInfo:: 63isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const 64{ 65 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || 66 (MI->getOpcode() == Mips::SDC1)) { 67 if ((MI->getOperand(1).isFI()) && // is a stack slot 68 (MI->getOperand(2).isImm()) && // the imm is zero 69 (isZeroImm(MI->getOperand(2)))) { 70 FrameIndex = MI->getOperand(1).getIndex(); 71 return MI->getOperand(0).getReg(); 72 } 73 } 74 return 0; 75} 76 77/// insertNoop - If data hazard condition is found insert the target nop 78/// instruction. 79void MipsInstrInfo:: 80insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const 81{ 82 DebugLoc DL; 83 BuildMI(MBB, MI, DL, get(Mips::NOP)); 84} 85 86void MipsInstrInfo:: 87copyPhysReg(MachineBasicBlock &MBB, 88 MachineBasicBlock::iterator I, DebugLoc DL, 89 unsigned DestReg, unsigned SrcReg, 90 bool KillSrc) const { 91 bool DestCPU = Mips::CPURegsRegClass.contains(DestReg); 92 bool SrcCPU = Mips::CPURegsRegClass.contains(SrcReg); 93 94 // CPU-CPU is the most common. 95 if (DestCPU && SrcCPU) { 96 BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO) 97 .addReg(SrcReg, getKillRegState(KillSrc)); 98 return; 99 } 100 101 // Copy to CPU from other registers. 102 if (DestCPU) { 103 if (Mips::CCRRegClass.contains(SrcReg)) 104 BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg) 105 .addReg(SrcReg, getKillRegState(KillSrc)); 106 else if (Mips::FGR32RegClass.contains(SrcReg)) 107 BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg) 108 .addReg(SrcReg, getKillRegState(KillSrc)); 109 else if (SrcReg == Mips::HI) 110 BuildMI(MBB, I, DL, get(Mips::MFHI), DestReg); 111 else if (SrcReg == Mips::LO) 112 BuildMI(MBB, I, DL, get(Mips::MFLO), DestReg); 113 else 114 llvm_unreachable("Copy to CPU from invalid register"); 115 return; 116 } 117 118 // Copy to other registers from CPU. 119 if (SrcCPU) { 120 if (Mips::CCRRegClass.contains(DestReg)) 121 BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg) 122 .addReg(SrcReg, getKillRegState(KillSrc)); 123 else if (Mips::FGR32RegClass.contains(DestReg)) 124 BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg) 125 .addReg(SrcReg, getKillRegState(KillSrc)); 126 else if (DestReg == Mips::HI) 127 BuildMI(MBB, I, DL, get(Mips::MTHI)) 128 .addReg(SrcReg, getKillRegState(KillSrc)); 129 else if (DestReg == Mips::LO) 130 BuildMI(MBB, I, DL, get(Mips::MTLO)) 131 .addReg(SrcReg, getKillRegState(KillSrc)); 132 else 133 llvm_unreachable("Copy from CPU to invalid register"); 134 return; 135 } 136 137 if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) { 138 BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg) 139 .addReg(SrcReg, getKillRegState(KillSrc)); 140 return; 141 } 142 143 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) { 144 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg) 145 .addReg(SrcReg, getKillRegState(KillSrc)); 146 return; 147 } 148 149 if (Mips::CCRRegClass.contains(DestReg, SrcReg)) { 150 BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg) 151 .addReg(SrcReg, getKillRegState(KillSrc)); 152 return; 153 } 154 llvm_unreachable("Cannot copy registers"); 155} 156 157void MipsInstrInfo:: 158storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 159 unsigned SrcReg, bool isKill, int FI, 160 const TargetRegisterClass *RC, 161 const TargetRegisterInfo *TRI) const { 162 DebugLoc DL; 163 if (I != MBB.end()) DL = I->getDebugLoc(); 164 165 if (RC == Mips::CPURegsRegisterClass) 166 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill)) 167 .addFrameIndex(FI).addImm(0); 168 else if (RC == Mips::FGR32RegisterClass) 169 BuildMI(MBB, I, DL, get(Mips::SWC1)).addReg(SrcReg, getKillRegState(isKill)) 170 .addFrameIndex(FI).addImm(0); 171 else if (RC == Mips::AFGR64RegisterClass) { 172 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 173 BuildMI(MBB, I, DL, get(Mips::SDC1)) 174 .addReg(SrcReg, getKillRegState(isKill)) 175 .addFrameIndex(FI).addImm(0); 176 } else { 177 const TargetRegisterInfo *TRI = 178 MBB.getParent()->getTarget().getRegisterInfo(); 179 const unsigned *SubSet = TRI->getSubRegisters(SrcReg); 180 BuildMI(MBB, I, DL, get(Mips::SWC1)) 181 .addReg(SubSet[0], getKillRegState(isKill)) 182 .addFrameIndex(FI).addImm(0); 183 BuildMI(MBB, I, DL, get(Mips::SWC1)) 184 .addReg(SubSet[1], getKillRegState(isKill)) 185 .addFrameIndex(FI).addImm(4); 186 } 187 } else 188 llvm_unreachable("Register class not handled!"); 189} 190 191void MipsInstrInfo:: 192loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 193 unsigned DestReg, int FI, 194 const TargetRegisterClass *RC, 195 const TargetRegisterInfo *TRI) const 196{ 197 DebugLoc DL; 198 if (I != MBB.end()) DL = I->getDebugLoc(); 199 200 if (RC == Mips::CPURegsRegisterClass) 201 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addFrameIndex(FI).addImm(0); 202 else if (RC == Mips::FGR32RegisterClass) 203 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addFrameIndex(FI).addImm(0); 204 else if (RC == Mips::AFGR64RegisterClass) { 205 if (!TM.getSubtarget<MipsSubtarget>().isMips1()) { 206 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addFrameIndex(FI).addImm(0); 207 } else { 208 const TargetRegisterInfo *TRI = 209 MBB.getParent()->getTarget().getRegisterInfo(); 210 const unsigned *SubSet = TRI->getSubRegisters(DestReg); 211 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0]) 212 .addFrameIndex(FI).addImm(0); 213 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[1]) 214 .addFrameIndex(FI).addImm(4); 215 } 216 } else 217 llvm_unreachable("Register class not handled!"); 218} 219 220MachineInstr* 221MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx, 222 uint64_t Offset, const MDNode *MDPtr, 223 DebugLoc DL) const { 224 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) 225 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr); 226 return &*MIB; 227} 228 229//===----------------------------------------------------------------------===// 230// Branch Analysis 231//===----------------------------------------------------------------------===// 232 233static unsigned GetAnalyzableBrOpc(unsigned Opc) { 234 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 235 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 236 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::J) ? Opc : 0; 237} 238 239/// GetOppositeBranchOpc - Return the inverse of the specified 240/// opcode, e.g. turning BEQ to BNE. 241unsigned Mips::GetOppositeBranchOpc(unsigned Opc) 242{ 243 switch (Opc) { 244 default: llvm_unreachable("Illegal opcode!"); 245 case Mips::BEQ : return Mips::BNE; 246 case Mips::BNE : return Mips::BEQ; 247 case Mips::BGTZ : return Mips::BLEZ; 248 case Mips::BGEZ : return Mips::BLTZ; 249 case Mips::BLTZ : return Mips::BGEZ; 250 case Mips::BLEZ : return Mips::BGTZ; 251 case Mips::BC1T : return Mips::BC1F; 252 case Mips::BC1F : return Mips::BC1T; 253 } 254} 255 256static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, 257 MachineBasicBlock *&BB, 258 SmallVectorImpl<MachineOperand>& Cond) { 259 assert(GetAnalyzableBrOpc(Opc) && "Not an analyzable branch"); 260 int NumOp = Inst->getNumExplicitOperands(); 261 262 // for both int and fp branches, the last explicit operand is the 263 // MBB. 264 BB = Inst->getOperand(NumOp-1).getMBB(); 265 Cond.push_back(MachineOperand::CreateImm(Opc)); 266 267 for (int i=0; i<NumOp-1; i++) 268 Cond.push_back(Inst->getOperand(i)); 269} 270 271bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 272 MachineBasicBlock *&TBB, 273 MachineBasicBlock *&FBB, 274 SmallVectorImpl<MachineOperand> &Cond, 275 bool AllowModify) const 276{ 277 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 278 279 // Skip all the debug instructions. 280 while (I != REnd && I->isDebugValue()) 281 ++I; 282 283 if (I == REnd || !isUnpredicatedTerminator(&*I)) { 284 // If this block ends with no branches (it just falls through to its succ) 285 // just return false, leaving TBB/FBB null. 286 TBB = FBB = NULL; 287 return false; 288 } 289 290 MachineInstr *LastInst = &*I; 291 unsigned LastOpc = LastInst->getOpcode(); 292 293 // Not an analyzable branch (must be an indirect jump). 294 if (!GetAnalyzableBrOpc(LastOpc)) 295 return true; 296 297 // Get the second to last instruction in the block. 298 unsigned SecondLastOpc = 0; 299 MachineInstr *SecondLastInst = NULL; 300 301 if (++I != REnd) { 302 SecondLastInst = &*I; 303 SecondLastOpc = GetAnalyzableBrOpc(SecondLastInst->getOpcode()); 304 305 // Not an analyzable branch (must be an indirect jump). 306 if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc) 307 return true; 308 } 309 310 // If there is only one terminator instruction, process it. 311 if (!SecondLastOpc) { 312 // Unconditional branch 313 if (LastOpc == Mips::J) { 314 TBB = LastInst->getOperand(0).getMBB(); 315 return false; 316 } 317 318 // Conditional branch 319 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond); 320 return false; 321 } 322 323 // If we reached here, there are two branches. 324 // If there are three terminators, we don't know what sort of block this is. 325 if (++I != REnd && isUnpredicatedTerminator(&*I)) 326 return true; 327 328 // If second to last instruction is an unconditional branch, 329 // analyze it and remove the last instruction. 330 if (SecondLastOpc == Mips::J) { 331 // Return if the last instruction cannot be removed. 332 if (!AllowModify) 333 return true; 334 335 TBB = SecondLastInst->getOperand(0).getMBB(); 336 LastInst->eraseFromParent(); 337 return false; 338 } 339 340 // Conditional branch followed by an unconditional branch. 341 // The last one must be unconditional. 342 if (LastOpc != Mips::J) 343 return true; 344 345 AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond); 346 FBB = LastInst->getOperand(0).getMBB(); 347 348 return false; 349} 350 351void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, 352 MachineBasicBlock *TBB, DebugLoc DL, 353 const SmallVectorImpl<MachineOperand>& Cond) 354 const { 355 unsigned Opc = Cond[0].getImm(); 356 const MCInstrDesc &MCID = get(Opc); 357 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); 358 359 for (unsigned i = 1; i < Cond.size(); ++i) 360 MIB.addReg(Cond[i].getReg()); 361 362 MIB.addMBB(TBB); 363} 364 365unsigned MipsInstrInfo:: 366InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 367 MachineBasicBlock *FBB, 368 const SmallVectorImpl<MachineOperand> &Cond, 369 DebugLoc DL) const { 370 // Shouldn't be a fall through. 371 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 372 373 // # of condition operands: 374 // Unconditional branches: 0 375 // Floating point branches: 1 (opc) 376 // Int BranchZero: 2 (opc, reg) 377 // Int Branch: 3 (opc, reg0, reg1) 378 assert((Cond.size() <= 3) && 379 "# of Mips branch conditions must be <= 3!"); 380 381 // Two-way Conditional branch. 382 if (FBB) { 383 BuildCondBr(MBB, TBB, DL, Cond); 384 BuildMI(&MBB, DL, get(Mips::J)).addMBB(FBB); 385 return 2; 386 } 387 388 // One way branch. 389 // Unconditional branch. 390 if (Cond.empty()) 391 BuildMI(&MBB, DL, get(Mips::J)).addMBB(TBB); 392 else // Conditional branch. 393 BuildCondBr(MBB, TBB, DL, Cond); 394 return 1; 395} 396 397unsigned MipsInstrInfo:: 398RemoveBranch(MachineBasicBlock &MBB) const 399{ 400 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); 401 MachineBasicBlock::reverse_iterator FirstBr; 402 unsigned removed; 403 404 // Skip all the debug instructions. 405 while (I != REnd && I->isDebugValue()) 406 ++I; 407 408 FirstBr = I; 409 410 // Up to 2 branches are removed. 411 // Note that indirect branches are not removed. 412 for(removed = 0; I != REnd && removed < 2; ++I, ++removed) 413 if (!GetAnalyzableBrOpc(I->getOpcode())) 414 break; 415 416 MBB.erase(I.base(), FirstBr.base()); 417 418 return removed; 419} 420 421/// ReverseBranchCondition - Return the inverse opcode of the 422/// specified Branch instruction. 423bool MipsInstrInfo:: 424ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 425{ 426 assert( (Cond.size() && Cond.size() <= 3) && 427 "Invalid Mips branch condition!"); 428 Cond[0].setImm(Mips::GetOppositeBranchOpc(Cond[0].getImm())); 429 return false; 430} 431 432/// getGlobalBaseReg - Return a virtual register initialized with the 433/// the global base register value. Output instructions required to 434/// initialize the register in the function entry block, if necessary. 435/// 436unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 437 MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>(); 438 unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg(); 439 if (GlobalBaseReg != 0) 440 return GlobalBaseReg; 441 442 // Insert the set of GlobalBaseReg into the first MBB of the function 443 MachineBasicBlock &FirstMBB = MF->front(); 444 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 445 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 446 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 447 448 GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass); 449 BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), 450 GlobalBaseReg).addReg(Mips::GP); 451 RegInfo.addLiveIn(Mips::GP); 452 453 MipsFI->setGlobalBaseReg(GlobalBaseReg); 454 return GlobalBaseReg; 455} 456