MipsInstrInfo.cpp revision a8173b934fdfdc7a3ca543a0734b7c8fa1969366 
1//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsInstrInfo.h"
15#include "MipsTargetMachine.h"
16#include "MipsMachineFunction.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "MipsGenInstrInfo.inc"
22
23using namespace llvm;
24
25MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
26  : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
27    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
28
29static bool isZeroImm(const MachineOperand &op) {
30  return op.isImm() && op.getImm() == 0;
31}
32
33/// Return true if the instruction is a register to register move and
34/// leave the source and dest operands in the passed parameters.
35bool MipsInstrInfo::
36isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
37            unsigned &SrcSubIdx, unsigned &DstSubIdx) const
38{
39  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
40
41  // addu $dst, $src, $zero || addu $dst, $zero, $src
42  // or   $dst, $src, $zero || or   $dst, $zero, $src
43  if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
44    if (MI.getOperand(1).getReg() == Mips::ZERO) {
45      DstReg = MI.getOperand(0).getReg();
46      SrcReg = MI.getOperand(2).getReg();
47      return true;
48    } else if (MI.getOperand(2).getReg() == Mips::ZERO) {
49      DstReg = MI.getOperand(0).getReg();
50      SrcReg = MI.getOperand(1).getReg();
51      return true;
52    }
53  }
54
55  // mov $fpDst, $fpSrc
56  // mfc $gpDst, $fpSrc
57  // mtc $fpDst, $gpSrc
58  if (MI.getOpcode() == Mips::FMOV_S32 ||
59      MI.getOpcode() == Mips::FMOV_D32 ||
60      MI.getOpcode() == Mips::MFC1 ||
61      MI.getOpcode() == Mips::MTC1 ||
62      MI.getOpcode() == Mips::MOVCCRToCCR) {
63    DstReg = MI.getOperand(0).getReg();
64    SrcReg = MI.getOperand(1).getReg();
65    return true;
66  }
67
68  // addiu $dst, $src, 0
69  if (MI.getOpcode() == Mips::ADDiu) {
70    if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
71      DstReg = MI.getOperand(0).getReg();
72      SrcReg = MI.getOperand(1).getReg();
73      return true;
74    }
75  }
76
77  return false;
78}
79
80/// isLoadFromStackSlot - If the specified machine instruction is a direct
81/// load from a stack slot, return the virtual or physical register number of
82/// the destination along with the FrameIndex of the loaded stack slot.  If
83/// not, return 0.  This predicate must return 0 if the instruction has
84/// any side effects other than loading from the stack slot.
85unsigned MipsInstrInfo::
86isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
87{
88  if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
89      (MI->getOpcode() == Mips::LDC1)) {
90    if ((MI->getOperand(2).isFI()) && // is a stack slot
91        (MI->getOperand(1).isImm()) &&  // the imm is zero
92        (isZeroImm(MI->getOperand(1)))) {
93      FrameIndex = MI->getOperand(2).getIndex();
94      return MI->getOperand(0).getReg();
95    }
96  }
97
98  return 0;
99}
100
101/// isStoreToStackSlot - If the specified machine instruction is a direct
102/// store to a stack slot, return the virtual or physical register number of
103/// the source reg along with the FrameIndex of the loaded stack slot.  If
104/// not, return 0.  This predicate must return 0 if the instruction has
105/// any side effects other than storing to the stack slot.
106unsigned MipsInstrInfo::
107isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
108{
109  if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
110      (MI->getOpcode() == Mips::SDC1)) {
111    if ((MI->getOperand(2).isFI()) && // is a stack slot
112        (MI->getOperand(1).isImm()) &&  // the imm is zero
113        (isZeroImm(MI->getOperand(1)))) {
114      FrameIndex = MI->getOperand(2).getIndex();
115      return MI->getOperand(0).getReg();
116    }
117  }
118  return 0;
119}
120
121/// insertNoop - If data hazard condition is found insert the target nop
122/// instruction.
123void MipsInstrInfo::
124insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
125{
126  DebugLoc DL = DebugLoc::getUnknownLoc();
127  if (MI != MBB.end()) DL = MI->getDebugLoc();
128  BuildMI(MBB, MI, DL, get(Mips::NOP));
129}
130
131bool MipsInstrInfo::
132copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
133             unsigned DestReg, unsigned SrcReg,
134             const TargetRegisterClass *DestRC,
135             const TargetRegisterClass *SrcRC) const {
136  DebugLoc DL = DebugLoc::getUnknownLoc();
137  const MachineFunction *MF = MBB.getParent();
138  const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
139
140  if (I != MBB.end()) DL = I->getDebugLoc();
141
142  if (DestRC != SrcRC) {
143
144    // Copy to/from FCR31 condition register
145    if ((DestRC == Mips::CPURegsRegisterClass) &&
146        (SrcRC == Mips::CCRRegisterClass))
147      BuildMI(MBB, I, DL, get(Mips::CFC1), DestReg).addReg(SrcReg);
148    else if ((DestRC == Mips::CCRRegisterClass) &&
149        (SrcRC == Mips::CPURegsRegisterClass))
150      BuildMI(MBB, I, DL, get(Mips::CTC1), DestReg).addReg(SrcReg);
151
152    // Moves between coprocessors and cpu
153    else if ((DestRC == Mips::CPURegsRegisterClass) &&
154        (SrcRC == Mips::FGR32RegisterClass))
155      BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
156    else if ((DestRC == Mips::FGR32RegisterClass) &&
157             (SrcRC == Mips::CPURegsRegisterClass))
158      BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
159    else if ((DestRC == Mips::AFGR64RegisterClass) &&
160             (SrcRC == Mips::CPURegsRegisterClass) &&
161             (SrcReg == Mips::ZERO)) {
162      const unsigned *AliasSet = TRI->getAliasSet(DestReg);
163      BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
164      BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
165    }
166
167    // Move from/to Hi/Lo registers
168    else if ((DestRC == Mips::HILORegisterClass) &&
169             (SrcRC == Mips::CPURegsRegisterClass)) {
170      unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
171      BuildMI(MBB, I, DL, get(Opc), DestReg);
172    } else if ((SrcRC == Mips::HILORegisterClass) &&
173               (DestRC == Mips::CPURegsRegisterClass)) {
174      unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
175      BuildMI(MBB, I, DL, get(Opc), DestReg);
176    } else
177      // Can't copy this register
178      return false;
179
180    return true;
181  }
182
183  if (DestRC == Mips::CPURegsRegisterClass)
184    BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
185      .addReg(SrcReg);
186  else if (DestRC == Mips::FGR32RegisterClass)
187    BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
188  else if (DestRC == Mips::AFGR64RegisterClass)
189    BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
190  else if (DestRC == Mips::CCRRegisterClass)
191    BuildMI(MBB, I, DL, get(Mips::MOVCCRToCCR), DestReg).addReg(SrcReg);
192  else
193    // Can't copy this register
194    return false;
195
196  return true;
197}
198
199void MipsInstrInfo::
200storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
201                    unsigned SrcReg, bool isKill, int FI,
202                    const TargetRegisterClass *RC) const {
203  unsigned Opc;
204
205  DebugLoc DL = DebugLoc::getUnknownLoc();
206  if (I != MBB.end()) DL = I->getDebugLoc();
207
208  if (RC == Mips::CPURegsRegisterClass)
209    Opc = Mips::SW;
210  else if (RC == Mips::FGR32RegisterClass)
211    Opc = Mips::SWC1;
212  else {
213    assert(RC == Mips::AFGR64RegisterClass);
214    Opc = Mips::SDC1;
215  }
216
217  BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
218          .addImm(0).addFrameIndex(FI);
219}
220
221void MipsInstrInfo::
222loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
223                     unsigned DestReg, int FI,
224                     const TargetRegisterClass *RC) const
225{
226  unsigned Opc;
227  if (RC == Mips::CPURegsRegisterClass)
228    Opc = Mips::LW;
229  else if (RC == Mips::FGR32RegisterClass)
230    Opc = Mips::LWC1;
231  else {
232    assert(RC == Mips::AFGR64RegisterClass);
233    Opc = Mips::LDC1;
234  }
235
236  DebugLoc DL = DebugLoc::getUnknownLoc();
237  if (I != MBB.end()) DL = I->getDebugLoc();
238  BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
239}
240
241MachineInstr *MipsInstrInfo::
242foldMemoryOperandImpl(MachineFunction &MF,
243                      MachineInstr* MI,
244                      const SmallVectorImpl<unsigned> &Ops, int FI) const
245{
246  if (Ops.size() != 1) return NULL;
247
248  MachineInstr *NewMI = NULL;
249
250  switch (MI->getOpcode()) {
251  case Mips::ADDu:
252    if ((MI->getOperand(0).isReg()) &&
253        (MI->getOperand(1).isReg()) &&
254        (MI->getOperand(1).getReg() == Mips::ZERO) &&
255        (MI->getOperand(2).isReg())) {
256      if (Ops[0] == 0) {    // COPY -> STORE
257        unsigned SrcReg = MI->getOperand(2).getReg();
258        bool isKill = MI->getOperand(2).isKill();
259        bool isUndef = MI->getOperand(2).isUndef();
260        NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
261          .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
262          .addImm(0).addFrameIndex(FI);
263      } else {              // COPY -> LOAD
264        unsigned DstReg = MI->getOperand(0).getReg();
265        bool isDead = MI->getOperand(0).isDead();
266        bool isUndef = MI->getOperand(0).isUndef();
267        NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
268          .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
269                  getUndefRegState(isUndef))
270          .addImm(0).addFrameIndex(FI);
271      }
272    }
273    break;
274  case Mips::FMOV_S32:
275  case Mips::FMOV_D32:
276    if ((MI->getOperand(0).isReg()) &&
277        (MI->getOperand(1).isReg())) {
278      const TargetRegisterClass
279        *RC = RI.getRegClass(MI->getOperand(0).getReg());
280      unsigned StoreOpc, LoadOpc;
281
282      if (RC == Mips::FGR32RegisterClass) {
283        LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
284      } else {
285        assert(RC == Mips::AFGR64RegisterClass);
286        LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
287      }
288
289      if (Ops[0] == 0) {    // COPY -> STORE
290        unsigned SrcReg = MI->getOperand(1).getReg();
291        bool isKill = MI->getOperand(1).isKill();
292        bool isUndef = MI->getOperand(2).isUndef();
293        NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
294          .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
295          .addImm(0).addFrameIndex(FI) ;
296      } else {              // COPY -> LOAD
297        unsigned DstReg = MI->getOperand(0).getReg();
298        bool isDead = MI->getOperand(0).isDead();
299        bool isUndef = MI->getOperand(0).isUndef();
300        NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
301          .addReg(DstReg, RegState::Define | getDeadRegState(isDead) |
302                  getUndefRegState(isUndef))
303          .addImm(0).addFrameIndex(FI);
304      }
305    }
306    break;
307  }
308
309  return NewMI;
310}
311
312//===----------------------------------------------------------------------===//
313// Branch Analysis
314//===----------------------------------------------------------------------===//
315
316/// GetCondFromBranchOpc - Return the Mips CC that matches
317/// the correspondent Branch instruction opcode.
318static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
319{
320  switch (BrOpc) {
321  default: return Mips::COND_INVALID;
322  case Mips::BEQ  : return Mips::COND_E;
323  case Mips::BNE  : return Mips::COND_NE;
324  case Mips::BGTZ : return Mips::COND_GZ;
325  case Mips::BGEZ : return Mips::COND_GEZ;
326  case Mips::BLTZ : return Mips::COND_LZ;
327  case Mips::BLEZ : return Mips::COND_LEZ;
328
329  // We dont do fp branch analysis yet!
330  case Mips::BC1T :
331  case Mips::BC1F : return Mips::COND_INVALID;
332  }
333}
334
335/// GetCondBranchFromCond - Return the Branch instruction
336/// opcode that matches the cc.
337unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
338{
339  switch (CC) {
340  default: llvm_unreachable("Illegal condition code!");
341  case Mips::COND_E   : return Mips::BEQ;
342  case Mips::COND_NE  : return Mips::BNE;
343  case Mips::COND_GZ  : return Mips::BGTZ;
344  case Mips::COND_GEZ : return Mips::BGEZ;
345  case Mips::COND_LZ  : return Mips::BLTZ;
346  case Mips::COND_LEZ : return Mips::BLEZ;
347
348  case Mips::FCOND_F:
349  case Mips::FCOND_UN:
350  case Mips::FCOND_EQ:
351  case Mips::FCOND_UEQ:
352  case Mips::FCOND_OLT:
353  case Mips::FCOND_ULT:
354  case Mips::FCOND_OLE:
355  case Mips::FCOND_ULE:
356  case Mips::FCOND_SF:
357  case Mips::FCOND_NGLE:
358  case Mips::FCOND_SEQ:
359  case Mips::FCOND_NGL:
360  case Mips::FCOND_LT:
361  case Mips::FCOND_NGE:
362  case Mips::FCOND_LE:
363  case Mips::FCOND_NGT: return Mips::BC1T;
364
365  case Mips::FCOND_T:
366  case Mips::FCOND_OR:
367  case Mips::FCOND_NEQ:
368  case Mips::FCOND_OGL:
369  case Mips::FCOND_UGE:
370  case Mips::FCOND_OGE:
371  case Mips::FCOND_UGT:
372  case Mips::FCOND_OGT:
373  case Mips::FCOND_ST:
374  case Mips::FCOND_GLE:
375  case Mips::FCOND_SNE:
376  case Mips::FCOND_GL:
377  case Mips::FCOND_NLT:
378  case Mips::FCOND_GE:
379  case Mips::FCOND_NLE:
380  case Mips::FCOND_GT: return Mips::BC1F;
381  }
382}
383
384/// GetOppositeBranchCondition - Return the inverse of the specified
385/// condition, e.g. turning COND_E to COND_NE.
386Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
387{
388  switch (CC) {
389  default: llvm_unreachable("Illegal condition code!");
390  case Mips::COND_E   : return Mips::COND_NE;
391  case Mips::COND_NE  : return Mips::COND_E;
392  case Mips::COND_GZ  : return Mips::COND_LEZ;
393  case Mips::COND_GEZ : return Mips::COND_LZ;
394  case Mips::COND_LZ  : return Mips::COND_GEZ;
395  case Mips::COND_LEZ : return Mips::COND_GZ;
396  case Mips::FCOND_F  : return Mips::FCOND_T;
397  case Mips::FCOND_UN : return Mips::FCOND_OR;
398  case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
399  case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
400  case Mips::FCOND_OLT: return Mips::FCOND_UGE;
401  case Mips::FCOND_ULT: return Mips::FCOND_OGE;
402  case Mips::FCOND_OLE: return Mips::FCOND_UGT;
403  case Mips::FCOND_ULE: return Mips::FCOND_OGT;
404  case Mips::FCOND_SF:  return Mips::FCOND_ST;
405  case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
406  case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
407  case Mips::FCOND_NGL: return Mips::FCOND_GL;
408  case Mips::FCOND_LT:  return Mips::FCOND_NLT;
409  case Mips::FCOND_NGE: return Mips::FCOND_GE;
410  case Mips::FCOND_LE:  return Mips::FCOND_NLE;
411  case Mips::FCOND_NGT: return Mips::FCOND_GT;
412  }
413}
414
415bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
416                                  MachineBasicBlock *&TBB,
417                                  MachineBasicBlock *&FBB,
418                                  SmallVectorImpl<MachineOperand> &Cond,
419                                  bool AllowModify) const
420{
421  // If the block has no terminators, it just falls into the block after it.
422  MachineBasicBlock::iterator I = MBB.end();
423  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
424    return false;
425
426  // Get the last instruction in the block.
427  MachineInstr *LastInst = I;
428
429  // If there is only one terminator instruction, process it.
430  unsigned LastOpc = LastInst->getOpcode();
431  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
432    if (!LastInst->getDesc().isBranch())
433      return true;
434
435    // Unconditional branch
436    if (LastOpc == Mips::J) {
437      TBB = LastInst->getOperand(0).getMBB();
438      return false;
439    }
440
441    Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
442    if (BranchCode == Mips::COND_INVALID)
443      return true;  // Can't handle indirect branch.
444
445    // Conditional branch
446    // Block ends with fall-through condbranch.
447    if (LastOpc != Mips::COND_INVALID) {
448      int LastNumOp = LastInst->getNumOperands();
449
450      TBB = LastInst->getOperand(LastNumOp-1).getMBB();
451      Cond.push_back(MachineOperand::CreateImm(BranchCode));
452
453      for (int i=0; i<LastNumOp-1; i++) {
454        Cond.push_back(LastInst->getOperand(i));
455      }
456
457      return false;
458    }
459  }
460
461  // Get the instruction before it if it is a terminator.
462  MachineInstr *SecondLastInst = I;
463
464  // If there are three terminators, we don't know what sort of block this is.
465  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
466    return true;
467
468  // If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
469  unsigned SecondLastOpc    = SecondLastInst->getOpcode();
470  Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
471
472  if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
473    int SecondNumOp = SecondLastInst->getNumOperands();
474
475    TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
476    Cond.push_back(MachineOperand::CreateImm(BranchCode));
477
478    for (int i=0; i<SecondNumOp-1; i++) {
479      Cond.push_back(SecondLastInst->getOperand(i));
480    }
481
482    FBB = LastInst->getOperand(0).getMBB();
483    return false;
484  }
485
486  // If the block ends with two unconditional branches, handle it. The last
487  // one is not executed, so remove it.
488  if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
489    TBB = SecondLastInst->getOperand(0).getMBB();
490    I = LastInst;
491    if (AllowModify)
492      I->eraseFromParent();
493    return false;
494  }
495
496  // Otherwise, can't handle this.
497  return true;
498}
499
500unsigned MipsInstrInfo::
501InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
502             MachineBasicBlock *FBB,
503             const SmallVectorImpl<MachineOperand> &Cond) const {
504  // FIXME this should probably have a DebugLoc argument
505  DebugLoc dl = DebugLoc::getUnknownLoc();
506  // Shouldn't be a fall through.
507  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
508  assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
509         "Mips branch conditions can have two|three components!");
510
511  if (FBB == 0) { // One way branch.
512    if (Cond.empty()) {
513      // Unconditional branch?
514      BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
515    } else {
516      // Conditional branch.
517      unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
518      const TargetInstrDesc &TID = get(Opc);
519
520      if (TID.getNumOperands() == 3)
521        BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
522                          .addReg(Cond[2].getReg())
523                          .addMBB(TBB);
524      else
525        BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
526                          .addMBB(TBB);
527
528    }
529    return 1;
530  }
531
532  // Two-way Conditional branch.
533  unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
534  const TargetInstrDesc &TID = get(Opc);
535
536  if (TID.getNumOperands() == 3)
537    BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
538                      .addMBB(TBB);
539  else
540    BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
541
542  BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
543  return 2;
544}
545
546unsigned MipsInstrInfo::
547RemoveBranch(MachineBasicBlock &MBB) const
548{
549  MachineBasicBlock::iterator I = MBB.end();
550  if (I == MBB.begin()) return 0;
551  --I;
552  if (I->getOpcode() != Mips::J &&
553      GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
554    return 0;
555
556  // Remove the branch.
557  I->eraseFromParent();
558
559  I = MBB.end();
560
561  if (I == MBB.begin()) return 1;
562  --I;
563  if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
564    return 1;
565
566  // Remove the branch.
567  I->eraseFromParent();
568  return 2;
569}
570
571/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
572/// fall-through into its successor block.
573bool MipsInstrInfo::
574BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
575{
576  if (MBB.empty()) return false;
577
578  switch (MBB.back().getOpcode()) {
579  case Mips::RET:     // Return.
580  case Mips::JR:      // Indirect branch.
581  case Mips::J:       // Uncond branch.
582    return true;
583  default: return false;
584  }
585}
586
587/// ReverseBranchCondition - Return the inverse opcode of the
588/// specified Branch instruction.
589bool MipsInstrInfo::
590ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
591{
592  assert( (Cond.size() == 3 || Cond.size() == 2) &&
593          "Invalid Mips branch condition!");
594  Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
595  return false;
596}
597
598/// getGlobalBaseReg - Return a virtual register initialized with the
599/// the global base register value. Output instructions required to
600/// initialize the register in the function entry block, if necessary.
601///
602unsigned MipsInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
603  MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>();
604  unsigned GlobalBaseReg = MipsFI->getGlobalBaseReg();
605  if (GlobalBaseReg != 0)
606    return GlobalBaseReg;
607
608  // Insert the set of GlobalBaseReg into the first MBB of the function
609  MachineBasicBlock &FirstMBB = MF->front();
610  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
611  MachineRegisterInfo &RegInfo = MF->getRegInfo();
612  const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
613
614  GlobalBaseReg = RegInfo.createVirtualRegister(Mips::CPURegsRegisterClass);
615  bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Mips::GP,
616                              Mips::CPURegsRegisterClass,
617                              Mips::CPURegsRegisterClass);
618  assert(Ok && "Couldn't assign to global base register!");
619  Ok = Ok; // Silence warning when assertions are turned off.
620  RegInfo.addLiveIn(Mips::GP);
621
622  MipsFI->setGlobalBaseReg(GlobalBaseReg);
623  return GlobalBaseReg;
624}
625