| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 324 EVT RegVT = local
329 unsigned RegBytes = RegVT.getSizeInBits() / 8;
333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); local
452 unsigned RegBytes = RegVT.getSizeInBits() / 8;
456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chai
[all...] |
| H A D | LegalizeVectorOps.cpp | 405 EVT RegVT = Value.getValueType(); local
406 EVT RegSclVT = RegVT.getScalarType();
|
| H A D | SelectionDAGBuilder.h | 268 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
274 EVT RegVT; member in struct:llvm::SelectionDAGBuilder::BitTestBlock
|
| H A D | LegalizeIntegerTypes.cpp | 698 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); local
700 // The argument is passed as NumRegs registers of type RegVT.
704 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
720 DAG.getConstant(i * RegVT.getSizeInBits(),
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| H A D | SelectionDAGBuilder.cpp | 1739 B.RegVT = VT;
1774 EVT VT = BB.RegVT;
5836 EVT RegVT = *PhysReg.second->vt_begin(); local
5837 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5839 RegVT, OpInfo.CallOperand);
5840 OpInfo.ConstraintVT = RegVT;
5841 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5846 RegVT = EVT::getIntegerVT(Context,
5849 RegVT, OpInfo.CallOperand);
5850 OpInfo.ConstraintVT = RegVT;
5857 EVT RegVT; local
6215 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); local
6752 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); local
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeISelLowering.cpp | 728 MVT RegVT = VA.getLocVT(); local
736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
742 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
903 MVT RegVT = VA.getLocVT(); local
907 if (RegVT == MVT::i32)
909 else if (RegVT == MVT::f32)
912 llvm_unreachable("RegVT not supported by LowerFormalArguments");
917 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
930 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValu
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 327 EVT RegVT = VA.getLocVT(); local
328 switch (RegVT.getSimpleVT().SimpleTy) {
333 << RegVT.getSimpleVT().SimpleTy << "\n";
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
346 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 845 EVT RegVT = VA.getLocVT(); local
846 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
847 RegVT == MVT::i32 || RegVT == MVT::f32) {
851 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
852 } else if (RegVT == MVT::i64) {
856 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1119 EVT RegVT = VA.getLocVT(); local
1120 switch (RegVT.getSimpleVT().SimpleTy) {
1125 << RegVT.getSimpleVT().SimpleTy << "\n";
1132 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
|
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3032 EVT RegVT = VA.getLocVT(); local
3036 if (RegVT == MVT::i32)
3038 else if (RegVT == MVT::i64)
3040 else if (RegVT == MVT::f32)
3042 else if (RegVT == MVT::f64)
3045 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
3050 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3062 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
3068 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3069 (RegVT
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 1828 EVT RegVT = VA.getLocVT(); local
1842 if (RegVT == MVT::v2f64) {
2619 EVT RegVT = VA.getLocVT(); local
2650 if (RegVT == MVT::f32)
2652 else if (RegVT == MVT::f64)
2654 else if (RegVT == MVT::v2f64)
2656 else if (RegVT == MVT::i32)
2661 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2665 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2678 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValu
[all...] |
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 1892 EVT RegVT = VA.getLocVT(); local
1894 if (RegVT == MVT::i32)
1896 else if (Is64Bit && RegVT == MVT::i64)
1898 else if (RegVT == MVT::f32)
1900 else if (RegVT == MVT::f64)
1902 else if (RegVT.is256BitVector())
1904 else if (RegVT.is128BitVector())
1906 else if (RegVT == MVT::x86mmx)
1912 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1918 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValu
2266 EVT RegVT = VA.getLocVT(); local
15074 EVT RegVT = Ld->getValueType(0); local
[all...] |