Searched defs:seg_reg (Results 1 - 4 of 4) sorted by relevance

/external/qemu/
H A Dcpu-exec.c755 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) argument
763 cpu_x86_load_seg_cache(env, seg_reg, selector,
766 helper_load_seg(seg_reg, selector);
/external/qemu/target-i386/
H A Dop_helper.c222 static void tss_load_seg(int seg_reg, int selector) argument
235 if (seg_reg == R_CS) {
243 } else if (seg_reg == R_SS) {
261 cpu_x86_load_seg_cache(env, seg_reg, selector,
266 if (seg_reg == R_SS || seg_reg == R_CS)
2116 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
2117 void helper_load_seg(int seg_reg, int selector) argument
2129 if (seg_reg == R_SS
2135 cpu_x86_load_seg_cache(env, seg_reg, selecto
2554 validate_seg(int seg_reg, int cpl) argument
4925 svm_load_seg_cache(target_phys_addr_t addr, CPUState *env, int seg_reg) argument
[all...]
H A Dtranslate.c2370 static inline void gen_op_movl_T0_seg(int seg_reg) argument
2373 offsetof(CPUX86State,segs[seg_reg].selector));
2376 static inline void gen_op_movl_seg_T0_vm(int seg_reg) argument
2380 offsetof(CPUX86State,segs[seg_reg].selector));
2383 offsetof(CPUX86State,segs[seg_reg].base));
2386 /* move T0 to seg_reg and compute if the CPU state may change. Never
2387 call this function with seg_reg == R_CS */
2388 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip) argument
2396 gen_helper_load_seg(tcg_const_i32(seg_reg), cpu_tmp2_i32);
2401 if (seg_reg
[all...]
H A Dcpu.h716 int seg_reg, unsigned int selector,
724 sc = &env->segs[seg_reg];
732 if (seg_reg == R_CS) {
790 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
715 cpu_x86_load_seg_cache(CPUX86State *env, int seg_reg, unsigned int selector, target_ulong base, unsigned int limit, unsigned int flags) argument

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