Searched refs:regs (Results 151 - 175 of 214) sorted by relevance

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/external/valgrind/main/coregrind/m_gdbserver/
H A Dvalgrind-low-ppc64.c39 struct reg regs[] = { variable in typeref:struct:reg
149 #define num_regs (sizeof (regs) / sizeof (regs[0]))
187 // numbers here have to match the order of regs above
324 regs,
337 set_register_cache (regs, num_regs);
/external/qemu/tcg/arm/
H A Dtcg-target.c167 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
173 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
177 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
178 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
183 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
187 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
194 tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
198 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
199 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
204 tcg_regset_set32(ct->u.regs,
[all...]
/external/strace/
H A Dsignal.c1265 struct pt_regs regs; local
1271 if (ptrace(PTRACE_GETREGS, tcp->pid, NULL, (void *)&regs) == -1)
1274 if (umove(tcp, regs.ARM_sp, &sc) < 0)
1438 struct pt_regs regs;
1441 if(ptrace(PTRACE_GETREGS, tcp->pid, (char *)&regs, 0) < 0) {
1447 i1 = regs.u_regs[U_REG_O1];
1492 struct pt_regs regs;
1495 if(ptrace(PTRACE_GETREGS, tcp->pid, (char *)&regs, 0) < 0) {
1501 sp = regs.regs[2
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/external/qemu/
H A Dkqemu.c520 env->regs[R_ECX] = kenv->next_eip;
521 env->regs[11] = env->eflags;
544 env->regs[R_ECX] = (uint32_t)kenv->next_eip;
708 kenv->regs[i] = env->regs[i];
778 env->regs[i] = kenv->regs[i];
H A Dcpu-exec.c539 && ((IS_M(env) && env->regs[15] < 0xfffffff0)
967 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
977 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
978 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1089 uint32_t *regs = (uint32_t *)(info + 1); local
1090 void *sigmask = (regs + 20);
1092 unsigned long pc = regs[1];
H A Dgdbstub.c516 GET_REGL(env->regs[gpr_map[n]]);
545 /* 8...15 x87 regs. */
554 /* 24+ xmm regs. */
565 env->regs[gpr_map[i]] = ldtul_p(mem_buf);
604 /* 8...15 x87 regs. */
617 /* 24+ xmm regs. */
629 regs and PC, MSR, CR, and so forth. We hack round this by giving the
630 FP regs zero size when talking to a newer gdb. */
860 the FPA registers appear in between core integer regs and the CPSR.
861 We hack round this by giving the FPA regs zer
[all...]
/external/quake/quake/src/WinQuake/
H A Dvid_dos.cpp65 extern regs_t regs;
313 regs.h.ah = 0;
314 regs.h.al = 0x3;
/external/kernel-headers/original/linux/
H A Drtc.h211 irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
H A Dserio.h78 irqreturn_t serio_interrupt(struct serio *serio, unsigned char data, unsigned int flags, struct pt_regs *regs);
H A Dcompat.h187 compat_uptr_t __user *envp, struct pt_regs * regs);
H A Dinterrupt.h78 extern irqreturn_t no_action(int cpl, void *dev_id, struct pt_regs *regs);
H A Dkernel.h139 extern void dump_thread(struct pt_regs *regs, struct user *dump);
/external/linux-tools-perf/
H A DAndroid.mk93 arch/arm/util/dwarf-regs.c
241 arch/arm/util/dwarf-regs.c
/external/oprofile/module/ia64/
H A Dop_syscalls.c158 my_sys_execve (char * filename, char **argv, char **envp, struct pt_regs * regs) argument
168 error = do_execve(filename, argv, envp, regs);
/external/oprofile/module/x86/
H A Dop_nmi.c46 asmlinkage void op_do_nmi(struct pt_regs * regs) argument
51 model->check_ctrs(cpu, msrs, regs);
H A Dop_model_p4.c625 struct pt_regs * const regs)
659 op_do_profile(cpu, instruction_pointer(regs), IRQ_ENABLED(regs), i);
623 p4_check_ctrs(unsigned int const cpu, struct op_msrs const * const msrs, struct pt_regs * const regs) argument
/external/v8/src/mips/
H A Dmacro-assembler-mips.h609 void MultiPush(RegList regs);
610 void MultiPushReversed(RegList regs);
612 void MultiPushFPU(RegList regs);
613 void MultiPushReversedFPU(RegList regs);
656 // registers specified in regs. Pop order is the opposite as in MultiPush.
657 void MultiPop(RegList regs);
658 void MultiPopReversed(RegList regs);
660 void MultiPopFPU(RegList regs);
661 void MultiPopReversedFPU(RegList regs);
/external/qemu/tcg/
H A Dtcg.c1032 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1084 tcg_regset_clear(def->args_ct[i].u.regs);
1625 reg = tcg_reg_alloc(s, arg_ct->u.regs, s->reserved_regs);
1635 reg = tcg_reg_alloc(s, arg_ct->u.regs, s->reserved_regs);
1688 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1702 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1726 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1732 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1785 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1788 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_reg
[all...]
/external/qemu/target-i386/
H A Dtranslate.c279 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
281 tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
285 tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
289 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
292 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
296 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));
301 tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
321 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
325 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
328 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[re
[all...]
H A Dcpu.h568 target_ulong regs[CPU_NB_REGS]; member in struct:CPUX86State
895 env->regs[R_ESP] = newsp;
896 env->regs[R_EAX] = 0;
H A Dmachine.c36 qemu_put_betls(f, &env->regs[i]);
199 qemu_get_betls(f, &env->regs[i]);
/external/qemu/tcg/ppc64/
H A Dtcg-target.c227 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
231 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
235 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
236 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
238 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
243 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
244 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
246 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
247 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
/external/valgrind/main/coregrind/
H A Dm_signals.c320 struct pt_regs *regs;
323 The regs pointer of that struct ends up at the same offset as the
326 regs are followed in memory by the floating point regs on 2.4.20.
332 There is another subtlety: 2.4.20 doesn't save the vector regs when
333 delivering a signal, and 2.6.x only saves the vector regs if the
335 the vector regs, it sets the MSR_VEC bit in
469 # define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.regs.psw.addr)
470 # define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.regs.gprs[15])
471 # define VG_UCONTEXT_FRAME_PTR(uc) ((uc)->uc_mcontext.regs
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/external/valgrind/main/include/vki/
H A Dvki-arm-linux.h807 * normal regs, with special meaning for the segment descriptors..
840 struct vki_vm86_regs regs; member in struct:vki_vm86_struct
858 struct vki_vm86_regs regs; member in struct:vki_vm86plus_struct
H A Dvki-x86-linux.h817 * normal regs, with special meaning for the segment descriptors..
850 struct vki_vm86_regs regs; member in struct:vki_vm86_struct
868 struct vki_vm86_regs regs; member in struct:vki_vm86plus_struct

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