Searched refs:Orders (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp704 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
722 Orders.push_back(std::make_pair(DVOrder, DbgMI));
736 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
742 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
749 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
753 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
754 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
802 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
843 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
850 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
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/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h231 std::vector<SmallVector<Record*, 16> > Orders; member in class:llvm::CodeGenRegisterClass
338 return Orders[No];
342 unsigned getNumOrders() const { return Orders.size(); }
H A DCodeGenRegisters.cpp711 Orders.resize(1 + AltOrders->size());
715 Orders[0].push_back((*Elements)[i]);
725 Orders[1 + i].append(Order.begin(), Order.end());
784 Orders.resize(Super.Orders.size());
785 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
786 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
787 if (contains(RegBank.getReg(Super.Orders[i][j])))
788 Orders[i].push_back(Super.Orders[
[all...]
/external/clang/lib/CodeGen/
H A DCGBuiltin.cpp1090 llvm::AtomicOrdering Orders[5] = { local
1104 Ptr, NewVal, Orders[i]);
1158 llvm::AtomicOrdering Orders[3] = { local
1169 Store->setOrdering(Orders[i]);

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