Searched refs:R_ECX (Results 1 - 10 of 10) sorted by relevance
| /external/qemu/target-i386/ |
| H A D | exec.h | 38 #define ECX (env->regs[R_ECX])
291 ECX = env->regs[R_ECX];
319 env->regs[R_ECX] = ECX;
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| H A D | helper.c | 682 env->regs[R_ECX],
717 (uint32_t)env->regs[R_ECX],
1813 kvm_arch_get_supported_cpuid(env, 1, R_ECX),
1819 kvm_arch_get_supported_cpuid(env, 0x80000001, R_ECX),
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| H A D | kvm.c | 95 case R_ECX:
343 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
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| H A D | cpu.h | 52 #define R_ECX 1 macro
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| H A D | hax-all.c | 840 hax_getput_reg(®s._rcx, &env->regs[R_ECX], set);
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| H A D | ops_sse.h | 1930 env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
1932 env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
1962 env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
1964 env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
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| H A D | translate.c | 706 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
713 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
1242 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1260 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
5414 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
6770 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6781 gen_op_add_reg_im(s->aflag, R_ECX, -1);
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| /external/qemu/ |
| H A D | kqemu.c | 520 env->regs[R_ECX] = kenv->next_eip;
544 env->regs[R_ECX] = (uint32_t)kenv->next_eip;
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| H A D | gdbstub.c | 504 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
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| /external/valgrind/main/VEX/priv/ |
| H A D | guest_x86_toIR.c | 295 #define R_ECX 1 macro
464 case R_ECX: return OFFB_ECX;
478 case R_ECX: return 1+ OFFB_ECX;
3263 assign( tc, getIReg(4,R_ECX) );
3269 putIReg(4, R_ECX, binop(Iop_Sub32, mkexpr(tc), mkU32(1)) );
12734 binop(Iop_CmpEQ16, getIReg(2,R_ECX), mkU16(0)),
13230 binop(Iop_CmpEQ32, getIReg(4,R_ECX), mkU32(0)),
13252 putIReg(4, R_ECX, binop(Iop_Sub32, getIReg(4,R_ECX), mkU32(1)));
13254 count = getIReg(4,R_ECX);
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