Searched refs:SU (Results 1 - 25 of 37) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
H A DResourcePriorityQueue.h88 void addNode(const SUnit *SU) { argument
92 void updateNode(const SUnit *SU) {} argument
108 /// Single cost function reflecting benefit of scheduling SU
110 signed SUSchedulingCost (SUnit *SU);
114 void initNumRegDefsLeft(SUnit *SU);
115 void updateNumRegDefsLeft(SUnit *SU);
116 signed regPressureDelta(SUnit *SU, bool RawPressure = false);
117 signed rawRegPressureDelta (SUnit *SU, unsigned RCId);
125 virtual void remove(SUnit *SU);
131 bool isResourceAvailable(SUnit *SU);
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H A DLatencyPriorityQueue.h57 void addNode(const SUnit *SU) { argument
61 void updateNode(const SUnit *SU) { argument
84 virtual void remove(SUnit *SU);
95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
96 SUnit *getSingleUnscheduledPred(SUnit *SU);
H A DScheduleDAGInstrs.h102 SUnit *SU; member in struct:llvm::VReg2SUnit
104 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
114 SUnit *SU; member in struct:llvm::PhysRegSUOper
117 PhysRegSUOper(SUnit *su, int op): SU(su), OpIdx(op) {}
298 virtual void computeLatency(SUnit *SU);
311 virtual void dumpNode(const SUnit *SU) const;
314 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
321 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx);
322 void addPhysRegDeps(SUnit *SU, unsigned OperIdx);
323 void addVRegDefDeps(SUnit *SU, unsigne
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H A DScoreboardHazardRecognizer.h116 // Stalls provides an cycle offset at which SU will be scheduled. It will be
118 virtual HazardType getHazardType(SUnit *SU, int Stalls);
120 virtual void EmitInstruction(SUnit *SU);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument
73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument
111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
146 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument
148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
156 static unsigned numberCtrlPredInSU(SUnit *SU) { argument
174 SUnit *SU = &(*SUnits)[i]; local
216 getSingleUnscheduledPred(SUnit *SU) argument
232 push(SUnit *SU) argument
247 isResourceAvailable(SUnit *SU) argument
290 reserveResources(SUnit *SU) argument
327 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument
361 regPressureDelta(SUnit *SU, bool RawPressure) argument
403 SUSchedulingCost(SUnit *SU) argument
473 scheduledNode(SUnit *SU) argument
549 initNumRegDefsLeft(SUnit *SU) argument
581 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument
636 remove(SUnit *SU) argument
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H A DScheduleDAGRRList.cpp177 /// IsReachable - Checks if SU is reachable from TargetSU.
178 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
179 return Topo.IsReachable(SU, TargetSU);
182 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
184 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
185 return Topo.WillCreateCycle(SU, TargetSU);
188 /// AddPred - adds a predecessor edge to SUnit SU.
191 void AddPred(SUnit *SU, const SDep &D) { argument
192 Topo.AddPred(SU, D.getSUnit());
193 SU
199 RemovePred(SUnit *SU, const SDep &D) argument
205 isReady(SUnit *SU) argument
345 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
505 ReleasePredecessors(SUnit *SU) argument
602 AdvancePastStalls(SUnit *SU) argument
644 EmitNode(SUnit *SU) argument
686 ScheduleNodeBottomUp(SUnit *SU) argument
783 UnscheduleNodeBottomUp(SUnit *SU) argument
870 SUnit *SU = *I; local
880 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
905 isOperandOf(const SUnit *SU, SDNode *N) argument
916 CopyAndMoveSuccessors(SUnit *SU) argument
1113 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument
1182 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument
1204 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs) argument
1232 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument
1470 SUnit *SU = PickNodeToScheduleBottomUp(); local
1674 remove(SUnit *SU) argument
1767 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); local
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H A DScheduleDAGVLIW.cpp86 void releaseSucc(SUnit *SU, const SDep &D);
87 void releaseSuccessors(SUnit *SU);
88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument
128 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
137 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument
139 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
144 releaseSucc(SU, *I);
151 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument
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H A DScheduleDAGFast.cpp80 /// AddPred - adds a predecessor edge to SUnit SU.
82 void AddPred(SUnit *SU, const SDep &D) { argument
83 SU->addPred(D);
86 /// RemovePred - removes a predecessor edge from SUnit SU.
88 void RemovePred(SUnit *SU, const SDep &D) { argument
89 SU->removePred(D);
93 void ReleasePred(SUnit *SU, SDep *PredEdge);
94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
134 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument
155 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument
177 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument
207 CopyAndMoveSuccessors(SUnit *SU) argument
380 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument
438 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument
459 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument
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H A DScheduleDAGSDNodes.cpp78 SUnit *SU = &SUnits.back(); local
83 SU->SchedulingPref = Sched::None;
85 SU->SchedulingPref = TLI.getSchedulingPreference(N);
86 return SU;
90 SUnit *SU = newSUnit(Old->getNode()); local
91 SU->OrigNode = Old->OrigNode;
92 SU->Latency = Old->Latency;
93 SU->isVRegCycle = Old->isVRegCycle;
94 SU->isCall = Old->isCall;
95 SU
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H A DScheduleDAGSDNodes.h92 void InitVRegCycleFlag(SUnit *SU);
96 void InitNumRegDefsLeft(SUnit *SU);
100 virtual void computeLatency(SUnit *SU);
119 virtual void dumpNode(const SUnit *SU) const;
123 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
139 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
173 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
/external/llvm/lib/Target/CellSPU/
H A DSPUHazardRecognizers.h29 virtual HazardType getHazardType(SUnit *SU, int Stalls);
30 virtual void EmitInstruction(SUnit *SU);
H A DSPUHazardRecognizers.cpp38 SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls) argument
46 const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
123 void SPUHazardRecognizer::EmitInstruction(SUnit *SU) argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp64 void VLIWMachineScheduler::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
80 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
81 void VLIWMachineScheduler::releaseSuccessors(SUnit *SU) { argument
82 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
84 releaseSucc(SU, &*I);
92 void VLIWMachineScheduler::releasePred(SUnit *SU, SDep *PredEdge) { argument
108 /// releasePredecessors - Call releasePred on each of SU's predecessors.
109 void VLIWMachineScheduler::releasePredecessors(SUnit *SU) { argument
110 for (SUnit::pred_iterator I = SU
225 isResourceAvailable(SUnit *SU) argument
265 reserveResources(SUnit *SU) argument
480 releaseTopNode(SUnit *SU) argument
497 releaseBottomNode(SUnit *SU) argument
529 checkHazard(SUnit *SU) argument
539 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
580 bumpNode(SUnit *SU) argument
618 SUnit *SU = *(Pending.begin()+i); local
638 removeReady(SUnit *SU) argument
666 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureElement P) argument
681 getSingleUnscheduledPred(SUnit *SU) argument
699 getSingleUnscheduledSucc(SUnit *SU) argument
726 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument
901 SUnit *SU; local
943 schedNode(SUnit *SU, bool IsTopNode) argument
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H A DHexagonMachineScheduler.h61 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
65 virtual void releaseTopNode(SUnit *SU) = 0;
68 virtual void releaseBottomNode(SUnit *SU) = 0;
91 // SU is in this queue if it's NodeQueueID is a superset of this ID.
92 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
104 iterator find(SUnit *SU) { argument
105 return std::find(Queue.begin(), Queue.end(), SU);
108 void push(SUnit *SU) { argument
109 Queue.push_back(SU);
320 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate
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/external/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp54 /// of SU, return it, otherwise return null.
55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument
57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
72 void LatencyPriorityQueue::push(SUnit *SU) { argument
76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
83 Queue.push_back(SU);
91 scheduledNode(SUnit *SU) argument
104 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument
133 remove(SUnit *SU) argument
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H A DMachineScheduler.cpp309 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
313 virtual void releaseTopNode(SUnit *SU) = 0;
316 virtual void releaseBottomNode(SUnit *SU) = 0;
426 void releaseSucc(SUnit *SU, SDep *SuccEdge);
427 void releaseSuccessors(SUnit *SU);
428 void releasePred(SUnit *SU, SDep *PredEdge);
429 void releasePredecessors(SUnit *SU);
439 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { argument
455 /// releaseSuccessors - Call releaseSucc on each of SU's successors.
456 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { argument
467 releasePred(SUnit *SU, SDep *PredEdge) argument
484 releasePredecessors(SUnit *SU) argument
752 find(SUnit *SU) argument
756 push(SUnit *SU) argument
785 SUnit *SU; member in struct:__anon9279::ConvergingScheduler::SchedCandidate
903 releaseTopNode(SUnit *SU) argument
920 releaseBottomNode(SUnit *SU) argument
952 checkHazard(SUnit *SU) argument
962 releaseNode(SUnit *SU, unsigned ReadyCycle) argument
1003 bumpNode(SUnit *SU) argument
1032 SUnit *SU = *(Pending.begin()+i); local
1052 removeReady(SUnit *SU) argument
1080 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureElement P) argument
1268 SUnit *SU; local
1311 schedNode(SUnit *SU, bool IsTopNode) argument
1377 SUnit *SU; local
1399 schedNode(SUnit *SU, bool IsTopNode) argument
1401 releaseTopNode(SUnit *SU) argument
1404 releaseBottomNode(SUnit *SU) argument
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H A DScheduleDAGInstrs.cpp191 /// the exit SU to the register defs and use list. This is because we want to
233 /// MO is an operand of SU's instruction that defines a physical register. Add
234 /// data dependencies from SU to any uses of the physical register.
235 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
236 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
242 unsigned DataLatency = SU->Latency;
250 SUnit *UseSU = UseList[i].SU;
251 if (UseSU == SU)
275 SDep dep(SU, SDep::Data, LDataLatency, *Alias);
278 TII->computeOperandLatency(InstrItins, SU
297 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
418 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
455 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
656 adjustChainDeps(AliasAnalysis *AA, const MachineFrameInfo *MFI, SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList, unsigned LatencyToLoad) argument
728 SUnit *SU = newSUnit(MI); local
806 SUnit *SU = MISUnitMap[MI]; local
999 computeLatency(SUnit *SU) argument
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H A DScheduleDAG.cpp167 SUnit *SU = WorkList.pop_back_val();
168 SU->isDepthCurrent = false;
169 for (SUnit::const_succ_iterator I = SU->Succs.begin(),
170 E = SU->Succs.end(); I != E; ++I) {
183 SUnit *SU = WorkList.pop_back_val();
184 SU->isHeightCurrent = false;
185 for (SUnit::const_pred_iterator I = SU->Preds.begin(),
186 E = SU->Preds.end(); I != E; ++I) {
286 dbgs() << "SU(" << NodeNum << "): ";
311 dbgs() << "SU(" <<
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H A DScoreboardHazardRecognizer.cpp118 ScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
165 DEBUG(dbgs() << "SU(" << SU->NodeNum << "): ");
166 DEBUG(DAG->dumpNode(SU));
178 void ScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
H A DScheduleDAGPrinter.cpp75 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU, argument
77 return G->getGraphNodeLabel(SU);
/external/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
38 MachineInstr *MI = SU->getInstr();
70 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
79 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument
80 MachineInstr *MI = SU->getInstr();
86 ScoreboardHazardRecognizer::EmitInstruction(SU);
H A DARMHazardRecognizer.h47 virtual HazardType getHazardType(SUnit *SU, int Stalls);
49 virtual void EmitInstruction(SUnit *SU);
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h33 virtual HazardType getHazardType(SUnit *SU, int Stalls);
34 virtual void EmitInstruction(SUnit *SU);
68 virtual HazardType getHazardType(SUnit *SU, int Stalls);
69 virtual void EmitInstruction(SUnit *SU);
H A DPPCHazardRecognizers.cpp26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { argument
27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
32 ScoreboardHazardRecognizer::EmitInstruction(SU);
36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
137 getHazardType(SUnit *SU, int Stalls) { argument
140 MachineInstr *MI = SU->getInstr();
197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { argument
198 MachineInstr *MI = SU->getInstr();
/external/eigen/blas/
H A Dsrotmg.f55 + SQ2,STEMP,SU,TWO,ZERO local in subroutine:SROTMG
86 SU = ONE - SH12*SH21
88 IF (.NOT.SU.LE.ZERO) GO TO 30
93 SD1 = SD1/SU
94 SD2 = SD2/SU
95 SX1 = SX1*SU
106 SU = ONE + SH11*SH22
107 STEMP = SD2/SU
108 SD2 = SD1/SU
110 SX1 = SY1*SU
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