Searched refs:inb (Results 1 - 25 of 37) sorted by relevance

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/external/kernel-headers/original/asm-mips/
H A Di8259.h58 irq = inb(PIC_MASTER_CMD) & 7;
65 irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
77 if(~inb(PIC_MASTER_ISR) & 0x80)
H A Ddma.h27 #define dma_inb inb
/external/grub/netboot/
H A Dtimer.h54 return ((inb(PPC_PORTB) & PPCB_T2OUT) == 0);
60 while ((inb(PPC_PORTB) & PPCB_T2OUT) == 0)
H A Dtimer.c16 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
50 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
72 } while ((inb(0x61) & 0x20) == 0);
H A Dni5010.c175 printf("XSTAT %hhX ", inb(EDLC_XSTAT));
176 printf("XMASK %hhX ", inb(EDLC_XMASK));
177 printf("RSTAT %hhX ", inb(EDLC_RSTAT));
178 printf("RMASK %hhX ", inb(EDLC_RMASK));
179 printf("RMODE %hhX ", inb(EDLC_RMODE));
180 printf("XMODE %hhX ", inb(EDLC_XMODE));
181 printf("ISTAT %hhX\n", inb(IE_ISTAT));
225 if (((rcv_stat = inb(EDLC_RSTAT)) & RS_VALID_BITS) != RS_PKT_OK) {
272 while (((xmt_stat = inb(IE_ISTAT)) & IS_EN_XMT) != 0)
288 inb(IE_RBU
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H A Dtiara.c125 while ((inb(ioaddr + DLCR_RECV_MODE) & BUF_EMPTY) == 0)
126 inb(ioaddr + BMPR_MEM_PORT);
141 if (inb(ioaddr + DLCR_RECV_MODE) & BUF_EMPTY)
186 while (currticks() < time && (inb(ioaddr) & (TMT_OK|TMT_16COLL)) == 0)
188 if ((inb(ioaddr) & (TMT_OK|TMT_16COLL)) == 0)
210 nic->node_addr[i] = inb(ioaddr + PROM_ID + i);
H A Dns8390.c131 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
140 *(dst++) = inb(eth_asic_base + ASIC_PIO);
180 while((inb(eth_asic_base + _3COM_STREG) & _3COM_STREG_DPRDY) == 0)
198 (inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
204 while((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
363 inb(0x84);
367 inb(0x84);
369 inb(0x84);
379 inb(0x84);
383 inb(
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H A Ddepca.c542 nicsr = inb(DEPCA_NICSR);
673 data = inb(DEPCA_PROM); /* clear counter on DEPCA */
674 data = inb(DEPCA_PROM); /* read data */
676 nicsr = inb(DEPCA_NICSR);
681 data = inb(DEPCA_PROM);
691 nicsr = ((inb(DEPCA_NICSR) & ~SHE & ~RBE & ~IEN) | IM);
702 sum += (u8)(nic->node_addr[i++] = inb(DEPCA_PROM));
703 sum += (u16)((nic->node_addr[i++] = inb(DEPCA_PROM)) << 8);
709 chksum = (u8)inb(DEPCA_PROM);
710 chksum |= (u16)(inb(DEPCA_PRO
[all...]
H A Dvia-rhine.c749 byMIIAdrbak = inb (byMIIAD);
750 byMIICRbak = inb (byMIICR);
757 outb (inb (byMIICR) | 0x40, byMIICR);
759 byMIItemp = inb (byMIICR);
764 byMIItemp = inb (byMIICR);
789 byMIIAdrbak = inb (byMIIAD);
791 byMIICRbak = inb (byMIICR);
797 outb (inb (byMIICR) | 0x40, byMIICR);
799 byMIItemp = inb (byMIICR);
804 byMIItemp = inb (byMIIC
[all...]
H A Dsk_g16.c185 #define SK_ROM_ON (inb(SK_POS2) & POS2_CARD)
186 #define SK_ROM_OFF (inb(SK_POS2) | POS2_EPROM)
187 #define SK_RAM_ON (inb(SK_POS2) | POS2_CARD)
188 #define SK_RAM_OFF (inb(SK_POS2) & POS2_EPROM)
755 long offset1, offset0 = inb(ioaddr);
757 ((offset1 = inb(ioaddr + 1)) == SK_IDHIGH))
1110 unsigned char pos0 = inb(SK_POS0),
1111 pos1 = inb(SK_POS1),
1112 pos2 = inb(SK_POS2),
1113 pos3 = inb(SK_POS
[all...]
H A Deepro.c42 #define SLOW_DOWN inb(0x80);
302 temp_reg = inb(ioaddr + eeprom_reg);
310 temp_reg = inb(ioaddr + REG1);
314 temp_reg = inb(ioaddr + REG2); /* match broadcast */
316 temp_reg = inb(ioaddr + REG3);
351 if ((inb(ioaddr + STATUS_REG) & 0x40) == 0)
364 inb(ioaddr + STATUS_REG));
488 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
511 id = inb(ioaddr + ID_REG);
515 if (((id = inb(ioadd
[all...]
H A Drtl8139.c209 *ap++ = inb(ioaddr + MAC0 + i);
212 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
275 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
296 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running())
395 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
456 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running())
H A D3c595.c119 inb(BASE + VX_W1_TX_STATUS);
193 while(( status=inb(BASE + VX_W1_TX_STATUS) )& TXS_COMPLETE ) {
271 nic->packet[rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
284 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + VX_W1_RX_PIO_RD_1);
H A Di82586.c504 if (inb(ioaddr) != '*' || inb(ioaddr+1) != '3'
505 || inb(ioaddr+2) != 'C' || inb(ioaddr+3) != 'O')
507 irq = inb(ioaddr + IRQ_CONFIG) & 0x0f;
508 mem_config = inb(ioaddr + MEM_CONFIG);
522 if_port = inb(ioaddr + ROM_CONFIG) & 0x80;
527 nic->node_addr[i] = inb(ioaddr+i);
632 if (inb(ioaddr + 6) != 0x0 || inb(ioadd
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H A Dlance.c455 nic->node_addr[i] = inb(ioaddr+LANCE_ETH_ADDR+i);
459 dma_channels = ((inb(DMA1_STAT_REG) >> 4) & 0xf) |
460 (inb(DMA2_STAT_REG) & 0xf0);
529 char offset15, offset14 = inb(ioaddr + 14);
534 ((offset15 = inb(ioaddr + 15)) == 0x57 || offset15 == 0x44))
540 ((offset15 = inb(ioaddr + 15)) == 0x55 || offset15 == 0x44))
H A Dsmc9000.c216 status = inb(smc9000_base + INTERRUPT);
234 packet_no = inb(smc9000_base + PNR_ARR + 1);
282 status = inb(smc9000_base + INTERRUPT);
H A D3c509.c115 inb(BASE + EP_W1_TX_STATUS);
185 while ((status=inb(BASE + EP_W1_TX_STATUS)) & TXS_COMPLETE ) {
261 nic->packet[rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);
273 nic->packet[nic->packetlen+rx_fifo-1]=inb(BASE + EP_W1_RX_PIO_RD_1);
359 * the AX register which is conveniently returned to us by inb(). Hence; we
H A Dtlan.c334 return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3)));
2184 if (inb(ioaddr + EISA_CR) != 0x1) { /* Check if adapter is enabled */
2193 switch (inb(ioaddr + 0xCC0)) {
3468 tx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3469 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3470 tx_good += inb( dev->base_addr + TLAN_DIO_DATA + 2 ) << 16;
3471 tx_under = inb( dev->base_addr + TLAN_DIO_DATA + 3 );
3474 rx_good = inb( dev->base_addr + TLAN_DIO_DATA );
3475 rx_good += inb( dev->base_addr + TLAN_DIO_DATA + 1 ) << 8;
3476 rx_good += inb( de
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/external/grub/stage2/
H A Dserial.c66 inb (unsigned short port)
70 asm volatile ("inb %w1, %0" : "=a" (value) : "Nd" (port));
88 if (inb (serial_hw_port + UART_LSR) & UART_DATA_READY)
89 return inb (serial_hw_port + UART_RX);
101 while ((inb (serial_hw_port + UART_LSR) & UART_EMPTY_TRANSMITTER) == 0)
65 inb (unsigned short port) function
H A Dsmp-imps.c73 inb (unsigned short port) function
77 __asm __volatile ("inb %1,%0" :"=a" (data):"d" (port));
99 return inb (0x71);
/external/qemu-pc-bios/bochs/bios/
H A Drombios32start.S95 inb %dx, %al
H A Drombios.c852 static Bit8u inb();
1126 inb(port) function
1410 return inb(base_port + UART_LSR) & 0x20;
1422 while (!(inb(base_port + UART_LSR) & 0x40));
1754 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1760 if (inb(0x64) & 0x01) {
1761 inb(0x60);
1777 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1782 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x01);
1786 if ((inb(
[all...]
/external/qemu-pc-bios/vgabios/
H A Dvgabios.c64 static Bit8u inb();
915 inb(VGAREG_ACTL_RESET);
955 inb(VGAREG_ACTL_RESET);
972 mmask = inb( VGAREG_SEQU_DATA );
2560 inb(VGAREG_ACTL_RESET);
2568 r=inb( VGAREG_DAC_DATA );
2569 g=inb( VGAREG_DAC_DATA );
2570 b=inb( VGAREG_DAC_DATA );
2585 inb(VGAREG_ACTL_RESET);
2654 crtc_r9 = inb(crtc_add
3684 inb(port) function
[all...]
/external/kernel-headers/original/asm-x86/
H A Ddma_32.h22 #define dma_inb inb
/external/llvm/test/MC/X86/
H A Dx86-64.s218 // CHECK: inb $161, %al
219 inb $161, %al label
243 // CHECK: inb $127, %al
248 inb $0x7f label
270 // CHECK: inb %dx
271 // CHECK: inb %dx
278 inb (%dx), %al label

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