1/* rtl8139.c - etherboot driver for the Realtek 8139 chipset 2 3 ported from the linux driver written by Donald Becker 4 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 5 6 This software may be used and distributed according to the terms 7 of the GNU Public License, incorporated herein by reference. 8 9 changes to the original driver: 10 - removed support for interrupts, switching to polling mode (yuck!) 11 - removed support for the 8129 chip (external MII) 12 13*/ 14 15/*********************************************************************/ 16/* Revision History */ 17/*********************************************************************/ 18 19/* 20 21 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) 22 Following email from Hyun-Joon Cha, added a disable routine, otherwise 23 NIC remains live and can crash the kernel later. 24 25 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) 26 Shuffled things around, removed the leftovers from the 8129 support 27 that was in the Linux driver and added a bit more 8139 definitions. 28 Moved the 8K receive buffer to a fixed, available address outside the 29 0x98000-0x9ffff range. This is a bit of a hack, but currently the only 30 way to make room for the Etherboot features that need substantial amounts 31 of code like the ANSI console support. Currently the buffer is just below 32 0x10000, so this even conforms to the tagged boot image specification, 33 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My 34 interpretation of this "reserved" is that Etherboot may do whatever it 35 likes, as long as its environment is kept intact (like the BIOS 36 variables). Hopefully fixed rtl_poll() once and for all. The symptoms 37 were that if Etherboot was left at the boot menu for several minutes, the 38 first eth_poll failed. Seems like I am the only person who does this. 39 First of all I fixed the debugging code and then set out for a long bug 40 hunting session. It took me about a week full time work - poking around 41 various places in the driver, reading Don Becker's and Jeff Garzik's Linux 42 driver and even the FreeBSD driver (what a piece of crap!) - and 43 eventually spotted the nasty thing: the transmit routine was acknowledging 44 each and every interrupt pending, including the RxOverrun and RxFIFIOver 45 interrupts. This confused the RTL8139 thoroughly. It destroyed the 46 Rx ring contents by dumping the 2K FIFO contents right where we wanted to 47 get the next packet. Oh well, what fun. 48 49 18 Jan 2000 mdc@thinguin.org (Marty Connor) 50 Drastically simplified error handling. Basically, if any error 51 in transmission or reception occurs, the card is reset. 52 Also, pointed all transmit descriptors to the same buffer to 53 save buffer space. This should decrease driver size and avoid 54 corruption because of exceeding 32K during runtime. 55 56 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) 57 rtl_poll was quite broken: it used the RxOK interrupt flag instead 58 of the RxBufferEmpty flag which often resulted in very bad 59 transmission performace - below 1kBytes/s. 60 61*/ 62 63#include "etherboot.h" 64#include "nic.h" 65#include "pci.h" 66#include "cards.h" 67#include "timer.h" 68 69#define RTL_TIMEOUT (1*TICKS_PER_SEC) 70 71/* PCI Tuning Parameters 72 Threshold is bytes transferred to chip before transmission starts. */ 73#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 74#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 75#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 76#define TX_DMA_BURST 4 /* Calculate as 16<<val. */ 77#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ 78#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ 79#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ 80#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 81 82#undef DEBUG_TX 83#undef DEBUG_RX 84 85/* Symbolic offsets to registers. */ 86enum RTL8139_registers { 87 MAC0=0, /* Ethernet hardware address. */ 88 MAR0=8, /* Multicast filter. */ 89 TxStatus0=0x10, /* Transmit status (four 32bit registers). */ 90 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ 91 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, 92 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, 93 IntrMask=0x3C, IntrStatus=0x3E, 94 TxConfig=0x40, RxConfig=0x44, 95 Timer=0x48, /* general-purpose counter. */ 96 RxMissed=0x4C, /* 24 bits valid, write clears. */ 97 Cfg9346=0x50, Config0=0x51, Config1=0x52, 98 TimerIntrReg=0x54, /* intr if gp counter reaches this value */ 99 MediaStatus=0x58, 100 Config3=0x59, 101 MultiIntr=0x5C, 102 RevisionID=0x5E, /* revision of the RTL8139 chip */ 103 TxSummary=0x60, 104 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, 105 NWayExpansion=0x6A, 106 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, 107 NWayTestReg=0x70, 108 RxCnt=0x72, /* packet received counter */ 109 CSCR=0x74, /* chip status and configuration register */ 110 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ 111 /* from 0x84 onwards are a number of power management/wakeup frame 112 * definitions we will probably never need to know about. */ 113}; 114 115enum ChipCmdBits { 116 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; 117 118/* Interrupt register bits, using my own meaningful names. */ 119enum IntrStatusBits { 120 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, 121 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, 122 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, 123}; 124enum TxStatusBits { 125 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, 126 TxOutOfWindow=0x20000000, TxAborted=0x40000000, 127 TxCarrierLost=0x80000000, 128}; 129enum RxStatusBits { 130 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, 131 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, 132 RxBadAlign=0x0002, RxStatusOK=0x0001, 133}; 134 135enum MediaStatusBits { 136 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, 137 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, 138}; 139 140enum MIIBMCRBits { 141 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, 142 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, 143}; 144 145enum CSCRBits { 146 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, 147 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, 148 CSCR_LinkDownCmd=0x0f3c0, 149}; 150 151/* Bits in RxConfig. */ 152enum rx_mode_bits { 153 RxCfgWrap=0x80, 154 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, 155 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, 156}; 157 158static int ioaddr; 159static unsigned int cur_rx,cur_tx; 160 161/* The RTL8139 can only transmit from a contiguous, aligned memory block. */ 162static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); 163 164/* I know that this is a MEGA HACK, but the tagged boot image specification 165 * states that we can do whatever we want below 0x10000 - so we do! */ 166/* But we still give the user the choice of using an internal buffer 167 just in case - Ken */ 168#ifdef USE_LOWMEM_BUFFER 169#define rx_ring ((unsigned char *)(0x10000 - (RX_BUF_LEN + 16))) 170#else 171static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); 172#endif 173 174struct nic *rtl8139_probe(struct nic *nic, unsigned short *probeaddrs, 175 struct pci_device *pci); 176static int read_eeprom(int location); 177static void rtl_reset(struct nic *nic); 178static void rtl_transmit(struct nic *nic, const char *destaddr, 179 unsigned int type, unsigned int len, const char *data); 180static int rtl_poll(struct nic *nic); 181static void rtl_disable(struct nic*); 182 183 184struct nic *rtl8139_probe(struct nic *nic, unsigned short *probeaddrs, 185 struct pci_device *pci) 186{ 187 int i; 188 int speed10, fullduplex; 189 190 /* There are enough "RTL8139" strings on the console already, so 191 * be brief and concentrate on the interesting pieces of info... */ 192 printf(" - "); 193 194 /* Mask the bit that says "this is an io addr" */ 195 ioaddr = probeaddrs[0] & ~3; 196 197 adjust_pci_device(pci); 198 199 /* Bring the chip out of low-power mode. */ 200 outb(0x00, ioaddr + Config1); 201 202 if (read_eeprom(0) != 0xffff) { 203 unsigned short *ap = (unsigned short*)nic->node_addr; 204 for (i = 0; i < 3; i++) 205 *ap++ = read_eeprom(i + 7); 206 } else { 207 unsigned char *ap = (unsigned char*)nic->node_addr; 208 for (i = 0; i < ETH_ALEN; i++) 209 *ap++ = inb(ioaddr + MAC0 + i); 210 } 211 212 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; 213 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex; 214 printf("ioaddr %#hX, addr %! %sMbps %s-duplex\n", ioaddr, 215 nic->node_addr, speed10 ? "10" : "100", 216 fullduplex ? "full" : "half"); 217 218 rtl_reset(nic); 219 220 nic->reset = rtl_reset; 221 nic->poll = rtl_poll; 222 nic->transmit = rtl_transmit; 223 nic->disable = rtl_disable; 224 225 return nic; 226} 227 228/* Serial EEPROM section. */ 229 230/* EEPROM_Ctrl bits. */ 231#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 232#define EE_CS 0x08 /* EEPROM chip select. */ 233#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 234#define EE_WRITE_0 0x00 235#define EE_WRITE_1 0x02 236#define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 237#define EE_ENB (0x80 | EE_CS) 238 239/* 240 Delay between EEPROM clock transitions. 241 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 242*/ 243 244#define eeprom_delay() inl(ee_addr) 245 246/* The EEPROM commands include the alway-set leading bit. */ 247#define EE_WRITE_CMD (5 << 6) 248#define EE_READ_CMD (6 << 6) 249#define EE_ERASE_CMD (7 << 6) 250 251static int read_eeprom(int location) 252{ 253 int i; 254 unsigned int retval = 0; 255 long ee_addr = ioaddr + Cfg9346; 256 int read_cmd = location | EE_READ_CMD; 257 258 outb(EE_ENB & ~EE_CS, ee_addr); 259 outb(EE_ENB, ee_addr); 260 261 /* Shift the read command bits out. */ 262 for (i = 10; i >= 0; i--) { 263 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 264 outb(EE_ENB | dataval, ee_addr); 265 eeprom_delay(); 266 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 267 eeprom_delay(); 268 } 269 outb(EE_ENB, ee_addr); 270 eeprom_delay(); 271 272 for (i = 16; i > 0; i--) { 273 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); 274 eeprom_delay(); 275 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); 276 outb(EE_ENB, ee_addr); 277 eeprom_delay(); 278 } 279 280 /* Terminate the EEPROM access. */ 281 outb(~EE_CS, ee_addr); 282 return retval; 283} 284 285static void rtl_reset(struct nic* nic) 286{ 287 int i; 288 289 outb(CmdReset, ioaddr + ChipCmd); 290 291 cur_rx = 0; 292 cur_tx = 0; 293 294 /* Give the chip 10ms to finish the reset. */ 295 load_timer2(10*TICKS_PER_MS); 296 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) 297 /* wait */; 298 299 for (i = 0; i < ETH_ALEN; i++) 300 outb(nic->node_addr[i], ioaddr + MAC0 + i); 301 302 /* Must enable Tx/Rx before setting transfer thresholds! */ 303 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 304 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), 305 ioaddr + RxConfig); /* accept no frames yet! */ 306 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); 307 308 /* The Linux driver changes Config1 here to use a different LED pattern 309 * for half duplex or full/autodetect duplex (for full/autodetect, the 310 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses 311 * TX/RX, Link100, Link10). This is messy, because it doesn't match 312 * the inscription on the mounting bracket. It should not be changed 313 * from the configuration EEPROM default, because the card manufacturer 314 * should have set that to match the card. */ 315 316#ifdef DEBUG_RX 317 printf("rx ring address is %X\n",(unsigned long)rx_ring); 318#endif 319 outl((unsigned long)rx_ring, ioaddr + RxBuf); 320 321 /* Start the chip's Tx and Rx process. */ 322 outl(0, ioaddr + RxMissed); 323 /* set_rx_mode */ 324 outb(AcceptBroadcast|AcceptMyPhys, ioaddr + RxConfig); 325 /* If we add multicast support, the MAR0 register would have to be 326 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot 327 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ 328 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 329 330 /* Disable all known interrupts by setting the interrupt mask. */ 331 outw(0, ioaddr + IntrMask); 332} 333 334static void rtl_transmit(struct nic *nic, const char *destaddr, 335 unsigned int type, unsigned int len, const char *data) 336{ 337 unsigned int status, to, nstype; 338 unsigned long txstatus; 339 340 memcpy(tx_buffer, destaddr, ETH_ALEN); 341 memcpy(tx_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN); 342 nstype = htons(type); 343 memcpy(tx_buffer + 2 * ETH_ALEN, (char*)&nstype, 2); 344 memcpy(tx_buffer + ETH_HLEN, data, len); 345 346 len += ETH_HLEN; 347#ifdef DEBUG_TX 348 printf("sending %d bytes ethtype %hX\n", len, type); 349#endif 350 351 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 352 * bytes are sent automatically for the FCS, totalling to 64 bytes). */ 353 while (len < ETH_ZLEN) { 354 tx_buffer[len++] = '\0'; 355 } 356 357 outl((unsigned long)tx_buffer, ioaddr + TxAddr0 + cur_tx*4); 358 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, 359 ioaddr + TxStatus0 + cur_tx*4); 360 361 to = currticks() + RTL_TIMEOUT; 362 363 do { 364 status = inw(ioaddr + IntrStatus); 365 /* Only acknlowledge interrupt sources we can properly handle 366 * here - the RxOverflow/RxFIFOOver MUST be handled in the 367 * rtl_poll() function. */ 368 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); 369 if ((status & (TxOK | TxErr | PCIErr)) != 0) break; 370 } while (currticks() < to); 371 372 txstatus = inl(ioaddr+ TxStatus0 + cur_tx*4); 373 374 if (status & TxOK) { 375 cur_tx = (cur_tx + 1) % NUM_TX_DESC; 376#ifdef DEBUG_TX 377 printf("tx done (%d ticks), status %hX txstatus %X\n", 378 to-currticks(), status, txstatus); 379#endif 380 } else { 381#ifdef DEBUG_TX 382 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n", 383 currticks()-to, status, txstatus); 384#endif 385 rtl_reset(nic); 386 } 387} 388 389static int rtl_poll(struct nic *nic) 390{ 391 unsigned int status; 392 unsigned int ring_offs; 393 unsigned int rx_size, rx_status; 394 395 if (inb(ioaddr + ChipCmd) & RxBufEmpty) { 396 return 0; 397 } 398 399 status = inw(ioaddr + IntrStatus); 400 /* See below for the rest of the interrupt acknowledges. */ 401 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 402 403#ifdef DEBUG_RX 404 printf("rtl_poll: int %hX ", status); 405#endif 406 407 ring_offs = cur_rx % RX_BUF_LEN; 408 rx_status = *(unsigned int*)(rx_ring + ring_offs); 409 rx_size = rx_status >> 16; 410 rx_status &= 0xffff; 411 412 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || 413 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { 414 printf("rx error %hX\n", rx_status); 415 rtl_reset(nic); /* this clears all interrupts still pending */ 416 return 0; 417 } 418 419 /* Received a good packet */ 420 nic->packetlen = rx_size - 4; /* no one cares about the FCS */ 421 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { 422 int semi_count = RX_BUF_LEN - ring_offs - 4; 423 424 memcpy(nic->packet, rx_ring + ring_offs + 4, semi_count); 425 memcpy(nic->packet+semi_count, rx_ring, rx_size-4-semi_count); 426#ifdef DEBUG_RX 427 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count); 428#endif 429 } else { 430 memcpy(nic->packet, rx_ring + ring_offs + 4, nic->packetlen); 431#ifdef DEBUG_RX 432 printf("rx packet %d bytes", rx_size-4); 433#endif 434 } 435#ifdef DEBUG_RX 436 printf(" at %X type %hhX%hhX rxstatus %hX\n", 437 (unsigned long)(rx_ring+ring_offs+4), 438 nic->packet[12], nic->packet[13], rx_status); 439#endif 440 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 441 outw(cur_rx - 16, ioaddr + RxBufPtr); 442 /* See RTL8139 Programming Guide V0.1 for the official handling of 443 * Rx overflow situations. The document itself contains basically no 444 * usable information, except for a few exception handling rules. */ 445 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 446 return 1; 447} 448 449static void rtl_disable(struct nic *nic) 450{ 451 /* reset the chip */ 452 outb(CmdReset, ioaddr + ChipCmd); 453 454 /* 10 ms timeout */ 455 load_timer2(10*TICKS_PER_MS); 456 while ((inb(ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) 457 /* wait */; 458} 459