Searched refs:outw (Results 1 - 25 of 38) sorted by relevance

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/external/grub/netboot/
H A D3c595.c74 outw(RX_DISABLE, BASE + VX_COMMAND);
75 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND);
77 outw(TX_DISABLE, BASE + VX_COMMAND);
78 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND);
80 outw(RX_RESET, BASE + VX_COMMAND);
82 outw(TX_RESET, BASE + VX_COMMAND);
84 outw(C_INTR_LATCH, BASE + VX_COMMAND);
85 outw(SET_RD_0_MASK, BASE + VX_COMMAND);
86 outw(SET_INTR_MASK, BASE + VX_COMMAND);
87 outw(SET_RX_FILTE
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H A D3c509.c72 outw(RX_DISABLE, BASE + EP_COMMAND);
73 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
76 outw(TX_DISABLE, BASE + EP_COMMAND);
77 outw(STOP_TRANSCEIVER, BASE + EP_COMMAND);
79 outw(RX_RESET, BASE + EP_COMMAND);
80 outw(TX_RESET, BASE + EP_COMMAND);
81 outw(C_INTR_LATCH, BASE + EP_COMMAND);
82 outw(SET_RD_0_MASK, BASE + EP_COMMAND);
83 outw(SET_INTR_MASK, BASE + EP_COMMAND);
84 outw(SET_RX_FILTE
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H A Dlance.c221 outw(0, ioaddr+LANCE_RESET);
226 outw(0x2, ioaddr+LANCE_ADDR);
228 outw(inw(ioaddr+LANCE_BUS_IF) | 0x2, ioaddr+LANCE_BUS_IF);
237 outw(49, ioaddr+0x12) ;
249 outw(49, ioaddr+0x12) ;
250 outw(media, ioaddr+0x16) ;
251 outw(49, ioaddr+0x12) ;
274 outw(0x1, ioaddr+LANCE_ADDR);
276 outw((short)l, ioaddr+LANCE_DATA);
277 outw(
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H A Dcs89x0.c85 outw(portno, eth_nic_base + ADD_PORT);
91 outw(portno, eth_nic_base + ADD_PORT);
92 outw(value, eth_nic_base + DATA_PORT);
248 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
249 outw(ETH_ZLEN, eth_nic_base + TX_LEN_PORT);
318 outw(PP_CS8920_ISAINT, eth_nic_base + ADD_PORT);
323 outw(PP_CS8920_ISAMemB, eth_nic_base + ADD_PORT);
354 outw(PP_ChipID, eth_nic_base + ADD_PORT);
380 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT);
381 outw(s
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H A Deepro100.c326 outw(EE_ENB, ee_addr); udelay(2);
327 outw(EE_ENB | EE_SHIFT_CLK, ee_addr); udelay(2);
332 outw(dataval, ee_addr); udelay(2);
333 outw(dataval | EE_SHIFT_CLK, ee_addr); udelay(2);
336 outw(EE_ENB, ee_addr); udelay(2);
339 outw(EE_ENB & ~EE_CS, ee_addr);
387 outw(status & 0xfc00, ioaddr + SCBStatus);
417 outw(INT_MASK | CU_START, ioaddr + SCBCmd);
452 outw(INT_MASK | RX_START, ioaddr + SCBCmd);
530 outw(INT_MAS
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H A D3c90x.c266 outw(val, ioaddr + regCommandIntStatus_w);
306 outw(address + ((0x02)<<6), ioaddr + regEepromCommand_0_w);
329 outw(0x30, ioaddr + regEepromCommand_0_w);
333 outw(address + ((0x03)<<6), ioaddr + regEepromCommand_0_w);
337 outw(value, ioaddr + regEepromData_0_w);
338 outw(0x30, ioaddr + regEepromCommand_0_w);
342 outw(address + ((0x01)<<6), ioaddr + regEepromCommand_0_w);
418 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+0);
419 outw(0, INF_3C90X.IOAddr + regStationMask_2_3w+2);
420 outw(
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H A Dni5010.c187 outw(0, IE_GP); /* Receive packet at start of buffer */
233 outw(0, IE_GP); /* Seek to beginning of packet */
258 outw(buf_offs, IE_GP); /* Point GP at start of packet */
266 outw(buf_offs, IE_GP); /* Rewrite where packet starts */
319 outw(i, IE_GP);
329 outw(0, IE_GP); /* Point GP at start of packet */
332 outw(i << 8, IE_GP); /* Point GP at packet size to be tested */
334 outw(0x0, IE_GP); /* Point GP at start of packet */
339 outw(0, IE_GP); /* Point GP at start of packet */
H A Ddepca.c471 outw(CSR0, DEPCA_ADDR);\
472 outw(STOP, DEPCA_DATA)
503 outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */
504 outw((u16) (lp.sh_mem & LA_MASK), DEPCA_DATA);
505 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */
506 outw((u16) ((lp.sh_mem & LA_MASK) >> 16), DEPCA_DATA);
507 outw(CSR3, DEPCA_ADDR); /* ALE control */
508 outw(ACON, DEPCA_DATA);
509 outw(CSR0, DEPCA_ADDR); /* Point back to CSR0 */
518 outw(CSR
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H A Dtiara.c144 outw(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT);
177 outw(t, ioaddr + BMPR_MEM_PORT);
183 outw(len | (TMST << 8), ioaddr + BMPR_PKT_LEN);
H A Deepro.c328 outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR);
329 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), ioaddr + RCV_STOP);
331 outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar);
355 outw(rcv_car, ioaddr + HOST_ADDRESS_REG);
383 outw(rcv_car - 1, ioaddr + RCV_STOP);
414 outw(last, ioaddr + HOST_ADDRESS_REG);
415 outw(XMT_CMD, ioaddr + IO_PORT);
416 outw(0, ioaddr + IO_PORT);
417 outw(end, ioaddr + IO_PORT);
418 outw(lengt
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H A Dnatsemi.c466 outw(0x0001, ioaddr + PGSEL);
467 outw(0x189C, ioaddr + PMDCSR);
468 outw(0x0000, ioaddr + TSTDAT);
469 outw(0x5040, ioaddr + DSPCFG);
470 outw(0x008C, ioaddr + SDCFG);
493 outw(nic->node_addr[i] + (nic->node_addr[i+1] << 8), ioaddr + RxFilterData);
H A Drtl8139.c331 outw(0, ioaddr + IntrMask);
368 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
401 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
441 outw(cur_rx - 16, ioaddr + RxBufPtr);
445 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
H A Dtlan.c333 outw(internal_addr, base_addr + TLAN_DIO_ADR);
340 outw(internal_addr, base_addr + TLAN_DIO_ADR);
347 outw(internal_addr, base_addr + TLAN_DIO_ADR);
354 outw(internal_addr, base_addr + TLAN_DIO_ADR);
361 outw(internal_addr, base_addr + TLAN_DIO_ADR);
362 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2));
368 outw(internal_addr, base_addr + TLAN_DIO_ADR);
407 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
446 outw( TLAN_NET_SIO, io_base + TLAN_DIO_ADR );
503 outw( TLAN_NET_SI
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H A Dvia-rhine.c824 outw (ReadMIItmp, wMIIDATA);
939 outw (CR_FDX, byCR0);
1073 outw (0x0000, byIMR0);
1085 outw (CR_FDX, byCR0);
1091 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
1094 outw (IMRShadow, byIMR0);
1175 /*outw(IMRShadow,byIMR0); */
/external/openssl/crypto/evp/
H A De_xcbc_d.c79 DES_cblock outw; member in struct:__anon10419
111 memcpy(&data(ctx)->outw[0],&key[16],8);
124 &data(ctx)->outw,
134 &data(ctx)->outw,
/external/chromium/base/
H A Dstringprintf_unittest.cc83 std::wstring outw; local
84 SStringPrintf(&outw, L"%ls", srcw);
85 EXPECT_STREQ(srcw, outw.c_str());
/external/qemu-pc-bios/bochs/bios/
H A Drombios32start.S103 outw %ax, %dx
115 outw %ax, %dx
/external/qemu-pc-bios/vgabios/
H A Dvbe.c269 outw(VBE_DISPI_IOPORT_INDEX,VBE_DISPI_INDEX_YRES);
270 outw(VBE_DISPI_IOPORT_DATA,yres);
276 outw(VBE_DISPI_IOPORT_INDEX,VBE_DISPI_INDEX_BPP);
277 outw(VBE_DISPI_IOPORT_DATA,bpp);
835 outw(VBE_DISPI_IOPORT_INDEX, VBE_DISPI_INDEX_VIDEO_MEMORY_64K);
1089 outw(VBE_DISPI_IOPORT_INDEX,VBE_DISPI_INDEX_ENABLE);
1097 outw(VBE_DISPI_IOPORT_INDEX, i);
1114 outw(VBE_DISPI_IOPORT_INDEX,VBE_DISPI_INDEX_ENABLE);
1115 outw(VBE_DISPI_IOPORT_DATA, enable);
1117 outw(VBE_DISPI_IOPORT_INDE
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H A Dvgabios.c67 static void outw();
943 outw(crtc_addr,0x0011);
1200 outw(VGAREG_GRDC_ADDRESS, 0x0105);
1205 outw(VGAREG_GRDC_ADDRESS, 0x0005);
1216 outw(VGAREG_GRDC_ADDRESS, 0x0205);
1221 outw(VGAREG_GRDC_ADDRESS, 0x0005);
1335 outw(VGAREG_GRDC_ADDRESS, 0x0205);
1337 outw(VGAREG_GRDC_ADDRESS, 0x0005);
1464 outw(VGAREG_SEQU_ADDRESS, 0x0f02);
1465 outw(VGAREG_GRDC_ADDRES
3741 outw(port, val) function
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/external/openssl/crypto/des/
H A Ddes_old.c111 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc)
114 length, (DES_key_schedule *)schedule, ivec, inw, outw, enc);
109 _ossl_old_des_xcbc_encrypt(_ossl_old_des_cblock *input,_ossl_old_des_cblock *output,long length, des_key_schedule schedule,_ossl_old_des_cblock *ivec, _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc) argument
H A Dxcbc_enc.c115 const_DES_cblock *outw, int enc)
128 in2 = &(*outw)[0];
112 DES_xcbc_encrypt(const unsigned char *in, unsigned char *out, long length, DES_key_schedule *schedule, DES_cblock *ivec, const_DES_cblock *inw, const_DES_cblock *outw, int enc) argument
H A Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
/external/openssl/include/openssl/
H A Ddes_old.h156 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
157 DES_xcbc_encrypt((i),(o),(l),&(k),(iv),(inw),(outw),(e))
259 #define des_xcbc_encrypt(i,o,l,k,iv,inw,outw,e)\
260 _ossl_old_des_xcbc_encrypt((i),(o),(l),(k),(iv),(inw),(outw),(e))
347 _ossl_old_des_cblock *inw,_ossl_old_des_cblock *outw,int enc);
/external/llvm/test/MC/X86/
H A Dx86-64.s216 // CHECK: outw %ax, $128
217 outw %ax, $128 label
246 // CHECK: outw %dx
251 outw %dx label
258 // CHECK: outw %dx
259 // CHECK: outw %dx
266 outw %ax, (%dx) label
/external/kernel-headers/original/asm-arm/
H A Dio.h112 #define outw(v,p) __raw_writew((__force __u16) \ macro
133 #define outw_p(val,port) outw((val),(port))

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