1/**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19#ifndef _ASM_MIPSMTREGS_H 20#define _ASM_MIPSMTREGS_H 21#include <asm/mipsregs.h> 22#include <asm/war.h> 23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24#ifndef __ASSEMBLY__ 25#define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1) 26#define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) 27#define read_c0_mvpconf0() __read_32bit_c0_register($0, 2) 28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29#define read_c0_mvpconf1() __read_32bit_c0_register($0, 3) 30#define read_c0_vpecontrol() __read_32bit_c0_register($1, 1) 31#define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) 32#define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) 33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34#define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) 35#define read_c0_tcstatus() __read_32bit_c0_register($2, 1) 36#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) 37#define read_c0_tcbind() __read_32bit_c0_register($2, 2) 38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39#define read_c0_tccontext() __read_32bit_c0_register($2, 5) 40#define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) 41#else 42#define CP0_MVPCONTROL $0, 1 43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44#define CP0_MVPCONF0 $0, 2 45#define CP0_MVPCONF1 $0, 3 46#define CP0_VPECONTROL $1, 1 47#define CP0_VPECONF0 $1, 2 48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49#define CP0_VPECONF1 $1, 3 50#define CP0_YQMASK $1, 4 51#define CP0_VPESCHEDULE $1, 5 52#define CP0_VPESCHEFBK $1, 6 53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54#define CP0_TCSTATUS $2, 1 55#define CP0_TCBIND $2, 2 56#define CP0_TCRESTART $2, 3 57#define CP0_TCHALT $2, 4 58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59#define CP0_TCCONTEXT $2, 5 60#define CP0_TCSCHEDULE $2, 6 61#define CP0_TCSCHEFBK $2, 7 62#define CP0_SRSCONF0 $6, 1 63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64#define CP0_SRSCONF1 $6, 2 65#define CP0_SRSCONF2 $6, 3 66#define CP0_SRSCONF3 $6, 4 67#define CP0_SRSCONF4 $6, 5 68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69#endif 70#define MVPCONTROL_EVP (_ULCAST_(1)) 71#define MVPCONTROL_VPC_SHIFT 1 72#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) 73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74#define MVPCONTROL_STLB_SHIFT 2 75#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) 76#define MVPCONF0_PTC_SHIFT 0 77#define MVPCONF0_PTC ( _ULCAST_(0xff)) 78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79#define MVPCONF0_PVPE_SHIFT 10 80#define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) 81#define MVPCONF0_TCA_SHIFT 15 82#define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) 83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84#define MVPCONF0_PTLBE_SHIFT 16 85#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) 86#define MVPCONF0_TLBS_SHIFT 29 87#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) 88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89#define MVPCONF0_M_SHIFT 31 90#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) 91#define CONFIG3_MT_SHIFT 2 92#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) 93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94#define VPECONTROL_TARGTC (_ULCAST_(0xff)) 95#define VPECONTROL_TE_SHIFT 15 96#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) 97#define VPECONTROL_EXCPT_SHIFT 16 98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) 100#define THREX_TU 0 101#define THREX_TO 1 102#define THREX_IYQ 2 103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104#define THREX_GSX 3 105#define THREX_YSCH 4 106#define THREX_GSSCH 5 107#define VPECONTROL_GSI_SHIFT 20 108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) 110#define VPECONTROL_YSI_SHIFT 21 111#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) 112#define VPECONF0_VPA_SHIFT 0 113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) 115#define VPECONF0_MVP_SHIFT 1 116#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) 117#define VPECONF0_XTC_SHIFT 21 118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) 120#define TCSTATUS_TASID (_ULCAST_(0xff)) 121#define TCSTATUS_IXMT_SHIFT 10 122#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) 123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124#define TCSTATUS_TKSU_SHIFT 11 125#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) 126#define TCSTATUS_A_SHIFT 13 127#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) 128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129#define TCSTATUS_DA_SHIFT 15 130#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) 131#define TCSTATUS_DT_SHIFT 20 132#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) 133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134#define TCSTATUS_TDS_SHIFT 21 135#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) 136#define TCSTATUS_TSST_SHIFT 22 137#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) 138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139#define TCSTATUS_RNST_SHIFT 23 140#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) 141#define TC_RUNNING 0 142#define TC_WAITING 1 143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144#define TC_YIELDING 2 145#define TC_GATED 3 146#define TCSTATUS_TMX_SHIFT 27 147#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) 148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149#define TCBIND_CURVPE_SHIFT 0 150#define TCBIND_CURVPE (_ULCAST_(0xf)) 151#define TCBIND_CURTC_SHIFT 21 152#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) 153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154#define TCHALT_H (_ULCAST_(1)) 155#ifndef __ASSEMBLY__ 156#define EVPE_ENABLE MVPCONTROL_EVP 157#define EMT_ENABLE VPECONTROL_TE 158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159#define mftc0(rt,sel) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " # mftc0 $1, $" #rt ", " #sel " \n" " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; }) 160#define mftgpr(rt) ({ unsigned long __res; __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips32r2 \n" " # mftgpr $1," #rt " \n" " .word 0x41000820 | (" #rt " << 16) \n" " move %0, $1 \n" " .set pop \n" : "=r" (__res)); __res; }) 161#define mftr(rt, u, sel) ({ unsigned long __res; __asm__ __volatile__( " mftr %0, " #rt ", " #u ", " #sel " \n" : "=r" (__res)); __res; }) 162#define mttgpr(rd,v) do { __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttgpr $1, " #rd " \n" " .word 0x41810020 | (" #rd " << 11) \n" " .set pop \n" : : "r" (v)); } while (0) 163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164#define mttc0(rd, sel, v) ({ __asm__ __volatile__( " .set push \n" " .set mips32r2 \n" " .set noat \n" " move $1, %0 \n" " # mttc0 %0," #rd ", " #sel " \n" " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" " .set pop \n" : : "r" (v)); }) 165#define mttr(rd, u, sel, v) ({ __asm__ __volatile__( "mttr %0," #rd ", " #u ", " #sel : : "r" (v)); }) 166#define settc(tc) do { write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); ehb(); } while (0) 167#define read_vpe_c0_vpecontrol() mftc0(1, 1) 168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) 170#define read_vpe_c0_vpeconf0() mftc0(1, 2) 171#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) 172#define read_vpe_c0_count() mftc0(9, 0) 173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174#define write_vpe_c0_count(val) mttc0(9, 0, val) 175#define read_vpe_c0_status() mftc0(12, 0) 176#define write_vpe_c0_status(val) mttc0(12, 0, val) 177#define read_vpe_c0_cause() mftc0(13, 0) 178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179#define write_vpe_c0_cause(val) mttc0(13, 0, val) 180#define read_vpe_c0_config() mftc0(16, 0) 181#define write_vpe_c0_config(val) mttc0(16, 0, val) 182#define read_vpe_c0_config1() mftc0(16, 1) 183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184#define write_vpe_c0_config1(val) mttc0(16, 1, val) 185#define read_vpe_c0_config7() mftc0(16, 7) 186#define write_vpe_c0_config7(val) mttc0(16, 7, val) 187#define read_vpe_c0_ebase() mftc0(15, 1) 188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189#define write_vpe_c0_ebase(val) mttc0(15, 1, val) 190#define write_vpe_c0_compare(val) mttc0(11, 0, val) 191#define read_vpe_c0_badvaddr() mftc0(8, 0) 192#define read_vpe_c0_epc() mftc0(14, 0) 193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194#define write_vpe_c0_epc(val) mttc0(14, 0, val) 195#define read_tc_c0_tcstatus() mftc0(2, 1) 196#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) 197#define read_tc_c0_tcbind() mftc0(2, 2) 198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199#define write_tc_c0_tcbind(val) mttc0(2, 2, val) 200#define read_tc_c0_tcrestart() mftc0(2, 3) 201#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) 202#define read_tc_c0_tchalt() mftc0(2, 4) 203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204#define write_tc_c0_tchalt(val) mttc0(2, 4, val) 205#define read_tc_c0_tccontext() mftc0(2, 5) 206#define write_tc_c0_tccontext(val) mttc0(2, 5, val) 207#define read_tc_gpr_sp() mftgpr(29) 208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209#define write_tc_gpr_sp(val) mttgpr(29, val) 210#define read_tc_gpr_gp() mftgpr(28) 211#define write_tc_gpr_gp(val) mttgpr(28, val) 212#endif 213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214#endif 215