1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _SGI_HPC3_H
20#define _SGI_HPC3_H
21#include <linux/types.h>
22#include <asm/page.h>
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24struct hpc_dma_desc {
25 u32 pbuf;
26 u32 cntinfo;
27#define HPCDMA_EOX 0x80000000
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define HPCDMA_EOR 0x80000000
30#define HPCDMA_EOXP 0x40000000
31#define HPCDMA_EORP 0x40000000
32#define HPCDMA_XIE 0x20000000
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define HPCDMA_XIU 0x01000000
35#define HPCDMA_EIPC 0x00ff0000
36#define HPCDMA_ETXD 0x00008000
37#define HPCDMA_OWN 0x00004000
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define HPCDMA_BCNT 0x00003fff
40 u32 pnext;
41};
42struct hpc3_pbus_dmacregs {
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44 volatile u32 pbdma_bptr;
45 volatile u32 pbdma_dptr;
46 u32 _unused0[0x1000/4 - 2];
47 volatile u32 pbdma_ctrl;
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define HPC3_PDMACTRL_INT 0x00000001
50#define HPC3_PDMACTRL_ISACT 0x00000002
51#define HPC3_PDMACTRL_SEL 0x00000002
52#define HPC3_PDMACTRL_RCV 0x00000004
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define HPC3_PDMACTRL_FLSH 0x00000008
55#define HPC3_PDMACTRL_ACT 0x00000010
56#define HPC3_PDMACTRL_LD 0x00000020
57#define HPC3_PDMACTRL_RT 0x00000040
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define HPC3_PDMACTRL_HW 0x0000ff00
60#define HPC3_PDMACTRL_FB 0x003f0000
61#define HPC3_PDMACTRL_FE 0x3f000000
62 u32 _unused1[0x1000/4 - 1];
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64};
65struct hpc3_scsiregs {
66 volatile u32 cbptr;
67 volatile u32 ndptr;
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69 u32 _unused0[0x1000/4 - 2];
70 volatile u32 bcd;
71#define HPC3_SBCD_BCNTMSK 0x00003fff
72#define HPC3_SBCD_XIE 0x00004000
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define HPC3_SBCD_EOX 0x00008000
75 volatile u32 ctrl;
76#define HPC3_SCTRL_IRQ 0x01
77#define HPC3_SCTRL_ENDIAN 0x02
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define HPC3_SCTRL_DIR 0x04
80#define HPC3_SCTRL_FLUSH 0x08
81#define HPC3_SCTRL_ACTIVE 0x10
82#define HPC3_SCTRL_AMASK 0x20
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define HPC3_SCTRL_CRESET 0x40
85#define HPC3_SCTRL_PERR 0x80
86 volatile u32 gfptr;
87 volatile u32 dfptr;
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89 volatile u32 dconfig;
90#define HPC3_SDCFG_HCLK 0x00001
91#define HPC3_SDCFG_D1 0x00006
92#define HPC3_SDCFG_D2 0x00038
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define HPC3_SDCFG_D3 0x001c0
95#define HPC3_SDCFG_HWAT 0x00e00
96#define HPC3_SDCFG_HW 0x01000
97#define HPC3_SDCFG_SWAP 0x02000
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99#define HPC3_SDCFG_EPAR 0x04000
100#define HPC3_SDCFG_POLL 0x08000
101#define HPC3_SDCFG_ERLY 0x30000
102 volatile u32 pconfig;
103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
104#define HPC3_SPCFG_P3 0x0003
105#define HPC3_SPCFG_P2W 0x001c
106#define HPC3_SPCFG_P2R 0x01e0
107#define HPC3_SPCFG_P1 0x0e00
108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
109#define HPC3_SPCFG_HW 0x1000
110#define HPC3_SPCFG_SWAP 0x2000
111#define HPC3_SPCFG_EPAR 0x4000
112#define HPC3_SPCFG_FUJI 0x8000
113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
114 u32 _unused1[0x1000/4 - 6];
115};
116struct hpc3_ethregs {
117 volatile u32 rx_cbptr;
118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
119 volatile u32 rx_ndptr;
120 u32 _unused0[0x1000/4 - 2];
121 volatile u32 rx_bcd;
122#define HPC3_ERXBCD_BCNTMSK 0x00003fff
123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
124#define HPC3_ERXBCD_XIE 0x20000000
125#define HPC3_ERXBCD_EOX 0x80000000
126 volatile u32 rx_ctrl;
127#define HPC3_ERXCTRL_STAT50 0x0000003f
128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
129#define HPC3_ERXCTRL_STAT6 0x00000040
130#define HPC3_ERXCTRL_STAT7 0x00000080
131#define HPC3_ERXCTRL_ENDIAN 0x00000100
132#define HPC3_ERXCTRL_ACTIVE 0x00000200
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134#define HPC3_ERXCTRL_AMASK 0x00000400
135#define HPC3_ERXCTRL_RBO 0x00000800
136 volatile u32 rx_gfptr;
137 volatile u32 rx_dfptr;
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
139 u32 _unused1;
140 volatile u32 reset;
141#define HPC3_ERST_CRESET 0x1
142#define HPC3_ERST_CLRIRQ 0x2
143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
144#define HPC3_ERST_LBACK 0x4
145 volatile u32 dconfig;
146#define HPC3_EDCFG_D1 0x0000f
147#define HPC3_EDCFG_D2 0x000f0
148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
149#define HPC3_EDCFG_D3 0x00f00
150#define HPC3_EDCFG_WCTRL 0x01000
151#define HPC3_EDCFG_FRXDC 0x02000
152#define HPC3_EDCFG_FEOP 0x04000
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154#define HPC3_EDCFG_FIRQ 0x08000
155#define HPC3_EDCFG_PTO 0x30000
156 volatile u32 pconfig;
157#define HPC3_EPCFG_P1 0x000f
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
159#define HPC3_EPCFG_P2 0x00f0
160#define HPC3_EPCFG_P3 0x0f00
161#define HPC3_EPCFG_TST 0x1000
162 u32 _unused2[0x1000/4 - 8];
163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
164 volatile u32 tx_cbptr;
165 volatile u32 tx_ndptr;
166 u32 _unused3[0x1000/4 - 2];
167 volatile u32 tx_bcd;
168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
169#define HPC3_ETXBCD_BCNTMSK 0x00003fff
170#define HPC3_ETXBCD_ESAMP 0x10000000
171#define HPC3_ETXBCD_XIE 0x20000000
172#define HPC3_ETXBCD_EOP 0x40000000
173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
174#define HPC3_ETXBCD_EOX 0x80000000
175 volatile u32 tx_ctrl;
176#define HPC3_ETXCTRL_STAT30 0x0000000f
177#define HPC3_ETXCTRL_STAT4 0x00000010
178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
179#define HPC3_ETXCTRL_STAT75 0x000000e0
180#define HPC3_ETXCTRL_ENDIAN 0x00000100
181#define HPC3_ETXCTRL_ACTIVE 0x00000200
182#define HPC3_ETXCTRL_AMASK 0x00000400
183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
184 volatile u32 tx_gfptr;
185 volatile u32 tx_dfptr;
186 u32 _unused4[0x1000/4 - 4];
187};
188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189struct hpc3_regs {
190 struct hpc3_pbus_dmacregs pbdma[8];
191 struct hpc3_scsiregs scsi_chan0, scsi_chan1;
192 struct hpc3_ethregs ethregs;
193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194 u32 _unused0[0x18000/4];
195 volatile u32 istat0;
196#define HPC3_ISTAT_PBIMASK 0x0ff
197#define HPC3_ISTAT_SC0MASK 0x100
198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
199#define HPC3_ISTAT_SC1MASK 0x200
200 volatile u32 gio_misc;
201#define HPC3_GIOMISC_ERTIME 0x1
202#define HPC3_GIOMISC_DENDIAN 0x2
203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
204 u32 eeprom;
205#define HPC3_EEPROM_EPROT 0x01
206#define HPC3_EEPROM_CSEL 0x02
207#define HPC3_EEPROM_ECLK 0x04
208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
209#define HPC3_EEPROM_DATO 0x08
210#define HPC3_EEPROM_DATI 0x10
211 volatile u32 istat1;
212 volatile u32 bestat;
213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
214#define HPC3_BESTAT_BLMASK 0x000ff
215#define HPC3_BESTAT_CTYPE 0x00100
216#define HPC3_BESTAT_PIDSHIFT 9
217#define HPC3_BESTAT_PIDMASK 0x3f700
218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
219 u32 _unused1[0x14000/4 - 5];
220 volatile u32 scsi0_ext[256];
221 u32 _unused2[0x7c00/4];
222 volatile u32 scsi1_ext[256];
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
224 u32 _unused3[0x7c00/4];
225 volatile u32 eth_ext[320];
226 u32 _unused4[0x3b00/4];
227 volatile u32 pbus_extregs[16][256];
228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
229 volatile u32 pbus_dmacfg[8][128];
230#define HPC3_DMACFG_D3R_MASK 0x00000001
231#define HPC3_DMACFG_D3R_SHIFT 0
232#define HPC3_DMACFG_D4R_MASK 0x0000001e
233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
234#define HPC3_DMACFG_D4R_SHIFT 1
235#define HPC3_DMACFG_D5R_MASK 0x000001e0
236#define HPC3_DMACFG_D5R_SHIFT 5
237#define HPC3_DMACFG_D3W_MASK 0x00000200
238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
239#define HPC3_DMACFG_D3W_SHIFT 9
240#define HPC3_DMACFG_D4W_MASK 0x00003c00
241#define HPC3_DMACFG_D4W_SHIFT 10
242#define HPC3_DMACFG_D5W_MASK 0x0003c000
243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
244#define HPC3_DMACFG_D5W_SHIFT 14
245#define HPC3_DMACFG_DS16 0x00040000
246#define HPC3_DMACFG_EVENHI 0x00080000
247#define HPC3_DMACFG_RTIME 0x00200000
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
249#define HPC3_DMACFG_BURST_MASK 0x07c00000
250#define HPC3_DMACFG_BURST_SHIFT 22
251#define HPC3_DMACFG_DRQLIVE 0x08000000
252 volatile u32 pbus_piocfg[16][64];
253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
254#define HPC3_PIOCFG_P2R_MASK 0x00001
255#define HPC3_PIOCFG_P2R_SHIFT 0
256#define HPC3_PIOCFG_P3R_MASK 0x0001e
257#define HPC3_PIOCFG_P3R_SHIFT 1
258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
259#define HPC3_PIOCFG_P4R_MASK 0x001e0
260#define HPC3_PIOCFG_P4R_SHIFT 5
261#define HPC3_PIOCFG_P2W_MASK 0x00200
262#define HPC3_PIOCFG_P2W_SHIFT 9
263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
264#define HPC3_PIOCFG_P3W_MASK 0x03c00
265#define HPC3_PIOCFG_P3W_SHIFT 10
266#define HPC3_PIOCFG_P4W_MASK 0x3c000
267#define HPC3_PIOCFG_P4W_SHIFT 14
268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
269#define HPC3_PIOCFG_DS16 0x40000
270#define HPC3_PIOCFG_EVENHI 0x80000
271 volatile u32 pbus_promwe;
272#define HPC3_PROM_WENAB 0x1
273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
274 u32 _unused5[0x0800/4 - 1];
275 volatile u32 pbus_promswap;
276#define HPC3_PROM_SWAP 0x1
277 u32 _unused6[0x0800/4 - 1];
278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
279 volatile u32 pbus_gout;
280#define HPC3_PROM_STAT 0x1
281 u32 _unused7[0x1000/4 - 1];
282 volatile u32 rtcregs[14];
283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
284 u32 _unused8[50];
285 volatile u32 bbram[8192-50-14];
286};
287#define HPC3_CHIP0_BASE 0x1fb80000
288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
289#define HPC3_CHIP1_BASE 0x1fb00000
290#endif
291