1    /*
2     * This handler is a bit odd - it may be called via chaining or
3     * from static code and is expected to cause control to flow
4     * to the interpreter.  The problem is where to find the Dalvik
5     * PC of the next instruction.  When called via chaining, the dPC
6     * will be located at *rp.  When called from static code, rPC is
7     * valid and rp is a real return pointer (that should be ignored).
8     * The Arm target deals with this by using the link register as
9     * a flag.  If it is zero, we know we were called from static code.
10     * If non-zero, it points to the chain cell containing dPC.
11     * For x86, we'll infer the source by looking where rp points.
12     * If it points to anywhere within the code cache, we'll assume
13     * we got here via chaining.  Otherwise, we'll assume rPC is valid.
14     *
15     * On entry:
16     *    (TOS)<- return pointer or pointer to dPC
17     */
18
19/*
20 * FIXME - this won't work as-is.  The cache boundaries are not
21 * set up until later.  Perhaps rething this whole thing.  Do we
22 * really need an interpret teplate?
23 */
24
25
26     movl   rSELF,%ecx
27     movl   $$.LinterpPunt,%edx
28     pop    %eax
29     /*cmpl   %eax,offThread_jitCacheEnd(%ecx)*/
30     ja     1f
31     /*cmpl   %eax,offThread_jitCacheStart(%ecx)*/
32     jb     1f
33     movl   %eax,rPC
341:
35     jmp    *(%edx)
36
37.LinterpPunt:
38    .long   dvmJitToInterpPunt
39