1%default {"preinstr":""}
2    /*
3     * Generic 32-bit unary operation.  Provide an "instr" line that
4     * specifies an instruction that performs "result = op r0".
5     * This could be an ARM instruction or a function call.
6     *
7     * for: neg-int, not-int, neg-float, int-to-float, float-to-int,
8     *      int-to-byte, int-to-char, int-to-short
9     */
10    /* unop vA, vB */
11    mov     r3, rINST, lsr #12          @ r3<- B
12    ubfx    r9, rINST, #8, #4           @ r9<- A
13    GET_VREG(r0, r3)                    @ r0<- vB
14    $preinstr                           @ optional op; may set condition codes
15    FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
16    $instr                              @ r0<- op, r0-r3 changed
17    GET_INST_OPCODE(ip)                 @ extract opcode from rINST
18    SET_VREG(r0, r9)                    @ vAA<- r0
19    GOTO_OPCODE(ip)                     @ jump to next instruction
20    /* 8-9 instructions */
21