1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from 9 * this software without specific prior written permission 10 * 11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 * 22 October 2, 1994 23 24 Modified by: Andres Vega Garcia 25 26 INRIA - Sophia Antipolis, France 27 e-mail: avega@sophia.inria.fr 28 finger: avega@pax.inria.fr 29 30 */ 31 32/* 33 * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the 34 * 3c590 family. 35 */ 36 37/* 38 * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> 39 * for etherboot 40 * Mar. 14, 2000 41*/ 42 43/* 44 * Ethernet software status per interface. 45 */ 46 47/* 48 * Some global constants 49 */ 50 51#define TX_INIT_RATE 16 52#define TX_INIT_MAX_RATE 64 53#define RX_INIT_LATENCY 64 54#define RX_INIT_EARLY_THRESH 64 55#define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ 56#define MIN_RX_EARLY_THRESHL 4 57 58#define EEPROMSIZE 0x40 59#define MAX_EEPROMBUSY 1000 60#define VX_LAST_TAG 0xd7 61#define VX_MAX_BOARDS 16 62#define VX_ID_PORT 0x100 63 64/* 65 * some macros to acces long named fields 66 */ 67#define BASE (eth_nic_base) 68 69/* 70 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 71 * Offset 0xa) 72 */ 73#define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ 74#define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ 75#define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ 76#define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ 77 78#define EEPROM_BUSY (1<<15) 79 80/* 81 * Some short functions, worth to let them be a macro 82 */ 83 84/************************************************************************** 85 * * 86 * These define the EEPROM data structure. They are used in the probe 87 * function to verify the existence of the adapter after having sent 88 * the ID_Sequence. 89 * 90 * There are others but only the ones we use are defined here. 91 * 92 **************************************************************************/ 93 94#define EEPROM_NODE_ADDR_0 0x0 /* Word */ 95#define EEPROM_NODE_ADDR_1 0x1 /* Word */ 96#define EEPROM_NODE_ADDR_2 0x2 /* Word */ 97#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ 98#define EEPROM_MFG_ID 0x7 /* 0x6d50 */ 99#define EEPROM_ADDR_CFG 0x8 /* Base addr */ 100#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ 101#define EEPROM_OEM_ADDR_0 0xa /* Word */ 102#define EEPROM_OEM_ADDR_1 0xb /* Word */ 103#define EEPROM_OEM_ADDR_2 0xc /* Word */ 104#define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ 105 106#define NO_RX_OVN_ANOMALY (1<<5) 107 108/************************************************************************** 109 * * 110 * These are the registers for the 3Com 3c509 and their bit patterns when * 111 * applicable. They have been taken out the the "EtherLink III Parallel * 112 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * 113 * from 3com. * 114 * * 115 **************************************************************************/ 116 117#define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a 118 * command reg. */ 119#define VX_STATUS 0x0e /* Read. BASE+0x0e is always status 120 * reg. */ 121#define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window 122 * reg. */ 123/* 124 * Window 0 registers. Setup. 125 */ 126/* Write */ 127#define VX_W0_EEPROM_DATA 0x0c 128#define VX_W0_EEPROM_COMMAND 0x0a 129#define VX_W0_RESOURCE_CFG 0x08 130#define VX_W0_ADDRESS_CFG 0x06 131#define VX_W0_CONFIG_CTRL 0x04 132 /* Read */ 133#define VX_W0_PRODUCT_ID 0x02 134#define VX_W0_MFG_ID 0x00 135 136 137/* 138 * Window 1 registers. Operating Set. 139 */ 140/* Write */ 141#define VX_W1_TX_PIO_WR_2 0x02 142#define VX_W1_TX_PIO_WR_1 0x00 143/* Read */ 144#define VX_W1_FREE_TX 0x0c 145#define VX_W1_TX_STATUS 0x0b /* byte */ 146#define VX_W1_TIMER 0x0a /* byte */ 147#define VX_W1_RX_STATUS 0x08 148#define VX_W1_RX_PIO_RD_2 0x02 149#define VX_W1_RX_PIO_RD_1 0x00 150 151/* 152 * Window 2 registers. Station Address Setup/Read 153 */ 154/* Read/Write */ 155#define VX_W2_ADDR_5 0x05 156#define VX_W2_ADDR_4 0x04 157#define VX_W2_ADDR_3 0x03 158#define VX_W2_ADDR_2 0x02 159#define VX_W2_ADDR_1 0x01 160#define VX_W2_ADDR_0 0x00 161 162/* 163 * Window 3 registers. FIFO Management. 164 */ 165/* Read */ 166#define VX_W3_INTERNAL_CFG 0x00 167#define VX_W3_RESET_OPT 0x08 168#define VX_W3_FREE_TX 0x0c 169#define VX_W3_FREE_RX 0x0a 170 171/* 172 * Window 4 registers. Diagnostics. 173 */ 174/* Read/Write */ 175#define VX_W4_MEDIA_TYPE 0x0a 176#define VX_W4_CTRLR_STATUS 0x08 177#define VX_W4_NET_DIAG 0x06 178#define VX_W4_FIFO_DIAG 0x04 179#define VX_W4_HOST_DIAG 0x02 180#define VX_W4_TX_DIAG 0x00 181 182/* 183 * Window 5 Registers. Results and Internal status. 184 */ 185/* Read */ 186#define VX_W5_READ_0_MASK 0x0c 187#define VX_W5_INTR_MASK 0x0a 188#define VX_W5_RX_FILTER 0x08 189#define VX_W5_RX_EARLY_THRESH 0x06 190#define VX_W5_TX_AVAIL_THRESH 0x02 191#define VX_W5_TX_START_THRESH 0x00 192 193/* 194 * Window 6 registers. Statistics. 195 */ 196/* Read/Write */ 197#define TX_TOTAL_OK 0x0c 198#define RX_TOTAL_OK 0x0a 199#define TX_DEFERRALS 0x08 200#define RX_FRAMES_OK 0x07 201#define TX_FRAMES_OK 0x06 202#define RX_OVERRUNS 0x05 203#define TX_COLLISIONS 0x04 204#define TX_AFTER_1_COLLISION 0x03 205#define TX_AFTER_X_COLLISIONS 0x02 206#define TX_NO_SQE 0x01 207#define TX_CD_LOST 0x00 208 209/**************************************** 210 * 211 * Register definitions. 212 * 213 ****************************************/ 214 215/* 216 * Command register. All windows. 217 * 218 * 16 bit register. 219 * 15-11: 5-bit code for command to be executed. 220 * 10-0: 11-bit arg if any. For commands with no args; 221 * this can be set to anything. 222 */ 223#define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms 224 * after issuing */ 225#define WINDOW_SELECT (unsigned short) (0x1<<11) 226#define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to 227 * determine whether 228 * this is needed. If 229 * so; wait 800 uSec 230 * before using trans- 231 * ceiver. */ 232#define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on 233 * power-up */ 234#define RX_ENABLE (unsigned short) (0x4<<11) 235#define RX_RESET (unsigned short) (0x5<<11) 236#define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) 237#define TX_ENABLE (unsigned short) (0x9<<11) 238#define TX_DISABLE (unsigned short) (0xa<<11) 239#define TX_RESET (unsigned short) (0xb<<11) 240#define REQ_INTR (unsigned short) (0xc<<11) 241/* 242 * The following C_* acknowledge the various interrupts. Some of them don't 243 * do anything. See the manual. 244 */ 245#define ACK_INTR (unsigned short) (0x6800) 246# define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) 247# define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) 248# define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) 249# define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) 250# define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) 251# define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) 252# define C_INT_RQD (unsigned short) (ACK_INTR|0x40) 253# define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) 254#define SET_INTR_MASK (unsigned short) (0xe<<11) 255#define SET_RD_0_MASK (unsigned short) (0xf<<11) 256#define SET_RX_FILTER (unsigned short) (0x10<<11) 257# define FIL_INDIVIDUAL (unsigned short) (0x1) 258# define FIL_MULTICAST (unsigned short) (0x02) 259# define FIL_BRDCST (unsigned short) (0x04) 260# define FIL_PROMISC (unsigned short) (0x08) 261#define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) 262#define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) 263#define SET_TX_START_THRESH (unsigned short) (0x13<<11) 264#define STATS_ENABLE (unsigned short) (0x15<<11) 265#define STATS_DISABLE (unsigned short) (0x16<<11) 266#define STOP_TRANSCEIVER (unsigned short) (0x17<<11) 267 268/* 269 * Status register. All windows. 270 * 271 * 15-13: Window number(0-7). 272 * 12: Command_in_progress. 273 * 11: reserved. 274 * 10: reserved. 275 * 9: reserved. 276 * 8: reserved. 277 * 7: Update Statistics. 278 * 6: Interrupt Requested. 279 * 5: RX Early. 280 * 4: RX Complete. 281 * 3: TX Available. 282 * 2: TX Complete. 283 * 1: Adapter Failure. 284 * 0: Interrupt Latch. 285 */ 286#define S_INTR_LATCH (unsigned short) (0x1) 287#define S_CARD_FAILURE (unsigned short) (0x2) 288#define S_TX_COMPLETE (unsigned short) (0x4) 289#define S_TX_AVAIL (unsigned short) (0x8) 290#define S_RX_COMPLETE (unsigned short) (0x10) 291#define S_RX_EARLY (unsigned short) (0x20) 292#define S_INT_RQD (unsigned short) (0x40) 293#define S_UPD_STATS (unsigned short) (0x80) 294#define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) 295 296#define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) 297 298/* Address Config. Register. 299 * Window 0/Port 06 300 */ 301 302#define ACF_CONNECTOR_BITS 14 303#define ACF_CONNECTOR_UTP 0 304#define ACF_CONNECTOR_AUI 1 305#define ACF_CONNECTOR_BNC 3 306 307#define INTERNAL_CONNECTOR_BITS 20 308#define INTERNAL_CONNECTOR_MASK 0x01700000 309 310/* 311 * FIFO Registers. RX Status. 312 * 313 * 15: Incomplete or FIFO empty. 314 * 14: 1: Error in RX Packet 0: Incomplete or no error. 315 * 13-11: Type of error. 316 * 1000 = Overrun. 317 * 1011 = Run Packet Error. 318 * 1100 = Alignment Error. 319 * 1101 = CRC Error. 320 * 1001 = Oversize Packet Error (>1514 bytes) 321 * 0010 = Dribble Bits. 322 * (all other error codes, no errors.) 323 * 324 * 10-0: RX Bytes (0-1514) 325 */ 326#define ERR_INCOMPLETE (unsigned short) (0x8000) 327#define ERR_RX (unsigned short) (0x4000) 328#define ERR_MASK (unsigned short) (0x7800) 329#define ERR_OVERRUN (unsigned short) (0x4000) 330#define ERR_RUNT (unsigned short) (0x5800) 331#define ERR_ALIGNMENT (unsigned short) (0x6000) 332#define ERR_CRC (unsigned short) (0x6800) 333#define ERR_OVERSIZE (unsigned short) (0x4800) 334#define ERR_DRIBBLE (unsigned short) (0x1000) 335 336/* 337 * TX Status. 338 * 339 * Reports the transmit status of a completed transmission. Writing this 340 * register pops the transmit completion stack. 341 * 342 * Window 1/Port 0x0b. 343 * 344 * 7: Complete 345 * 6: Interrupt on successful transmission requested. 346 * 5: Jabber Error (TP Only, TX Reset required. ) 347 * 4: Underrun (TX Reset required. ) 348 * 3: Maximum Collisions. 349 * 2: TX Status Overflow. 350 * 1-0: Undefined. 351 * 352 */ 353#define TXS_COMPLETE 0x80 354#define TXS_INTR_REQ 0x40 355#define TXS_JABBER 0x20 356#define TXS_UNDERRUN 0x10 357#define TXS_MAX_COLLISION 0x8 358#define TXS_STATUS_OVERFLOW 0x4 359 360#define RS_AUI (1<<5) 361#define RS_BNC (1<<4) 362#define RS_UTP (1<<3) 363#define RS_T4 (1<<0) 364#define RS_TX (1<<1) 365#define RS_FX (1<<2) 366#define RS_MII (1<<6) 367 368 369/* 370 * FIFO Status (Window 4) 371 * 372 * Supports FIFO diagnostics 373 * 374 * Window 4/Port 0x04.1 375 * 376 * 15: 1=RX receiving (RO). Set when a packet is being received 377 * into the RX FIFO. 378 * 14: Reserved 379 * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. 380 * Requires RX Reset or Global Reset command to recover. 381 * It is generated when you read past the end of a packet - 382 * reading past what has been received so far will give bad 383 * data. 384 * 12: 1=RX status overrun (RO). Set when there are already 8 385 * packets in the RX FIFO. While this bit is set, no additional 386 * packets are received. Requires no action on the part of 387 * the host. The condition is cleared once a packet has been 388 * read out of the RX FIFO. 389 * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there 390 * may not be an overrun packet yet). While this bit is set, 391 * no additional packets will be received (some additional 392 * bytes can still be pending between the wire and the RX 393 * FIFO). Requires no action on the part of the host. The 394 * condition is cleared once a few bytes have been read out 395 * from the RX FIFO. 396 * 10: 1=TX overrun (RO). Generates adapter failure interrupt. 397 * Requires TX Reset or Global Reset command to recover. 398 * Disables Transmitter. 399 * 9-8: Unassigned. 400 * 7-0: Built in self test bits for the RX and TX FIFO's. 401 */ 402#define FIFOS_RX_RECEIVING (unsigned short) 0x8000 403#define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 404#define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 405#define FIFOS_RX_OVERRUN (unsigned short) 0x0800 406#define FIFOS_TX_OVERRUN (unsigned short) 0x0400 407 408/* 409 * Misc defines for various things. 410 */ 411#define TAG_ADAPTER 0xd0 412#define ACTIVATE_ADAPTER_TO_CONFIG 0xff 413#define ENABLE_DRQ_IRQ 0x0001 414#define MFG_ID 0x506d /* `TCM' */ 415#define PROD_ID 0x5090 416#define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) 417#define JABBER_GUARD_ENABLE 0x40 418#define LINKBEAT_ENABLE 0x80 419#define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 420#define DISABLE_UTP 0x0 421#define RX_BYTES_MASK (unsigned short) (0x07ff) 422#define RX_ERROR 0x4000 423#define RX_INCOMPLETE 0x8000 424#define TX_INDICATE 1<<15 425#define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) 426 427#define VX_IOSIZE 0x20 428 429#define VX_CONNECTORS 8 430 431/* 432 * Local variables: 433 * c-basic-offset: 8 434 * End: 435 */ 436