LiveRangeEdit.h revision 789d5d85ba6e9259a8e0f0bcfbd06a59ad164512 
1//===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The LiveRangeEdit class represents changes done to a virtual register when it
11// is spilled or split.
12//
13// The parent register is never changed. Instead, a number of new virtual
14// registers are created and added to the newRegs vector.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
19#define LLVM_CODEGEN_LIVERANGEEDIT_H
20
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/CodeGen/LiveInterval.h"
24#include "llvm/Target/TargetMachine.h"
25
26namespace llvm {
27
28class AliasAnalysis;
29class LiveIntervals;
30class MachineLoopInfo;
31class MachineRegisterInfo;
32class VirtRegMap;
33
34class LiveRangeEdit {
35public:
36  /// Callback methods for LiveRangeEdit owners.
37  class Delegate {
38    virtual void anchor();
39  public:
40    /// Called immediately before erasing a dead machine instruction.
41    virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
42
43    /// Called when a virtual register is no longer used. Return false to defer
44    /// its deletion from LiveIntervals.
45    virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
46
47    /// Called before shrinking the live range of a virtual register.
48    virtual void LRE_WillShrinkVirtReg(unsigned) {}
49
50    /// Called after cloning a virtual register.
51    /// This is used for new registers representing connected components of Old.
52    virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
53
54    virtual ~Delegate() {}
55  };
56
57private:
58  LiveInterval &parent_;
59  SmallVectorImpl<LiveInterval*> &newRegs_;
60  MachineRegisterInfo &MRI;
61  LiveIntervals &LIS;
62  VirtRegMap *VRM;
63  const TargetInstrInfo &TII;
64  Delegate *const delegate_;
65
66  /// firstNew_ - Index of the first register added to newRegs_.
67  const unsigned firstNew_;
68
69  /// scannedRemattable_ - true when remattable values have been identified.
70  bool scannedRemattable_;
71
72  /// remattable_ - Values defined by remattable instructions as identified by
73  /// tii.isTriviallyReMaterializable().
74  SmallPtrSet<const VNInfo*,4> remattable_;
75
76  /// rematted_ - Values that were actually rematted, and so need to have their
77  /// live range trimmed or entirely removed.
78  SmallPtrSet<const VNInfo*,4> rematted_;
79
80  /// scanRemattable - Identify the parent_ values that may rematerialize.
81  void scanRemattable(AliasAnalysis *aa);
82
83  /// allUsesAvailableAt - Return true if all registers used by OrigMI at
84  /// OrigIdx are also available with the same value at UseIdx.
85  bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
86                          SlotIndex UseIdx);
87
88  /// foldAsLoad - If LI has a single use and a single def that can be folded as
89  /// a load, eliminate the register by folding the def into the use.
90  bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
91
92public:
93  /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
94  /// @param parent The register being spilled or split.
95  /// @param newRegs List to receive any new registers created. This needn't be
96  ///                empty initially, any existing registers are ignored.
97  LiveRangeEdit(LiveInterval &parent,
98                SmallVectorImpl<LiveInterval*> &newRegs,
99                MachineFunction &MF,
100                LiveIntervals &lis,
101                VirtRegMap *vrm,
102                Delegate *delegate = 0)
103    : parent_(parent), newRegs_(newRegs),
104      MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
105      TII(*MF.getTarget().getInstrInfo()),
106      delegate_(delegate),
107      firstNew_(newRegs.size()),
108      scannedRemattable_(false) {}
109
110  LiveInterval &getParent() const { return parent_; }
111  unsigned getReg() const { return parent_.reg; }
112
113  /// Iterator for accessing the new registers added by this edit.
114  typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
115  iterator begin() const { return newRegs_.begin()+firstNew_; }
116  iterator end() const { return newRegs_.end(); }
117  unsigned size() const { return newRegs_.size()-firstNew_; }
118  bool empty() const { return size() == 0; }
119  LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
120
121  ArrayRef<LiveInterval*> regs() const {
122    return makeArrayRef(newRegs_).slice(firstNew_);
123  }
124
125  /// createFrom - Create a new virtual register based on OldReg.
126  LiveInterval &createFrom(unsigned OldReg);
127
128  /// create - Create a new register with the same class and original slot as
129  /// parent.
130  LiveInterval &create() {
131    return createFrom(getReg());
132  }
133
134  /// anyRematerializable - Return true if any parent values may be
135  /// rematerializable.
136  /// This function must be called before any rematerialization is attempted.
137  bool anyRematerializable(AliasAnalysis*);
138
139  /// checkRematerializable - Manually add VNI to the list of rematerializable
140  /// values if DefMI may be rematerializable.
141  bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
142                             AliasAnalysis*);
143
144  /// Remat - Information needed to rematerialize at a specific location.
145  struct Remat {
146    VNInfo *ParentVNI;      // parent_'s value at the remat location.
147    MachineInstr *OrigMI;   // Instruction defining ParentVNI.
148    explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
149  };
150
151  /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
152  /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
153  /// When cheapAsAMove is set, only cheap remats are allowed.
154  bool canRematerializeAt(Remat &RM,
155                          SlotIndex UseIdx,
156                          bool cheapAsAMove);
157
158  /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
159  /// instruction into MBB before MI. The new instruction is mapped, but
160  /// liveness is not updated.
161  /// Return the SlotIndex of the new instruction.
162  SlotIndex rematerializeAt(MachineBasicBlock &MBB,
163                            MachineBasicBlock::iterator MI,
164                            unsigned DestReg,
165                            const Remat &RM,
166                            const TargetRegisterInfo&,
167                            bool Late = false);
168
169  /// markRematerialized - explicitly mark a value as rematerialized after doing
170  /// it manually.
171  void markRematerialized(const VNInfo *ParentVNI) {
172    rematted_.insert(ParentVNI);
173  }
174
175  /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
176  bool didRematerialize(const VNInfo *ParentVNI) const {
177    return rematted_.count(ParentVNI);
178  }
179
180  /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
181  /// to erase it from LIS.
182  void eraseVirtReg(unsigned Reg);
183
184  /// eliminateDeadDefs - Try to delete machine instructions that are now dead
185  /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
186  /// and further dead efs to be eliminated.
187  /// RegsBeingSpilled lists registers currently being spilled by the register
188  /// allocator.  These registers should not be split into new intervals
189  /// as currently those new intervals are not guaranteed to spill.
190  void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
191                         ArrayRef<unsigned> RegsBeingSpilled
192                          = ArrayRef<unsigned>());
193
194  /// calculateRegClassAndHint - Recompute register class and hint for each new
195  /// register.
196  void calculateRegClassAndHint(MachineFunction&,
197                                const MachineLoopInfo&);
198};
199
200}
201
202#endif
203