ScheduleDAG.h revision 3f23744df4809eba94284e601e81489212c974d4
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 struct SUnit; 27 class MachineConstantPool; 28 class MachineFunction; 29 class MachineModuleInfo; 30 class MachineRegisterInfo; 31 class MachineInstr; 32 class TargetRegisterInfo; 33 class ScheduleDAG; 34 class SelectionDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 template<class Graph> class GraphWriter; 42 43 /// SDep - Scheduling dependency. This represents one direction of an 44 /// edge in the scheduling DAG. 45 class SDep { 46 public: 47 /// Kind - These are the different kinds of scheduling dependencies. 48 enum Kind { 49 Data, ///< Regular data dependence (aka true-dependence). 50 Anti, ///< A register anti-dependedence (aka WAR). 51 Output, ///< A register output-dependence (aka WAW). 52 Order ///< Any other ordering dependency. 53 }; 54 55 private: 56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 57 /// indicating the kind of the dependency. 58 PointerIntPair<SUnit *, 2, Kind> Dep; 59 60 /// Contents - A union discriminated by the dependence kind. 61 union { 62 /// Reg - For Data, Anti, and Output dependencies, the associated 63 /// register. For Data dependencies that don't currently have a register 64 /// assigned, this is set to zero. 65 unsigned Reg; 66 67 /// Order - Additional information about Order dependencies. 68 struct { 69 /// isNormalMemory - True if both sides of the dependence 70 /// access memory in non-volatile and fully modeled ways. 71 bool isNormalMemory : 1; 72 73 /// isMustAlias - True if both sides of the dependence are known to 74 /// access the same memory. 75 bool isMustAlias : 1; 76 77 /// isArtificial - True if this is an artificial dependency, meaning 78 /// it is not necessary for program correctness, and may be safely 79 /// deleted if necessary. 80 bool isArtificial : 1; 81 } Order; 82 } Contents; 83 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 86 /// models may provide additional information about specific edges. 87 unsigned Latency; 88 89 public: 90 /// SDep - Construct a null SDep. This is only for use by container 91 /// classes which require default constructors. SUnits may not 92 /// have null SDep edges. 93 SDep() : Dep(0, Data) {} 94 95 /// SDep - Construct an SDep with the specified values. 96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 97 bool isNormalMemory = false, bool isMustAlias = false, 98 bool isArtificial = false) 99 : Dep(S, kind), Contents(), Latency(latency) { 100 switch (kind) { 101 case Anti: 102 case Output: 103 assert(Reg != 0 && 104 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 105 // fall through 106 case Data: 107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 108 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 109 Contents.Reg = Reg; 110 break; 111 case Order: 112 assert(Reg == 0 && "Reg given for non-register dependence!"); 113 Contents.Order.isNormalMemory = isNormalMemory; 114 Contents.Order.isMustAlias = isMustAlias; 115 Contents.Order.isArtificial = isArtificial; 116 break; 117 } 118 } 119 120 bool operator==(const SDep &Other) const { 121 if (Dep != Other.Dep || Latency != Other.Latency) return false; 122 switch (Dep.getInt()) { 123 case Data: 124 case Anti: 125 case Output: 126 return Contents.Reg == Other.Contents.Reg; 127 case Order: 128 return Contents.Order.isNormalMemory == 129 Other.Contents.Order.isNormalMemory && 130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 132 } 133 assert(0 && "Invalid dependency kind!"); 134 return false; 135 } 136 137 bool operator!=(const SDep &Other) const { 138 return !operator==(Other); 139 } 140 141 /// getLatency - Return the latency value for this edge, which roughly 142 /// means the minimum number of cycles that must elapse between the 143 /// predecessor and the successor, given that they have this edge 144 /// between them. 145 unsigned getLatency() const { 146 return Latency; 147 } 148 149 //// getSUnit - Return the SUnit to which this edge points. 150 SUnit *getSUnit() const { 151 return Dep.getPointer(); 152 } 153 154 //// setSUnit - Assign the SUnit to which this edge points. 155 void setSUnit(SUnit *SU) { 156 Dep.setPointer(SU); 157 } 158 159 /// getKind - Return an enum value representing the kind of the dependence. 160 Kind getKind() const { 161 return Dep.getInt(); 162 } 163 164 /// isCtrl - Shorthand for getKind() != SDep::Data. 165 bool isCtrl() const { 166 return getKind() != Data; 167 } 168 169 /// isMustAlias - Test if this is an Order dependence that is marked 170 /// as "must alias", meaning that the SUnits at either end of the edge 171 /// have a memory dependence on a known memory location. 172 bool isMustAlias() const { 173 return getKind() == Order && Contents.Order.isMustAlias; 174 } 175 176 /// isArtificial - Test if this is an Order dependence that is marked 177 /// as "artificial", meaning it isn't necessary for correctness. 178 bool isArtificial() const { 179 return getKind() == Order && Contents.Order.isArtificial; 180 } 181 182 /// isAssignedRegDep - Test if this is a Data dependence that is 183 /// associated with a register. 184 bool isAssignedRegDep() const { 185 return getKind() == Data && Contents.Reg != 0; 186 } 187 188 /// getReg - Return the register associated with this edge. This is 189 /// only valid on Data, Anti, and Output edges. On Data edges, this 190 /// value may be zero, meaning there is no associated register. 191 unsigned getReg() const { 192 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 193 "getReg called on non-register dependence edge!"); 194 return Contents.Reg; 195 } 196 197 /// setReg - Assign the associated register for this edge. This is 198 /// only valid on Data, Anti, and Output edges. On Anti and Output 199 /// edges, this value must not be zero. On Data edges, the value may 200 /// be zero, which would mean that no specific register is associated 201 /// with this edge. 202 void setReg(unsigned Reg) { 203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 204 "setReg called on non-register dependence edge!"); 205 assert((getKind() != Anti || Reg != 0) && 206 "SDep::Anti edge cannot use the zero register!"); 207 assert((getKind() != Output || Reg != 0) && 208 "SDep::Output edge cannot use the zero register!"); 209 Contents.Reg = Reg; 210 } 211 }; 212 213 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 214 struct SUnit { 215 private: 216 SDNode *Node; // Representative node. 217 MachineInstr *Instr; // Alternatively, a MachineInstr. 218 public: 219 SUnit *OrigNode; // If not this, the node from which 220 // this node was cloned. 221 222 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 223 // is true if the edge is a token chain edge, false if it is a value edge. 224 SmallVector<SDep, 4> Preds; // All sunit predecessors. 225 SmallVector<SDep, 4> Succs; // All sunit successors. 226 227 typedef SmallVector<SDep, 4>::iterator pred_iterator; 228 typedef SmallVector<SDep, 4>::iterator succ_iterator; 229 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 230 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 231 232 unsigned NodeNum; // Entry # of node in the node vector. 233 unsigned NodeQueueId; // Queue id of node. 234 unsigned short Latency; // Node latency. 235 short NumPreds; // # of SDep::Data preds. 236 short NumSuccs; // # of SDep::Data sucss. 237 short NumPredsLeft; // # of preds not scheduled. 238 short NumSuccsLeft; // # of succs not scheduled. 239 bool isTwoAddress : 1; // Is a two-address instruction. 240 bool isCommutable : 1; // Is a commutable instruction. 241 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 242 bool isPending : 1; // True once pending. 243 bool isAvailable : 1; // True once available. 244 bool isScheduled : 1; // True once scheduled. 245 private: 246 bool isDepthCurrent : 1; // True if Depth is current. 247 bool isHeightCurrent : 1; // True if Height is current. 248 unsigned Depth; // Node depth. 249 unsigned Height; // Node height. 250 public: 251 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 252 const TargetRegisterClass *CopySrcRC; 253 254 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 255 /// an SDNode and any nodes flagged to it. 256 SUnit(SDNode *node, unsigned nodenum) 257 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 258 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 259 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 260 isPending(false), isAvailable(false), isScheduled(false), 261 isDepthCurrent(false), isHeightCurrent(false), 262 Depth(0), Height(0), 263 CopyDstRC(NULL), CopySrcRC(NULL) {} 264 265 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 266 /// a MachineInstr. 267 SUnit(MachineInstr *instr, unsigned nodenum) 268 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 269 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 270 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 271 isPending(false), isAvailable(false), isScheduled(false), 272 isDepthCurrent(false), isHeightCurrent(false), 273 Depth(0), Height(0), 274 CopyDstRC(NULL), CopySrcRC(NULL) {} 275 276 /// setNode - Assign the representative SDNode for this SUnit. 277 /// This may be used during pre-regalloc scheduling. 278 void setNode(SDNode *N) { 279 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 280 Node = N; 281 } 282 283 /// getNode - Return the representative SDNode for this SUnit. 284 /// This may be used during pre-regalloc scheduling. 285 SDNode *getNode() const { 286 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 287 return Node; 288 } 289 290 /// setInstr - Assign the instruction for the SUnit. 291 /// This may be used during post-regalloc scheduling. 292 void setInstr(MachineInstr *MI) { 293 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 294 Instr = MI; 295 } 296 297 /// getInstr - Return the representative MachineInstr for this SUnit. 298 /// This may be used during post-regalloc scheduling. 299 MachineInstr *getInstr() const { 300 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 301 return Instr; 302 } 303 304 /// addPred - This adds the specified edge as a pred of the current node if 305 /// not already. It also adds the current node as a successor of the 306 /// specified node. 307 void addPred(const SDep &D); 308 309 /// removePred - This removes the specified edge as a pred of the current 310 /// node if it exists. It also removes the current node as a successor of 311 /// the specified node. 312 void removePred(const SDep &D); 313 314 /// getHeight - Return the height of this node, which is the length of the 315 /// maximum path down to any node with has no successors. 316 unsigned getDepth() const { 317 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth(); 318 return Depth; 319 } 320 321 /// getHeight - Return the height of this node, which is the length of the 322 /// maximum path up to any node with has no predecessors. 323 unsigned getHeight() const { 324 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight(); 325 return Height; 326 } 327 328 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 329 /// value, set it to be the new depth value. This also recursively 330 /// marks successor nodes dirty. 331 void setDepthToAtLeast(unsigned NewDepth); 332 333 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 334 /// value, set it to be the new height value. This also recursively 335 /// marks predecessor nodes dirty. 336 void setHeightToAtLeast(unsigned NewHeight); 337 338 /// setDepthDirty - Set a flag in this node to indicate that its 339 /// stored Depth value will require recomputation the next time 340 /// getDepth() is called. 341 void setDepthDirty(); 342 343 /// setHeightDirty - Set a flag in this node to indicate that its 344 /// stored Height value will require recomputation the next time 345 /// getHeight() is called. 346 void setHeightDirty(); 347 348 /// isPred - Test if node N is a predecessor of this node. 349 bool isPred(SUnit *N) { 350 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 351 if (Preds[i].getSUnit() == N) 352 return true; 353 return false; 354 } 355 356 /// isSucc - Test if node N is a successor of this node. 357 bool isSucc(SUnit *N) { 358 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 359 if (Succs[i].getSUnit() == N) 360 return true; 361 return false; 362 } 363 364 void dump(const ScheduleDAG *G) const; 365 void dumpAll(const ScheduleDAG *G) const; 366 void print(raw_ostream &O, const ScheduleDAG *G) const; 367 368 private: 369 void ComputeDepth(); 370 void ComputeHeight(); 371 }; 372 373 //===--------------------------------------------------------------------===// 374 /// SchedulingPriorityQueue - This interface is used to plug different 375 /// priorities computation algorithms into the list scheduler. It implements 376 /// the interface of a standard priority queue, where nodes are inserted in 377 /// arbitrary order and returned in priority order. The computation of the 378 /// priority and the representation of the queue are totally up to the 379 /// implementation to decide. 380 /// 381 class SchedulingPriorityQueue { 382 public: 383 virtual ~SchedulingPriorityQueue() {} 384 385 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 386 virtual void addNode(const SUnit *SU) = 0; 387 virtual void updateNode(const SUnit *SU) = 0; 388 virtual void releaseState() = 0; 389 390 virtual unsigned size() const = 0; 391 virtual bool empty() const = 0; 392 virtual void push(SUnit *U) = 0; 393 394 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 395 virtual SUnit *pop() = 0; 396 397 virtual void remove(SUnit *SU) = 0; 398 399 /// ScheduledNode - As each node is scheduled, this method is invoked. This 400 /// allows the priority function to adjust the priority of related 401 /// unscheduled nodes, for example. 402 /// 403 virtual void ScheduledNode(SUnit *) {} 404 405 virtual void UnscheduledNode(SUnit *) {} 406 }; 407 408 class ScheduleDAG { 409 public: 410 SelectionDAG *DAG; // DAG of the current basic block 411 MachineBasicBlock *BB; // Current basic block 412 const TargetMachine &TM; // Target processor 413 const TargetInstrInfo *TII; // Target instruction information 414 const TargetRegisterInfo *TRI; // Target processor register info 415 TargetLowering *TLI; // Target lowering info 416 MachineFunction *MF; // Machine function 417 MachineRegisterInfo &MRI; // Virtual/real register map 418 MachineConstantPool *ConstPool; // Target constant pool 419 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 420 // represent noop instructions. 421 std::vector<SUnit> SUnits; // The scheduling units. 422 423 ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, 424 const TargetMachine &tm); 425 426 virtual ~ScheduleDAG(); 427 428 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 429 /// using 'dot'. 430 /// 431 void viewGraph(); 432 433 /// Run - perform scheduling. 434 /// 435 void Run(); 436 437 /// BuildSchedUnits - Build SUnits and set up their Preds and Succs 438 /// to form the scheduling dependency graph. 439 /// 440 virtual void BuildSchedUnits() = 0; 441 442 /// ComputeLatency - Compute node latency. 443 /// 444 virtual void ComputeLatency(SUnit *SU) = 0; 445 446 protected: 447 /// EmitNoop - Emit a noop instruction. 448 /// 449 void EmitNoop(); 450 451 public: 452 virtual MachineBasicBlock *EmitSchedule() = 0; 453 454 void dumpSchedule() const; 455 456 /// Schedule - Order nodes according to selected style, filling 457 /// in the Sequence member. 458 /// 459 virtual void Schedule() = 0; 460 461 virtual void dumpNode(const SUnit *SU) const = 0; 462 463 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 464 /// of the ScheduleDAG. 465 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 466 467 /// addCustomGraphFeatures - Add custom features for a visualization of 468 /// the ScheduleDAG. 469 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 470 471#ifndef NDEBUG 472 /// VerifySchedule - Verify that all SUnits were scheduled and that 473 /// their state is consistent. 474 void VerifySchedule(bool isBottomUp); 475#endif 476 477 protected: 478 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); 479 480 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 481 482 /// ForceUnitLatencies - Return true if all scheduling edges should be given a 483 /// latency value of one. The default is to return false; schedulers may 484 /// override this as needed. 485 virtual bool ForceUnitLatencies() const { return false; } 486 487 private: 488 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the 489 /// physical register has only a single copy use, then coalesced the copy 490 /// if possible. 491 void EmitLiveInCopy(MachineBasicBlock *MBB, 492 MachineBasicBlock::iterator &InsertPos, 493 unsigned VirtReg, unsigned PhysReg, 494 const TargetRegisterClass *RC, 495 DenseMap<MachineInstr*, unsigned> &CopyRegMap); 496 497 /// EmitLiveInCopies - If this is the first basic block in the function, 498 /// and if it has live ins that need to be copied into vregs, emit the 499 /// copies into the top of the block. 500 void EmitLiveInCopies(MachineBasicBlock *MBB); 501 }; 502 503 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { 504 SUnit *Node; 505 unsigned Operand; 506 507 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 508 public: 509 bool operator==(const SUnitIterator& x) const { 510 return Operand == x.Operand; 511 } 512 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 513 514 const SUnitIterator &operator=(const SUnitIterator &I) { 515 assert(I.Node == Node && "Cannot assign iterators to two different nodes!"); 516 Operand = I.Operand; 517 return *this; 518 } 519 520 pointer operator*() const { 521 return Node->Preds[Operand].getSUnit(); 522 } 523 pointer operator->() const { return operator*(); } 524 525 SUnitIterator& operator++() { // Preincrement 526 ++Operand; 527 return *this; 528 } 529 SUnitIterator operator++(int) { // Postincrement 530 SUnitIterator tmp = *this; ++*this; return tmp; 531 } 532 533 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 534 static SUnitIterator end (SUnit *N) { 535 return SUnitIterator(N, (unsigned)N->Preds.size()); 536 } 537 538 unsigned getOperand() const { return Operand; } 539 const SUnit *getNode() const { return Node; } 540 /// isCtrlDep - Test if this is not an SDep::Data dependence. 541 bool isCtrlDep() const { 542 return getSDep().isCtrl(); 543 } 544 bool isArtificialDep() const { 545 return getSDep().isArtificial(); 546 } 547 const SDep &getSDep() const { 548 return Node->Preds[Operand]; 549 } 550 }; 551 552 template <> struct GraphTraits<SUnit*> { 553 typedef SUnit NodeType; 554 typedef SUnitIterator ChildIteratorType; 555 static inline NodeType *getEntryNode(SUnit *N) { return N; } 556 static inline ChildIteratorType child_begin(NodeType *N) { 557 return SUnitIterator::begin(N); 558 } 559 static inline ChildIteratorType child_end(NodeType *N) { 560 return SUnitIterator::end(N); 561 } 562 }; 563 564 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 565 typedef std::vector<SUnit>::iterator nodes_iterator; 566 static nodes_iterator nodes_begin(ScheduleDAG *G) { 567 return G->SUnits.begin(); 568 } 569 static nodes_iterator nodes_end(ScheduleDAG *G) { 570 return G->SUnits.end(); 571 } 572 }; 573 574 /// ScheduleDAGTopologicalSort is a class that computes a topological 575 /// ordering for SUnits and provides methods for dynamically updating 576 /// the ordering as new edges are added. 577 /// 578 /// This allows a very fast implementation of IsReachable, for example. 579 /// 580 class ScheduleDAGTopologicalSort { 581 /// SUnits - A reference to the ScheduleDAG's SUnits. 582 std::vector<SUnit> &SUnits; 583 584 /// Index2Node - Maps topological index to the node number. 585 std::vector<int> Index2Node; 586 /// Node2Index - Maps the node number to its topological index. 587 std::vector<int> Node2Index; 588 /// Visited - a set of nodes visited during a DFS traversal. 589 BitVector Visited; 590 591 /// DFS - make a DFS traversal and mark all nodes affected by the 592 /// edge insertion. These nodes will later get new topological indexes 593 /// by means of the Shift method. 594 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 595 596 /// Shift - reassign topological indexes for the nodes in the DAG 597 /// to preserve the topological ordering. 598 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 599 600 /// Allocate - assign the topological index to the node n. 601 void Allocate(int n, int index); 602 603 public: 604 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 605 606 /// InitDAGTopologicalSorting - create the initial topological 607 /// ordering from the DAG to be scheduled. 608 void InitDAGTopologicalSorting(); 609 610 /// IsReachable - Checks if SU is reachable from TargetSU. 611 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 612 613 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 614 /// will create a cycle. 615 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 616 617 /// AddPred - Updates the topological ordering to accomodate an edge 618 /// to be added from SUnit X to SUnit Y. 619 void AddPred(SUnit *Y, SUnit *X); 620 621 /// RemovePred - Updates the topological ordering to accomodate an 622 /// an edge to be removed from the specified node N from the predecessors 623 /// of the current node M. 624 void RemovePred(SUnit *M, SUnit *N); 625 626 typedef std::vector<int>::iterator iterator; 627 typedef std::vector<int>::const_iterator const_iterator; 628 iterator begin() { return Index2Node.begin(); } 629 const_iterator begin() const { return Index2Node.begin(); } 630 iterator end() { return Index2Node.end(); } 631 const_iterator end() const { return Index2Node.end(); } 632 633 typedef std::vector<int>::reverse_iterator reverse_iterator; 634 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 635 reverse_iterator rbegin() { return Index2Node.rbegin(); } 636 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 637 reverse_iterator rend() { return Index2Node.rend(); } 638 const_reverse_iterator rend() const { return Index2Node.rend(); } 639 }; 640} 641 642#endif 643