ScheduleDAG.h revision bfdf7f38523bd38ae0538861a2bfd8bdc46e5c33
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 class AliasAnalysis; 27 class SUnit; 28 class MachineConstantPool; 29 class MachineFunction; 30 class MachineModuleInfo; 31 class MachineRegisterInfo; 32 class MachineInstr; 33 class TargetRegisterInfo; 34 class ScheduleDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 template<class Graph> class GraphWriter; 42 43 /// SDep - Scheduling dependency. This represents one direction of an 44 /// edge in the scheduling DAG. 45 class SDep { 46 public: 47 /// Kind - These are the different kinds of scheduling dependencies. 48 enum Kind { 49 Data, ///< Regular data dependence (aka true-dependence). 50 Anti, ///< A register anti-dependedence (aka WAR). 51 Output, ///< A register output-dependence (aka WAW). 52 Order ///< Any other ordering dependency. 53 }; 54 55 private: 56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 57 /// indicating the kind of the dependency. 58 PointerIntPair<SUnit *, 2, Kind> Dep; 59 60 /// Contents - A union discriminated by the dependence kind. 61 union { 62 /// Reg - For Data, Anti, and Output dependencies, the associated 63 /// register. For Data dependencies that don't currently have a register 64 /// assigned, this is set to zero. 65 unsigned Reg; 66 67 /// Order - Additional information about Order dependencies. 68 struct { 69 /// isNormalMemory - True if both sides of the dependence 70 /// access memory in non-volatile and fully modeled ways. 71 bool isNormalMemory : 1; 72 73 /// isMustAlias - True if both sides of the dependence are known to 74 /// access the same memory. 75 bool isMustAlias : 1; 76 77 /// isArtificial - True if this is an artificial dependency, meaning 78 /// it is not necessary for program correctness, and may be safely 79 /// deleted if necessary. 80 bool isArtificial : 1; 81 } Order; 82 } Contents; 83 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 86 /// models may provide additional information about specific edges. 87 unsigned Latency; 88 89 public: 90 /// SDep - Construct a null SDep. This is only for use by container 91 /// classes which require default constructors. SUnits may not 92 /// have null SDep edges. 93 SDep() : Dep(0, Data) {} 94 95 /// SDep - Construct an SDep with the specified values. 96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 97 bool isNormalMemory = false, bool isMustAlias = false, 98 bool isArtificial = false) 99 : Dep(S, kind), Contents(), Latency(latency) { 100 switch (kind) { 101 case Anti: 102 case Output: 103 assert(Reg != 0 && 104 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 105 // fall through 106 case Data: 107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 108 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 109 Contents.Reg = Reg; 110 break; 111 case Order: 112 assert(Reg == 0 && "Reg given for non-register dependence!"); 113 Contents.Order.isNormalMemory = isNormalMemory; 114 Contents.Order.isMustAlias = isMustAlias; 115 Contents.Order.isArtificial = isArtificial; 116 break; 117 } 118 } 119 120 bool operator==(const SDep &Other) const { 121 if (Dep != Other.Dep || Latency != Other.Latency) return false; 122 switch (Dep.getInt()) { 123 case Data: 124 case Anti: 125 case Output: 126 return Contents.Reg == Other.Contents.Reg; 127 case Order: 128 return Contents.Order.isNormalMemory == 129 Other.Contents.Order.isNormalMemory && 130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 132 } 133 assert(0 && "Invalid dependency kind!"); 134 return false; 135 } 136 137 bool operator!=(const SDep &Other) const { 138 return !operator==(Other); 139 } 140 141 /// getLatency - Return the latency value for this edge, which roughly 142 /// means the minimum number of cycles that must elapse between the 143 /// predecessor and the successor, given that they have this edge 144 /// between them. 145 unsigned getLatency() const { 146 return Latency; 147 } 148 149 /// setLatency - Set the latency for this edge. 150 void setLatency(unsigned Lat) { 151 Latency = Lat; 152 } 153 154 //// getSUnit - Return the SUnit to which this edge points. 155 SUnit *getSUnit() const { 156 return Dep.getPointer(); 157 } 158 159 //// setSUnit - Assign the SUnit to which this edge points. 160 void setSUnit(SUnit *SU) { 161 Dep.setPointer(SU); 162 } 163 164 /// getKind - Return an enum value representing the kind of the dependence. 165 Kind getKind() const { 166 return Dep.getInt(); 167 } 168 169 /// isCtrl - Shorthand for getKind() != SDep::Data. 170 bool isCtrl() const { 171 return getKind() != Data; 172 } 173 174 /// isNormalMemory - Test if this is an Order dependence between two 175 /// memory accesses where both sides of the dependence access memory 176 /// in non-volatile and fully modeled ways. 177 bool isNormalMemory() const { 178 return getKind() == Order && Contents.Order.isNormalMemory; 179 } 180 181 /// isMustAlias - Test if this is an Order dependence that is marked 182 /// as "must alias", meaning that the SUnits at either end of the edge 183 /// have a memory dependence on a known memory location. 184 bool isMustAlias() const { 185 return getKind() == Order && Contents.Order.isMustAlias; 186 } 187 188 /// isArtificial - Test if this is an Order dependence that is marked 189 /// as "artificial", meaning it isn't necessary for correctness. 190 bool isArtificial() const { 191 return getKind() == Order && Contents.Order.isArtificial; 192 } 193 194 /// isAssignedRegDep - Test if this is a Data dependence that is 195 /// associated with a register. 196 bool isAssignedRegDep() const { 197 return getKind() == Data && Contents.Reg != 0; 198 } 199 200 /// getReg - Return the register associated with this edge. This is 201 /// only valid on Data, Anti, and Output edges. On Data edges, this 202 /// value may be zero, meaning there is no associated register. 203 unsigned getReg() const { 204 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 205 "getReg called on non-register dependence edge!"); 206 return Contents.Reg; 207 } 208 209 /// setReg - Assign the associated register for this edge. This is 210 /// only valid on Data, Anti, and Output edges. On Anti and Output 211 /// edges, this value must not be zero. On Data edges, the value may 212 /// be zero, which would mean that no specific register is associated 213 /// with this edge. 214 void setReg(unsigned Reg) { 215 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 216 "setReg called on non-register dependence edge!"); 217 assert((getKind() != Anti || Reg != 0) && 218 "SDep::Anti edge cannot use the zero register!"); 219 assert((getKind() != Output || Reg != 0) && 220 "SDep::Output edge cannot use the zero register!"); 221 Contents.Reg = Reg; 222 } 223 }; 224 225 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 226 class SUnit { 227 private: 228 SDNode *Node; // Representative node. 229 MachineInstr *Instr; // Alternatively, a MachineInstr. 230 MachineInstr *DbgInstr; // A dbg_value referencing this. 231 public: 232 SUnit *OrigNode; // If not this, the node from which 233 // this node was cloned. 234 235 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 236 // is true if the edge is a token chain edge, false if it is a value edge. 237 SmallVector<SDep, 4> Preds; // All sunit predecessors. 238 SmallVector<SDep, 4> Succs; // All sunit successors. 239 240 typedef SmallVector<SDep, 4>::iterator pred_iterator; 241 typedef SmallVector<SDep, 4>::iterator succ_iterator; 242 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 243 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 244 245 unsigned NodeNum; // Entry # of node in the node vector. 246 unsigned NodeQueueId; // Queue id of node. 247 unsigned short Latency; // Node latency. 248 unsigned NumPreds; // # of SDep::Data preds. 249 unsigned NumSuccs; // # of SDep::Data sucss. 250 unsigned NumPredsLeft; // # of preds not scheduled. 251 unsigned NumSuccsLeft; // # of succs not scheduled. 252 bool isTwoAddress : 1; // Is a two-address instruction. 253 bool isCommutable : 1; // Is a commutable instruction. 254 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 255 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not. 256 bool isPending : 1; // True once pending. 257 bool isAvailable : 1; // True once available. 258 bool isScheduled : 1; // True once scheduled. 259 bool isScheduleHigh : 1; // True if preferable to schedule high. 260 bool isCloned : 1; // True if this node has been cloned. 261 private: 262 bool isDepthCurrent : 1; // True if Depth is current. 263 bool isHeightCurrent : 1; // True if Height is current. 264 unsigned Depth; // Node depth. 265 unsigned Height; // Node height. 266 public: 267 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 268 const TargetRegisterClass *CopySrcRC; 269 270 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 271 /// an SDNode and any nodes flagged to it. 272 SUnit(SDNode *node, unsigned nodenum) 273 : Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum), 274 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 275 NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), 276 hasPhysRegDefs(false), hasPhysRegClobbers(false), 277 isPending(false), isAvailable(false), isScheduled(false), 278 isScheduleHigh(false), isCloned(false), 279 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 280 CopyDstRC(NULL), CopySrcRC(NULL) {} 281 282 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 283 /// a MachineInstr. 284 SUnit(MachineInstr *instr, unsigned nodenum) 285 : Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum), 286 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 287 NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), 288 hasPhysRegDefs(false), hasPhysRegClobbers(false), 289 isPending(false), isAvailable(false), isScheduled(false), 290 isScheduleHigh(false), isCloned(false), 291 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 292 CopyDstRC(NULL), CopySrcRC(NULL) {} 293 294 /// SUnit - Construct a placeholder SUnit. 295 SUnit() 296 : Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u), 297 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), 298 NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), 299 hasPhysRegDefs(false), hasPhysRegClobbers(false), 300 isPending(false), isAvailable(false), isScheduled(false), 301 isScheduleHigh(false), isCloned(false), 302 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 303 CopyDstRC(NULL), CopySrcRC(NULL) {} 304 305 /// setNode - Assign the representative SDNode for this SUnit. 306 /// This may be used during pre-regalloc scheduling. 307 void setNode(SDNode *N) { 308 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 309 Node = N; 310 } 311 312 /// getNode - Return the representative SDNode for this SUnit. 313 /// This may be used during pre-regalloc scheduling. 314 SDNode *getNode() const { 315 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 316 return Node; 317 } 318 319 /// setInstr - Assign the instruction for the SUnit. 320 /// This may be used during post-regalloc scheduling. 321 void setInstr(MachineInstr *MI) { 322 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 323 Instr = MI; 324 } 325 326 /// getInstr - Return the representative MachineInstr for this SUnit. 327 /// This may be used during post-regalloc scheduling. 328 MachineInstr *getInstr() const { 329 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 330 return Instr; 331 } 332 333 /// setDbgInstr - Assign the debug instruction for the SUnit. 334 /// This may be used during post-regalloc scheduling. 335 void setDbgInstr(MachineInstr *MI) { 336 assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!"); 337 DbgInstr = MI; 338 } 339 340 /// getDbgInstr - Return the debug MachineInstr for this SUnit. 341 /// This may be used during post-regalloc scheduling. 342 MachineInstr *getDbgInstr() const { 343 assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!"); 344 return DbgInstr; 345 } 346 347 /// addPred - This adds the specified edge as a pred of the current node if 348 /// not already. It also adds the current node as a successor of the 349 /// specified node. 350 void addPred(const SDep &D); 351 352 /// removePred - This removes the specified edge as a pred of the current 353 /// node if it exists. It also removes the current node as a successor of 354 /// the specified node. 355 void removePred(const SDep &D); 356 357 /// getDepth - Return the depth of this node, which is the length of the 358 /// maximum path up to any node with has no predecessors. 359 unsigned getDepth() const { 360 if (!isDepthCurrent) 361 const_cast<SUnit *>(this)->ComputeDepth(); 362 return Depth; 363 } 364 365 /// getHeight - Return the height of this node, which is the length of the 366 /// maximum path down to any node with has no successors. 367 unsigned getHeight() const { 368 if (!isHeightCurrent) 369 const_cast<SUnit *>(this)->ComputeHeight(); 370 return Height; 371 } 372 373 /// setDepthToAtLeast - If NewDepth is greater than this node's 374 /// depth value, set it to be the new depth value. This also 375 /// recursively marks successor nodes dirty. 376 void setDepthToAtLeast(unsigned NewDepth); 377 378 /// setDepthToAtLeast - If NewDepth is greater than this node's 379 /// depth value, set it to be the new height value. This also 380 /// recursively marks predecessor nodes dirty. 381 void setHeightToAtLeast(unsigned NewHeight); 382 383 /// setDepthDirty - Set a flag in this node to indicate that its 384 /// stored Depth value will require recomputation the next time 385 /// getDepth() is called. 386 void setDepthDirty(); 387 388 /// setHeightDirty - Set a flag in this node to indicate that its 389 /// stored Height value will require recomputation the next time 390 /// getHeight() is called. 391 void setHeightDirty(); 392 393 /// isPred - Test if node N is a predecessor of this node. 394 bool isPred(SUnit *N) { 395 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 396 if (Preds[i].getSUnit() == N) 397 return true; 398 return false; 399 } 400 401 /// isSucc - Test if node N is a successor of this node. 402 bool isSucc(SUnit *N) { 403 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 404 if (Succs[i].getSUnit() == N) 405 return true; 406 return false; 407 } 408 409 void dump(const ScheduleDAG *G) const; 410 void dumpAll(const ScheduleDAG *G) const; 411 void print(raw_ostream &O, const ScheduleDAG *G) const; 412 413 private: 414 void ComputeDepth(); 415 void ComputeHeight(); 416 }; 417 418 //===--------------------------------------------------------------------===// 419 /// SchedulingPriorityQueue - This interface is used to plug different 420 /// priorities computation algorithms into the list scheduler. It implements 421 /// the interface of a standard priority queue, where nodes are inserted in 422 /// arbitrary order and returned in priority order. The computation of the 423 /// priority and the representation of the queue are totally up to the 424 /// implementation to decide. 425 /// 426 class SchedulingPriorityQueue { 427 public: 428 virtual ~SchedulingPriorityQueue() {} 429 430 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 431 virtual void addNode(const SUnit *SU) = 0; 432 virtual void updateNode(const SUnit *SU) = 0; 433 virtual void releaseState() = 0; 434 435 virtual unsigned size() const = 0; 436 virtual bool empty() const = 0; 437 virtual void push(SUnit *U) = 0; 438 439 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 440 virtual SUnit *pop() = 0; 441 442 virtual void remove(SUnit *SU) = 0; 443 444 /// ScheduledNode - As each node is scheduled, this method is invoked. This 445 /// allows the priority function to adjust the priority of related 446 /// unscheduled nodes, for example. 447 /// 448 virtual void ScheduledNode(SUnit *) {} 449 450 virtual void UnscheduledNode(SUnit *) {} 451 }; 452 453 class ScheduleDAG { 454 public: 455 MachineBasicBlock *BB; // The block in which to insert instructions 456 MachineBasicBlock::iterator InsertPos;// The position to insert instructions 457 const TargetMachine &TM; // Target processor 458 const TargetInstrInfo *TII; // Target instruction information 459 const TargetRegisterInfo *TRI; // Target processor register info 460 const TargetLowering *TLI; // Target lowering info 461 MachineFunction &MF; // Machine function 462 MachineRegisterInfo &MRI; // Virtual/real register map 463 MachineConstantPool *ConstPool; // Target constant pool 464 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 465 // represent noop instructions. 466 std::vector<SUnit> SUnits; // The scheduling units. 467 SUnit EntrySU; // Special node for the region entry. 468 SUnit ExitSU; // Special node for the region exit. 469 470 explicit ScheduleDAG(MachineFunction &mf); 471 472 virtual ~ScheduleDAG(); 473 474 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 475 /// using 'dot'. 476 /// 477 void viewGraph(); 478 479 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock 480 /// according to the order specified in Sequence. 481 /// 482 virtual MachineBasicBlock* 483 EmitSchedule(DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) = 0; 484 485 void dumpSchedule() const; 486 487 virtual void dumpNode(const SUnit *SU) const = 0; 488 489 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 490 /// of the ScheduleDAG. 491 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 492 493 /// addCustomGraphFeatures - Add custom features for a visualization of 494 /// the ScheduleDAG. 495 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 496 497#ifndef NDEBUG 498 /// VerifySchedule - Verify that all SUnits were scheduled and that 499 /// their state is consistent. 500 void VerifySchedule(bool isBottomUp); 501#endif 502 503 protected: 504 /// Run - perform scheduling. 505 /// 506 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); 507 508 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs 509 /// to form the scheduling dependency graph. 510 /// 511 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0; 512 513 /// ComputeLatency - Compute node latency. 514 /// 515 virtual void ComputeLatency(SUnit *SU) = 0; 516 517 /// ComputeOperandLatency - Override dependence edge latency using 518 /// operand use/def information 519 /// 520 virtual void ComputeOperandLatency(SUnit *, SUnit *, 521 SDep&) const { } 522 523 /// Schedule - Order nodes according to selected style, filling 524 /// in the Sequence member. 525 /// 526 virtual void Schedule() = 0; 527 528 /// ForceUnitLatencies - Return true if all scheduling edges should be given 529 /// a latency value of one. The default is to return false; schedulers may 530 /// override this as needed. 531 virtual bool ForceUnitLatencies() const { return false; } 532 533 /// EmitNoop - Emit a noop instruction. 534 /// 535 void EmitNoop(); 536 537 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 538 }; 539 540 class SUnitIterator : public std::iterator<std::forward_iterator_tag, 541 SUnit, ptrdiff_t> { 542 SUnit *Node; 543 unsigned Operand; 544 545 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 546 public: 547 bool operator==(const SUnitIterator& x) const { 548 return Operand == x.Operand; 549 } 550 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 551 552 const SUnitIterator &operator=(const SUnitIterator &I) { 553 assert(I.Node==Node && "Cannot assign iterators to two different nodes!"); 554 Operand = I.Operand; 555 return *this; 556 } 557 558 pointer operator*() const { 559 return Node->Preds[Operand].getSUnit(); 560 } 561 pointer operator->() const { return operator*(); } 562 563 SUnitIterator& operator++() { // Preincrement 564 ++Operand; 565 return *this; 566 } 567 SUnitIterator operator++(int) { // Postincrement 568 SUnitIterator tmp = *this; ++*this; return tmp; 569 } 570 571 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 572 static SUnitIterator end (SUnit *N) { 573 return SUnitIterator(N, (unsigned)N->Preds.size()); 574 } 575 576 unsigned getOperand() const { return Operand; } 577 const SUnit *getNode() const { return Node; } 578 /// isCtrlDep - Test if this is not an SDep::Data dependence. 579 bool isCtrlDep() const { 580 return getSDep().isCtrl(); 581 } 582 bool isArtificialDep() const { 583 return getSDep().isArtificial(); 584 } 585 const SDep &getSDep() const { 586 return Node->Preds[Operand]; 587 } 588 }; 589 590 template <> struct GraphTraits<SUnit*> { 591 typedef SUnit NodeType; 592 typedef SUnitIterator ChildIteratorType; 593 static inline NodeType *getEntryNode(SUnit *N) { return N; } 594 static inline ChildIteratorType child_begin(NodeType *N) { 595 return SUnitIterator::begin(N); 596 } 597 static inline ChildIteratorType child_end(NodeType *N) { 598 return SUnitIterator::end(N); 599 } 600 }; 601 602 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 603 typedef std::vector<SUnit>::iterator nodes_iterator; 604 static nodes_iterator nodes_begin(ScheduleDAG *G) { 605 return G->SUnits.begin(); 606 } 607 static nodes_iterator nodes_end(ScheduleDAG *G) { 608 return G->SUnits.end(); 609 } 610 }; 611 612 /// ScheduleDAGTopologicalSort is a class that computes a topological 613 /// ordering for SUnits and provides methods for dynamically updating 614 /// the ordering as new edges are added. 615 /// 616 /// This allows a very fast implementation of IsReachable, for example. 617 /// 618 class ScheduleDAGTopologicalSort { 619 /// SUnits - A reference to the ScheduleDAG's SUnits. 620 std::vector<SUnit> &SUnits; 621 622 /// Index2Node - Maps topological index to the node number. 623 std::vector<int> Index2Node; 624 /// Node2Index - Maps the node number to its topological index. 625 std::vector<int> Node2Index; 626 /// Visited - a set of nodes visited during a DFS traversal. 627 BitVector Visited; 628 629 /// DFS - make a DFS traversal and mark all nodes affected by the 630 /// edge insertion. These nodes will later get new topological indexes 631 /// by means of the Shift method. 632 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 633 634 /// Shift - reassign topological indexes for the nodes in the DAG 635 /// to preserve the topological ordering. 636 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 637 638 /// Allocate - assign the topological index to the node n. 639 void Allocate(int n, int index); 640 641 public: 642 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 643 644 /// InitDAGTopologicalSorting - create the initial topological 645 /// ordering from the DAG to be scheduled. 646 void InitDAGTopologicalSorting(); 647 648 /// IsReachable - Checks if SU is reachable from TargetSU. 649 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 650 651 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 652 /// will create a cycle. 653 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 654 655 /// AddPred - Updates the topological ordering to accomodate an edge 656 /// to be added from SUnit X to SUnit Y. 657 void AddPred(SUnit *Y, SUnit *X); 658 659 /// RemovePred - Updates the topological ordering to accomodate an 660 /// an edge to be removed from the specified node N from the predecessors 661 /// of the current node M. 662 void RemovePred(SUnit *M, SUnit *N); 663 664 typedef std::vector<int>::iterator iterator; 665 typedef std::vector<int>::const_iterator const_iterator; 666 iterator begin() { return Index2Node.begin(); } 667 const_iterator begin() const { return Index2Node.begin(); } 668 iterator end() { return Index2Node.end(); } 669 const_iterator end() const { return Index2Node.end(); } 670 671 typedef std::vector<int>::reverse_iterator reverse_iterator; 672 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 673 reverse_iterator rbegin() { return Index2Node.rbegin(); } 674 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 675 reverse_iterator rend() { return Index2Node.rend(); } 676 const_reverse_iterator rend() const { return Index2Node.rend(); } 677 }; 678} 679 680#endif 681