MachineVerifier.cpp revision 44b27e5c7522e0e2e1a48efefceab8508db711b9 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/ADT/DenseSet.h"
27#include "llvm/ADT/SetOperations.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/Function.h"
30#include "llvm/CodeGen/LiveVariables.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Target/TargetInstrInfo.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include <fstream>
40
41using namespace llvm;
42
43namespace {
44  struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
45    static char ID; // Pass ID, replacement for typeid
46
47    MachineVerifier(bool allowDoubleDefs = false) :
48      MachineFunctionPass(&ID),
49      allowVirtDoubleDefs(allowDoubleDefs),
50      allowPhysDoubleDefs(allowDoubleDefs),
51      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
52        {}
53
54    void getAnalysisUsage(AnalysisUsage &AU) const {
55      AU.setPreservesAll();
56    }
57
58    bool runOnMachineFunction(MachineFunction &MF);
59
60    const bool allowVirtDoubleDefs;
61    const bool allowPhysDoubleDefs;
62
63    const char *const OutFileName;
64    std::ostream *OS;
65    const MachineFunction *MF;
66    const TargetMachine *TM;
67    const TargetRegisterInfo *TRI;
68    const MachineRegisterInfo *MRI;
69
70    unsigned foundErrors;
71
72    typedef SmallVector<unsigned, 16> RegVector;
73    typedef DenseSet<unsigned> RegSet;
74    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
75
76    BitVector regsReserved;
77    RegSet regsLive;
78    RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
79
80    // Add Reg and any sub-registers to RV
81    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
82      RV.push_back(Reg);
83      if (TargetRegisterInfo::isPhysicalRegister(Reg))
84        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
85          RV.push_back(*R);
86    }
87
88    // Does RS contain any super-registers of Reg?
89    bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
90      for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
91        if (RS.count(*R))
92          return true;
93      return false;
94    }
95
96    struct BBInfo {
97      // Is this MBB reachable from the MF entry point?
98      bool reachable;
99
100      // Vregs that must be live in because they are used without being
101      // defined. Map value is the user.
102      RegMap vregsLiveIn;
103
104      // Vregs that must be dead in because they are defined without being
105      // killed first. Map value is the defining instruction.
106      RegMap vregsDeadIn;
107
108      // Regs killed in MBB. They may be defined again, and will then be in both
109      // regsKilled and regsLiveOut.
110      RegSet regsKilled;
111
112      // Regs defined in MBB and live out. Note that vregs passing through may
113      // be live out without being mentioned here.
114      RegSet regsLiveOut;
115
116      // Vregs that pass through MBB untouched. This set is disjoint from
117      // regsKilled and regsLiveOut.
118      RegSet vregsPassed;
119
120      BBInfo() : reachable(false) {}
121
122      // Add register to vregsPassed if it belongs there. Return true if
123      // anything changed.
124      bool addPassed(unsigned Reg) {
125        if (!TargetRegisterInfo::isVirtualRegister(Reg))
126          return false;
127        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
128          return false;
129        return vregsPassed.insert(Reg).second;
130      }
131
132      // Same for a full set.
133      bool addPassed(const RegSet &RS) {
134        bool changed = false;
135        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
136          if (addPassed(*I))
137            changed = true;
138        return changed;
139      }
140
141      // Live-out registers are either in regsLiveOut or vregsPassed.
142      bool isLiveOut(unsigned Reg) const {
143        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
144      }
145    };
146
147    // Extra register info per MBB.
148    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
149
150    bool isReserved(unsigned Reg) {
151      return Reg < regsReserved.size() && regsReserved[Reg];
152    }
153
154    void visitMachineFunctionBefore();
155    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
156    void visitMachineInstrBefore(const MachineInstr *MI);
157    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
158    void visitMachineInstrAfter(const MachineInstr *MI);
159    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
160    void visitMachineFunctionAfter();
161
162    void report(const char *msg, const MachineFunction *MF);
163    void report(const char *msg, const MachineBasicBlock *MBB);
164    void report(const char *msg, const MachineInstr *MI);
165    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
166
167    void markReachable(const MachineBasicBlock *MBB);
168    void calcMaxRegsPassed();
169    void calcMinRegsPassed();
170    void checkPHIOps(const MachineBasicBlock *MBB);
171  };
172}
173
174char MachineVerifier::ID = 0;
175static RegisterPass<MachineVerifier>
176MachineVer("verify-machineinstrs", "Verify generated machine code");
177static const PassInfo *const MachineVerifyID = &MachineVer;
178
179FunctionPass *
180llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
181{
182  return new MachineVerifier(allowPhysDoubleDefs);
183}
184
185bool
186MachineVerifier::runOnMachineFunction(MachineFunction &MF)
187{
188  std::ofstream OutFile;
189  if (OutFileName) {
190    OutFile.open(OutFileName, std::ios::out | std::ios::app);
191    OS = &OutFile;
192  } else {
193    OS = cerr.stream();
194  }
195
196  foundErrors = 0;
197
198  this->MF = &MF;
199  TM = &MF.getTarget();
200  TRI = TM->getRegisterInfo();
201  MRI = &MF.getRegInfo();
202
203  visitMachineFunctionBefore();
204  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
205       MFI!=MFE; ++MFI) {
206    visitMachineBasicBlockBefore(MFI);
207    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
208           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
209      visitMachineInstrBefore(MBBI);
210      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
211        visitMachineOperand(&MBBI->getOperand(I), I);
212      visitMachineInstrAfter(MBBI);
213    }
214    visitMachineBasicBlockAfter(MFI);
215  }
216  visitMachineFunctionAfter();
217
218  if (OutFileName)
219    OutFile.close();
220
221  if (foundErrors) {
222    cerr << "\nStopping with " << foundErrors << " machine code errors.\n";
223    exit(1);
224  }
225
226  return false;                 // no changes
227}
228
229void
230MachineVerifier::report(const char *msg, const MachineFunction *MF)
231{
232  assert(MF);
233  *OS << "\n";
234  if (!foundErrors++)
235    MF->print(OS);
236  *OS << "*** Bad machine code: " << msg << " ***\n"
237      << "- function:    " << MF->getFunction()->getName() << "\n";
238}
239
240void
241MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
242{
243  assert(MBB);
244  report(msg, MBB->getParent());
245  *OS << "- basic block: " << MBB->getBasicBlock()->getName()
246      << " " << (void*)MBB
247      << " (#" << MBB->getNumber() << ")\n";
248}
249
250void
251MachineVerifier::report(const char *msg, const MachineInstr *MI)
252{
253  assert(MI);
254  report(msg, MI->getParent());
255  *OS << "- instruction: ";
256  MI->print(OS, TM);
257}
258
259void
260MachineVerifier::report(const char *msg,
261                        const MachineOperand *MO, unsigned MONum)
262{
263  assert(MO);
264  report(msg, MO->getParent());
265  *OS << "- operand " << MONum << ":   ";
266  MO->print(*OS, TM);
267  *OS << "\n";
268}
269
270void
271MachineVerifier::markReachable(const MachineBasicBlock *MBB)
272{
273  BBInfo &MInfo = MBBInfoMap[MBB];
274  if (!MInfo.reachable) {
275    MInfo.reachable = true;
276    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
277           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
278      markReachable(*SuI);
279  }
280}
281
282void
283MachineVerifier::visitMachineFunctionBefore()
284{
285  regsReserved = TRI->getReservedRegs(*MF);
286  markReachable(&MF->front());
287}
288
289void
290MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
291{
292  regsLive.clear();
293  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
294         E = MBB->livein_end(); I != E; ++I) {
295    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
296      report("MBB live-in list contains non-physical register", MBB);
297      continue;
298    }
299    regsLive.insert(*I);
300    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
301      regsLive.insert(*R);
302  }
303  regsKilled.clear();
304  regsDefined.clear();
305  regsImpDefined.clear();
306}
307
308void
309MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
310{
311  const TargetInstrDesc &TI = MI->getDesc();
312  if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
313    report("Too few operands", MI);
314    *OS << TI.getNumOperands() << " operands expected, but "
315        << MI->getNumExplicitOperands() << " given.\n";
316  }
317  if (!TI.isVariadic()) {
318    if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
319      report("Too many operands", MI);
320      *OS << TI.getNumOperands() << " operands expected, but "
321          << MI->getNumExplicitOperands() << " given.\n";
322    }
323  }
324}
325
326void
327MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
328{
329  const MachineInstr *MI = MO->getParent();
330  const TargetInstrDesc &TI = MI->getDesc();
331
332  // The first TI.NumDefs operands must be explicit register defines
333  if (MONum < TI.getNumDefs()) {
334    if (!MO->isReg())
335      report("Explicit definition must be a register", MO, MONum);
336    else if (!MO->isDef())
337      report("Explicit definition marked as use", MO, MONum);
338    else if (MO->isImplicit())
339      report("Explicit definition marked as implicit", MO, MONum);
340  }
341
342  switch (MO->getType()) {
343  case MachineOperand::MO_Register: {
344    const unsigned Reg = MO->getReg();
345    if (!Reg)
346      return;
347
348    // Check Live Variables.
349    if (MO->isUse()) {
350      if (MO->isKill()) {
351        addRegWithSubRegs(regsKilled, Reg);
352      } else {
353        // TwoAddress instr modyfying a reg is treated as kill+def.
354        unsigned defIdx;
355        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
356            MI->getOperand(defIdx).getReg() == Reg)
357          addRegWithSubRegs(regsKilled, Reg);
358      }
359      // Explicit use of a dead register.
360      if (!MO->isImplicit() && !regsLive.count(Reg)) {
361        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
362          // Reserved registers may be used even when 'dead'.
363          if (!isReserved(Reg))
364            report("Using an undefined physical register", MO, MONum);
365        } else {
366          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
367          // We don't know which virtual registers are live in, so only complain
368          // if vreg was killed in this MBB. Otherwise keep track of vregs that
369          // must be live in. PHI instructions are handled separately.
370          if (MInfo.regsKilled.count(Reg))
371            report("Using a killed virtual register", MO, MONum);
372          else if (MI->getOpcode() != TargetInstrInfo::PHI)
373            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
374        }
375      }
376    } else {
377      // Register defined.
378      // TODO: verify that earlyclobber ops are not used.
379      if (MO->isImplicit())
380        addRegWithSubRegs(regsImpDefined, Reg);
381      else
382        addRegWithSubRegs(regsDefined, Reg);
383
384      if (MO->isDead())
385        addRegWithSubRegs(regsDead, Reg);
386    }
387
388    // Check register classes.
389    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
390      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
391      unsigned SubIdx = MO->getSubReg();
392
393      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
394        unsigned sr = Reg;
395        if (SubIdx) {
396          unsigned s = TRI->getSubReg(Reg, SubIdx);
397          if (!s) {
398            report("Invalid subregister index for physical register",
399                   MO, MONum);
400            return;
401          }
402          sr = s;
403        }
404        if (TOI.RegClass) {
405          const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
406          if (!DRC->contains(sr)) {
407            report("Illegal physical register for instruction", MO, MONum);
408            *OS << TRI->getName(sr) << " is not a "
409                << DRC->getName() << " register.\n";
410          }
411        }
412      } else {
413        // Virtual register.
414        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
415        if (SubIdx) {
416          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
417            report("Invalid subregister index for virtual register", MO, MONum);
418            return;
419          }
420          RC = *(RC->subregclasses_begin()+SubIdx);
421        }
422        if (TOI.RegClass) {
423          const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
424          if (RC != DRC && !RC->hasSuperClass(DRC)) {
425            report("Illegal virtual register for instruction", MO, MONum);
426            *OS << "Expected a " << DRC->getName() << " register, but got a "
427                << RC->getName() << " register\n";
428          }
429        }
430      }
431    }
432    break;
433  }
434    // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
435    // case MachineOperand::MO_MachineBasicBlock:
436    //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
437    //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
438    //       report("PHI operand is not in the CFG", MO, MONum);
439    //   }
440    //   break;
441  default:
442    break;
443  }
444}
445
446void
447MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
448{
449  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
450  set_union(MInfo.regsKilled, regsKilled);
451  set_subtract(regsLive, regsKilled);
452  regsKilled.clear();
453
454  for (RegVector::const_iterator I = regsDefined.begin(),
455         E = regsDefined.end(); I != E; ++I) {
456    if (regsLive.count(*I)) {
457      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
458        // We allow double defines to physical registers with live
459        // super-registers.
460        if (!allowPhysDoubleDefs && !isReserved(*I) &&
461            !anySuperRegisters(regsLive, *I)) {
462          report("Redefining a live physical register", MI);
463          *OS << "Register " << TRI->getName(*I)
464              << " was defined but already live.\n";
465        }
466      } else {
467        if (!allowVirtDoubleDefs) {
468          report("Redefining a live virtual register", MI);
469          *OS << "Virtual register %reg" << *I
470              << " was defined but already live.\n";
471        }
472      }
473    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
474               !MInfo.regsKilled.count(*I)) {
475      // Virtual register defined without being killed first must be dead on
476      // entry.
477      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
478    }
479  }
480
481  set_union(regsLive, regsDefined); regsDefined.clear();
482  set_union(regsLive, regsImpDefined); regsImpDefined.clear();
483  set_subtract(regsLive, regsDead); regsDead.clear();
484}
485
486void
487MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
488{
489  MBBInfoMap[MBB].regsLiveOut = regsLive;
490  regsLive.clear();
491}
492
493// Calculate the largest possible vregsPassed sets. These are the registers that
494// can pass through an MBB live, but may not be live every time. It is assumed
495// that all vregsPassed sets are empty before the call.
496void
497MachineVerifier::calcMaxRegsPassed()
498{
499  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
500  // have any vregsPassed.
501  DenseSet<const MachineBasicBlock*> todo;
502  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
503       MFI != MFE; ++MFI) {
504    const MachineBasicBlock &MBB(*MFI);
505    BBInfo &MInfo = MBBInfoMap[&MBB];
506    if (!MInfo.reachable)
507      continue;
508    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
509           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
510      BBInfo &SInfo = MBBInfoMap[*SuI];
511      if (SInfo.addPassed(MInfo.regsLiveOut))
512        todo.insert(*SuI);
513    }
514  }
515
516  // Iteratively push vregsPassed to successors. This will converge to the same
517  // final state regardless of DenseSet iteration order.
518  while (!todo.empty()) {
519    const MachineBasicBlock *MBB = *todo.begin();
520    todo.erase(MBB);
521    BBInfo &MInfo = MBBInfoMap[MBB];
522    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
523           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
524      if (*SuI == MBB)
525        continue;
526      BBInfo &SInfo = MBBInfoMap[*SuI];
527      if (SInfo.addPassed(MInfo.vregsPassed))
528        todo.insert(*SuI);
529    }
530  }
531}
532
533// Calculate the minimum vregsPassed set. These are the registers that always
534// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
535// been called earlier.
536void
537MachineVerifier::calcMinRegsPassed()
538{
539  DenseSet<const MachineBasicBlock*> todo;
540  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
541       MFI != MFE; ++MFI)
542    todo.insert(MFI);
543
544  while (!todo.empty()) {
545    const MachineBasicBlock *MBB = *todo.begin();
546    todo.erase(MBB);
547    BBInfo &MInfo = MBBInfoMap[MBB];
548
549    // Remove entries from vRegsPassed that are not live out from all
550    // reachable predecessors.
551    RegSet dead;
552    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
553           E = MInfo.vregsPassed.end(); I != E; ++I) {
554      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
555             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
556        BBInfo &PrInfo = MBBInfoMap[*PrI];
557        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
558          dead.insert(*I);
559          break;
560        }
561      }
562    }
563    // If any regs removed, we need to recheck successors.
564    if (!dead.empty()) {
565      set_subtract(MInfo.vregsPassed, dead);
566      todo.insert(MBB->succ_begin(), MBB->succ_end());
567    }
568  }
569}
570
571// Check PHI instructions at the beginning of MBB. It is assumed that
572// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
573void
574MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
575{
576  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
577       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
578    DenseSet<const MachineBasicBlock*> seen;
579
580    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
581      unsigned Reg = BBI->getOperand(i).getReg();
582      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
583      if (!Pre->isSuccessor(MBB))
584        continue;
585      seen.insert(Pre);
586      BBInfo &PrInfo = MBBInfoMap[Pre];
587      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
588        report("PHI operand is not live-out from predecessor",
589               &BBI->getOperand(i), i);
590    }
591
592    // Did we see all predecessors?
593    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
594           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
595      if (!seen.count(*PrI)) {
596        report("Missing PHI operand", BBI);
597        *OS << "MBB #" << (*PrI)->getNumber()
598            << " is a predecessor according to the CFG.\n";
599      }
600    }
601  }
602}
603
604void
605MachineVerifier::visitMachineFunctionAfter()
606{
607  calcMaxRegsPassed();
608
609  // With the maximal set of vregsPassed we can verify dead-in registers.
610  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
611       MFI != MFE; ++MFI) {
612    BBInfo &MInfo = MBBInfoMap[MFI];
613
614    // Skip unreachable MBBs.
615    if (!MInfo.reachable)
616      continue;
617
618    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
619           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
620      BBInfo &PrInfo = MBBInfoMap[*PrI];
621      if (!PrInfo.reachable)
622        continue;
623
624      // Verify physical live-ins. EH landing pads have magic live-ins so we
625      // ignore them.
626      if (!MFI->isLandingPad()) {
627        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
628               E = MFI->livein_end(); I != E; ++I) {
629          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
630              !isReserved (*I) && !PrInfo.isLiveOut(*I)) {
631            report("Live-in physical register is not live-out from predecessor",
632                   MFI);
633            *OS << "Register " << TRI->getName(*I)
634                << " is not live-out from MBB #" << (*PrI)->getNumber()
635                << ".\n";
636          }
637        }
638      }
639
640
641      // Verify dead-in virtual registers.
642      if (!allowVirtDoubleDefs) {
643        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
644               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
645          // DeadIn register must be in neither regsLiveOut or vregsPassed of
646          // any predecessor.
647          if (PrInfo.isLiveOut(I->first)) {
648            report("Live-in virtual register redefined", I->second);
649            *OS << "Register %reg" << I->first
650                << " was live-out from predecessor MBB #"
651                << (*PrI)->getNumber() << ".\n";
652          }
653        }
654      }
655    }
656  }
657
658  calcMinRegsPassed();
659
660  // With the minimal set of vregsPassed we can verify live-in virtual
661  // registers, including PHI instructions.
662  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
663       MFI != MFE; ++MFI) {
664    BBInfo &MInfo = MBBInfoMap[MFI];
665
666    // Skip unreachable MBBs.
667    if (!MInfo.reachable)
668      continue;
669
670    checkPHIOps(MFI);
671
672    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
673           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
674      BBInfo &PrInfo = MBBInfoMap[*PrI];
675      if (!PrInfo.reachable)
676        continue;
677
678      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
679             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
680        if (!PrInfo.isLiveOut(I->first)) {
681          report("Used virtual register is not live-in", I->second);
682          *OS << "Register %reg" << I->first
683              << " is not live-out from predecessor MBB #"
684              << (*PrI)->getNumber()
685              << ".\n";
686        }
687      }
688    }
689  }
690}
691