MachineVerifier.cpp revision e556720ea8d60581c95d3ca3f9175a3688150d95 
1//===-- MachineVerifier.cpp - Machine Code Verifier -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Pass to verify generated machine code. The following is checked:
11//
12// Operand counts: All explicit operands must be present.
13//
14// Register classes: All physical and virtual register operands must be
15// compatible with the register class required by the instruction descriptor.
16//
17// Register live intervals: Registers must be defined only once, and must be
18// defined before use.
19//
20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
21// command-line option -verify-machineinstrs, or by defining the environment
22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
23// the verifier errors.
24//===----------------------------------------------------------------------===//
25
26#include "llvm/ADT/DenseSet.h"
27#include "llvm/ADT/SetOperations.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/Function.h"
30#include "llvm/CodeGen/LiveVariables.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/Target/TargetMachine.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Target/TargetInstrInfo.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include <fstream>
40
41using namespace llvm;
42
43namespace {
44  struct VISIBILITY_HIDDEN MachineVerifier : public MachineFunctionPass {
45    static char ID; // Pass ID, replacement for typeid
46
47    MachineVerifier(bool allowDoubleDefs = false) :
48      MachineFunctionPass(&ID),
49      allowVirtDoubleDefs(allowDoubleDefs),
50      allowPhysDoubleDefs(allowDoubleDefs),
51      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
52        {}
53
54    void getAnalysisUsage(AnalysisUsage &AU) const {
55      AU.setPreservesAll();
56    }
57
58    bool runOnMachineFunction(MachineFunction &MF);
59
60    const bool allowVirtDoubleDefs;
61    const bool allowPhysDoubleDefs;
62
63    const char *const OutFileName;
64    std::ostream *OS;
65    const MachineFunction *MF;
66    const TargetMachine *TM;
67    const TargetRegisterInfo *TRI;
68    const MachineRegisterInfo *MRI;
69
70    unsigned foundErrors;
71
72    typedef SmallVector<unsigned, 16> RegVector;
73    typedef DenseSet<unsigned> RegSet;
74    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
75
76    BitVector regsReserved;
77    RegSet regsLive;
78    RegVector regsDefined, regsImpDefined, regsDead, regsKilled;
79
80    // Add Reg and any sub-registers to RV
81    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
82      RV.push_back(Reg);
83      if (TargetRegisterInfo::isPhysicalRegister(Reg))
84        for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++)
85          RV.push_back(*R);
86    }
87
88    // Does RS contain any super-registers of Reg?
89    bool anySuperRegisters(const RegSet &RS, unsigned Reg) {
90      for (const unsigned *R = TRI->getSuperRegisters(Reg); *R; R++)
91        if (RS.count(*R))
92          return true;
93      return false;
94    }
95
96    struct BBInfo {
97      // Is this MBB reachable from the MF entry point?
98      bool reachable;
99
100      // Vregs that must be live in because they are used without being
101      // defined. Map value is the user.
102      RegMap vregsLiveIn;
103
104      // Vregs that must be dead in because they are defined without being
105      // killed first. Map value is the defining instruction.
106      RegMap vregsDeadIn;
107
108      // Regs killed in MBB. They may be defined again, and will then be in both
109      // regsKilled and regsLiveOut.
110      RegSet regsKilled;
111
112      // Regs defined in MBB and live out. Note that vregs passing through may
113      // be live out without being mentioned here.
114      RegSet regsLiveOut;
115
116      // Vregs that pass through MBB untouched. This set is disjoint from
117      // regsKilled and regsLiveOut.
118      RegSet vregsPassed;
119
120      BBInfo() : reachable(false) {}
121
122      // Add register to vregsPassed if it belongs there. Return true if
123      // anything changed.
124      bool addPassed(unsigned Reg) {
125        if (!TargetRegisterInfo::isVirtualRegister(Reg))
126          return false;
127        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
128          return false;
129        return vregsPassed.insert(Reg).second;
130      }
131
132      // Same for a full set.
133      bool addPassed(const RegSet &RS) {
134        bool changed = false;
135        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
136          if (addPassed(*I))
137            changed = true;
138        return changed;
139      }
140
141      // Live-out registers are either in regsLiveOut or vregsPassed.
142      bool isLiveOut(unsigned Reg) const {
143        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
144      }
145    };
146
147    // Extra register info per MBB.
148    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
149
150    bool isReserved(unsigned Reg) {
151      return Reg < regsReserved.size() && regsReserved[Reg];
152    }
153
154    void visitMachineFunctionBefore();
155    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
156    void visitMachineInstrBefore(const MachineInstr *MI);
157    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
158    void visitMachineInstrAfter(const MachineInstr *MI);
159    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
160    void visitMachineFunctionAfter();
161
162    void report(const char *msg, const MachineFunction *MF);
163    void report(const char *msg, const MachineBasicBlock *MBB);
164    void report(const char *msg, const MachineInstr *MI);
165    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
166
167    void markReachable(const MachineBasicBlock *MBB);
168    void calcMaxRegsPassed();
169    void calcMinRegsPassed();
170    void checkPHIOps(const MachineBasicBlock *MBB);
171  };
172}
173
174char MachineVerifier::ID = 0;
175static RegisterPass<MachineVerifier>
176MachineVer("verify-machineinstrs", "Verify generated machine code");
177static const PassInfo *const MachineVerifyID = &MachineVer;
178
179FunctionPass *
180llvm::createMachineVerifierPass(bool allowPhysDoubleDefs)
181{
182  return new MachineVerifier(allowPhysDoubleDefs);
183}
184
185bool
186MachineVerifier::runOnMachineFunction(MachineFunction &MF)
187{
188  std::ofstream OutFile;
189  if (OutFileName) {
190    OutFile.open(OutFileName, std::ios::out | std::ios::app);
191    OS = &OutFile;
192  } else {
193    OS = cerr.stream();
194  }
195
196  foundErrors = 0;
197
198  this->MF = &MF;
199  TM = &MF.getTarget();
200  TRI = TM->getRegisterInfo();
201  MRI = &MF.getRegInfo();
202
203  visitMachineFunctionBefore();
204  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
205       MFI!=MFE; ++MFI) {
206    visitMachineBasicBlockBefore(MFI);
207    for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
208           MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
209      visitMachineInstrBefore(MBBI);
210      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
211        visitMachineOperand(&MBBI->getOperand(I), I);
212      visitMachineInstrAfter(MBBI);
213    }
214    visitMachineBasicBlockAfter(MFI);
215  }
216  visitMachineFunctionAfter();
217
218  if (OutFileName)
219    OutFile.close();
220
221  if (foundErrors) {
222    cerr << "\nStopping with " << foundErrors << " machine code errors.\n";
223    exit(1);
224  }
225
226  return false;                 // no changes
227}
228
229void
230MachineVerifier::report(const char *msg, const MachineFunction *MF)
231{
232  assert(MF);
233  *OS << "\n";
234  if (!foundErrors++)
235    MF->print(OS);
236  *OS << "*** Bad machine code: " << msg << " ***\n"
237      << "- function:    " << MF->getFunction()->getName() << "\n";
238}
239
240void
241MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB)
242{
243  assert(MBB);
244  report(msg, MBB->getParent());
245  *OS << "- basic block: " << MBB->getBasicBlock()->getName()
246      << " " << (void*)MBB
247      << " (#" << MBB->getNumber() << ")\n";
248}
249
250void
251MachineVerifier::report(const char *msg, const MachineInstr *MI)
252{
253  assert(MI);
254  report(msg, MI->getParent());
255  *OS << "- instruction: ";
256  MI->print(OS, TM);
257}
258
259void
260MachineVerifier::report(const char *msg,
261                        const MachineOperand *MO, unsigned MONum)
262{
263  assert(MO);
264  report(msg, MO->getParent());
265  *OS << "- operand " << MONum << ":   ";
266  MO->print(*OS, TM);
267  *OS << "\n";
268}
269
270void
271MachineVerifier::markReachable(const MachineBasicBlock *MBB)
272{
273  BBInfo &MInfo = MBBInfoMap[MBB];
274  if (!MInfo.reachable) {
275    MInfo.reachable = true;
276    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
277           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
278      markReachable(*SuI);
279  }
280}
281
282void
283MachineVerifier::visitMachineFunctionBefore()
284{
285  regsReserved = TRI->getReservedRegs(*MF);
286  markReachable(&MF->front());
287}
288
289void
290MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB)
291{
292  regsLive.clear();
293  for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
294         E = MBB->livein_end(); I != E; ++I) {
295    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
296      report("MBB live-in list contains non-physical register", MBB);
297      continue;
298    }
299    regsLive.insert(*I);
300    for (const unsigned *R = TRI->getSubRegisters(*I); *R; R++)
301      regsLive.insert(*R);
302  }
303  regsKilled.clear();
304  regsDefined.clear();
305  regsImpDefined.clear();
306}
307
308void
309MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI)
310{
311  const TargetInstrDesc &TI = MI->getDesc();
312  if (MI->getNumExplicitOperands() < TI.getNumOperands()) {
313    report("Too few operands", MI);
314    *OS << TI.getNumOperands() << " operands expected, but "
315        << MI->getNumExplicitOperands() << " given.\n";
316  }
317  if (!TI.isVariadic()) {
318    if (MI->getNumExplicitOperands() > TI.getNumOperands()) {
319      report("Too many operands", MI);
320      *OS << TI.getNumOperands() << " operands expected, but "
321          << MI->getNumExplicitOperands() << " given.\n";
322    }
323  }
324}
325
326void
327MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum)
328{
329  const MachineInstr *MI = MO->getParent();
330  switch (MO->getType()) {
331  case MachineOperand::MO_Register: {
332    const unsigned Reg = MO->getReg();
333    if (!Reg)
334      return;
335
336    // Check Live Variables.
337    if (MO->isUse()) {
338      if (MO->isKill()) {
339        addRegWithSubRegs(regsKilled, Reg);
340      } else {
341        // TwoAddress instr modyfying a reg is treated as kill+def.
342        unsigned defIdx;
343        if (MI->isRegTiedToDefOperand(MONum, &defIdx) &&
344            MI->getOperand(defIdx).getReg() == Reg)
345          addRegWithSubRegs(regsKilled, Reg);
346      }
347      // Explicit use of a dead register.
348      if (!MO->isImplicit() && !regsLive.count(Reg)) {
349        if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
350          // Reserved registers may be used even when 'dead'.
351          if (!isReserved(Reg))
352            report("Using an undefined physical register", MO, MONum);
353        } else {
354          BBInfo &MInfo = MBBInfoMap[MI->getParent()];
355          // We don't know which virtual registers are live in, so only complain
356          // if vreg was killed in this MBB. Otherwise keep track of vregs that
357          // must be live in. PHI instructions are handled separately.
358          if (MInfo.regsKilled.count(Reg))
359            report("Using a killed virtual register", MO, MONum);
360          else if (MI->getOpcode() != TargetInstrInfo::PHI)
361            MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
362        }
363      }
364    } else {
365      // Register defined.
366      // TODO: verify that earlyclobber ops are not used.
367      if (MO->isImplicit())
368        addRegWithSubRegs(regsImpDefined, Reg);
369      else
370        addRegWithSubRegs(regsDefined, Reg);
371
372      if (MO->isDead())
373        addRegWithSubRegs(regsDead, Reg);
374    }
375
376    // Check register classes.
377    const TargetInstrDesc &TI = MI->getDesc();
378    if (MONum < TI.getNumOperands() && !MO->isImplicit()) {
379      const TargetOperandInfo &TOI = TI.OpInfo[MONum];
380      unsigned SubIdx = MO->getSubReg();
381
382      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
383        unsigned sr = Reg;
384        if (SubIdx) {
385          unsigned s = TRI->getSubReg(Reg, SubIdx);
386          if (!s) {
387            report("Invalid subregister index for physical register",
388                   MO, MONum);
389            return;
390          }
391          sr = s;
392        }
393        if (TOI.RegClass) {
394          const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
395          if (!DRC->contains(sr)) {
396            report("Illegal physical register for instruction", MO, MONum);
397            *OS << TRI->getName(sr) << " is not a "
398                << DRC->getName() << " register.\n";
399          }
400        }
401      } else {
402        // Virtual register.
403        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
404        if (SubIdx) {
405          if (RC->subregclasses_begin()+SubIdx >= RC->subregclasses_end()) {
406            report("Invalid subregister index for virtual register", MO, MONum);
407            return;
408          }
409          RC = *(RC->subregclasses_begin()+SubIdx);
410        }
411        if (TOI.RegClass) {
412          const TargetRegisterClass *DRC = TRI->getRegClass(TOI.RegClass);
413          if (RC != DRC && !RC->hasSuperClass(DRC)) {
414            report("Illegal virtual register for instruction", MO, MONum);
415            *OS << "Expected a " << DRC->getName() << " register, but got a "
416                << RC->getName() << " register\n";
417          }
418        }
419      }
420    }
421    break;
422  }
423    // Can PHI instrs refer to MBBs not in the CFG? X86 and ARM do.
424    // case MachineOperand::MO_MachineBasicBlock:
425    //   if (MI->getOpcode() == TargetInstrInfo::PHI) {
426    //     if (!MO->getMBB()->isSuccessor(MI->getParent()))
427    //       report("PHI operand is not in the CFG", MO, MONum);
428    //   }
429    //   break;
430  default:
431    break;
432  }
433}
434
435void
436MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI)
437{
438  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
439  set_union(MInfo.regsKilled, regsKilled);
440  set_subtract(regsLive, regsKilled);
441  regsKilled.clear();
442
443  for (RegVector::const_iterator I = regsDefined.begin(),
444         E = regsDefined.end(); I != E; ++I) {
445    if (regsLive.count(*I)) {
446      if (TargetRegisterInfo::isPhysicalRegister(*I)) {
447        // We allow double defines to physical registers with live
448        // super-registers.
449        if (!allowPhysDoubleDefs && !anySuperRegisters(regsLive, *I)) {
450          report("Redefining a live physical register", MI);
451          *OS << "Register " << TRI->getName(*I)
452              << " was defined but already live.\n";
453        }
454      } else {
455        if (!allowVirtDoubleDefs) {
456          report("Redefining a live virtual register", MI);
457          *OS << "Virtual register %reg" << *I
458              << " was defined but already live.\n";
459        }
460      }
461    } else if (TargetRegisterInfo::isVirtualRegister(*I) &&
462               !MInfo.regsKilled.count(*I)) {
463      // Virtual register defined without being killed first must be dead on
464      // entry.
465      MInfo.vregsDeadIn.insert(std::make_pair(*I, MI));
466    }
467  }
468
469  set_union(regsLive, regsDefined); regsDefined.clear();
470  set_union(regsLive, regsImpDefined); regsImpDefined.clear();
471  set_subtract(regsLive, regsDead); regsDead.clear();
472}
473
474void
475MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB)
476{
477  MBBInfoMap[MBB].regsLiveOut = regsLive;
478  regsLive.clear();
479}
480
481// Calculate the largest possible vregsPassed sets. These are the registers that
482// can pass through an MBB live, but may not be live every time. It is assumed
483// that all vregsPassed sets are empty before the call.
484void
485MachineVerifier::calcMaxRegsPassed()
486{
487  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
488  // have any vregsPassed.
489  DenseSet<const MachineBasicBlock*> todo;
490  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
491       MFI != MFE; ++MFI) {
492    const MachineBasicBlock &MBB(*MFI);
493    BBInfo &MInfo = MBBInfoMap[&MBB];
494    if (!MInfo.reachable)
495      continue;
496    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
497           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
498      BBInfo &SInfo = MBBInfoMap[*SuI];
499      if (SInfo.addPassed(MInfo.regsLiveOut))
500        todo.insert(*SuI);
501    }
502  }
503
504  // Iteratively push vregsPassed to successors. This will converge to the same
505  // final state regardless of DenseSet iteration order.
506  while (!todo.empty()) {
507    const MachineBasicBlock *MBB = *todo.begin();
508    todo.erase(MBB);
509    BBInfo &MInfo = MBBInfoMap[MBB];
510    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
511           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
512      if (*SuI == MBB)
513        continue;
514      BBInfo &SInfo = MBBInfoMap[*SuI];
515      if (SInfo.addPassed(MInfo.vregsPassed))
516        todo.insert(*SuI);
517    }
518  }
519}
520
521// Calculate the minimum vregsPassed set. These are the registers that always
522// pass live through an MBB. The calculation assumes that calcMaxRegsPassed has
523// been called earlier.
524void
525MachineVerifier::calcMinRegsPassed()
526{
527  DenseSet<const MachineBasicBlock*> todo;
528  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
529       MFI != MFE; ++MFI)
530    todo.insert(MFI);
531
532  while (!todo.empty()) {
533    const MachineBasicBlock *MBB = *todo.begin();
534    todo.erase(MBB);
535    BBInfo &MInfo = MBBInfoMap[MBB];
536
537    // Remove entries from vRegsPassed that are not live out from all
538    // reachable predecessors.
539    RegSet dead;
540    for (RegSet::iterator I = MInfo.vregsPassed.begin(),
541           E = MInfo.vregsPassed.end(); I != E; ++I) {
542      for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
543             PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
544        BBInfo &PrInfo = MBBInfoMap[*PrI];
545        if (PrInfo.reachable && !PrInfo.isLiveOut(*I)) {
546          dead.insert(*I);
547          break;
548        }
549      }
550    }
551    // If any regs removed, we need to recheck successors.
552    if (!dead.empty()) {
553      set_subtract(MInfo.vregsPassed, dead);
554      todo.insert(MBB->succ_begin(), MBB->succ_end());
555    }
556  }
557}
558
559// Check PHI instructions at the beginning of MBB. It is assumed that
560// calcMinRegsPassed has been run so BBInfo::isLiveOut is valid.
561void
562MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB)
563{
564  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
565       BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) {
566    DenseSet<const MachineBasicBlock*> seen;
567
568    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
569      unsigned Reg = BBI->getOperand(i).getReg();
570      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
571      if (!Pre->isSuccessor(MBB))
572        continue;
573      seen.insert(Pre);
574      BBInfo &PrInfo = MBBInfoMap[Pre];
575      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
576        report("PHI operand is not live-out from predecessor",
577               &BBI->getOperand(i), i);
578    }
579
580    // Did we see all predecessors?
581    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
582           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
583      if (!seen.count(*PrI)) {
584        report("Missing PHI operand", BBI);
585        *OS << "MBB #" << (*PrI)->getNumber()
586            << " is a predecessor according to the CFG.\n";
587      }
588    }
589  }
590}
591
592void
593MachineVerifier::visitMachineFunctionAfter()
594{
595  calcMaxRegsPassed();
596
597  // With the maximal set of vregsPassed we can verify dead-in registers.
598  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
599       MFI != MFE; ++MFI) {
600    BBInfo &MInfo = MBBInfoMap[MFI];
601
602    // Skip unreachable MBBs.
603    if (!MInfo.reachable)
604      continue;
605
606    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
607           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
608      BBInfo &PrInfo = MBBInfoMap[*PrI];
609      if (!PrInfo.reachable)
610        continue;
611
612      // Verify physical live-ins. EH landing pads have magic live-ins so we
613      // ignore them.
614      if (!MFI->isLandingPad()) {
615        for (MachineBasicBlock::const_livein_iterator I = MFI->livein_begin(),
616               E = MFI->livein_end(); I != E; ++I) {
617          if (TargetRegisterInfo::isPhysicalRegister(*I) &&
618              !PrInfo.isLiveOut(*I)) {
619            report("Live-in physical register is not live-out from predecessor",
620                   MFI);
621            *OS << "Register " << TRI->getName(*I)
622                << " is not live-out from MBB #" << (*PrI)->getNumber()
623                << ".\n";
624          }
625        }
626      }
627
628
629      // Verify dead-in virtual registers.
630      if (!allowVirtDoubleDefs) {
631        for (RegMap::iterator I = MInfo.vregsDeadIn.begin(),
632               E = MInfo.vregsDeadIn.end(); I != E; ++I) {
633          // DeadIn register must be in neither regsLiveOut or vregsPassed of
634          // any predecessor.
635          if (PrInfo.isLiveOut(I->first)) {
636            report("Live-in virtual register redefined", I->second);
637            *OS << "Register %reg" << I->first
638                << " was live-out from predecessor MBB #"
639                << (*PrI)->getNumber() << ".\n";
640          }
641        }
642      }
643    }
644  }
645
646  calcMinRegsPassed();
647
648  // With the minimal set of vregsPassed we can verify live-in virtual
649  // registers, including PHI instructions.
650  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
651       MFI != MFE; ++MFI) {
652    BBInfo &MInfo = MBBInfoMap[MFI];
653
654    // Skip unreachable MBBs.
655    if (!MInfo.reachable)
656      continue;
657
658    checkPHIOps(MFI);
659
660    for (MachineBasicBlock::const_pred_iterator PrI = MFI->pred_begin(),
661           PrE = MFI->pred_end(); PrI != PrE; ++PrI) {
662      BBInfo &PrInfo = MBBInfoMap[*PrI];
663      if (!PrInfo.reachable)
664        continue;
665
666      for (RegMap::iterator I = MInfo.vregsLiveIn.begin(),
667             E = MInfo.vregsLiveIn.end(); I != E; ++I) {
668        if (!PrInfo.isLiveOut(I->first)) {
669          report("Used virtual register is not live-in", I->second);
670          *OS << "Register %reg" << I->first
671              << " is not live-out from predecessor MBB #"
672              << (*PrI)->getNumber()
673              << ".\n";
674        }
675      }
676    }
677  }
678}
679