SelectionDAG.cpp revision 15e4b01920d6a0ffbe35d3e5aa88a4b42970b6a7
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Target/TargetLowering.h" 20#include <iostream> 21#include <set> 22#include <cmath> 23#include <algorithm> 24using namespace llvm; 25 26static bool isCommutativeBinOp(unsigned Opcode) { 27 switch (Opcode) { 28 case ISD::ADD: 29 case ISD::MUL: 30 case ISD::AND: 31 case ISD::OR: 32 case ISD::XOR: return true; 33 default: return false; // FIXME: Need commutative info for user ops! 34 } 35} 36 37static bool isAssociativeBinOp(unsigned Opcode) { 38 switch (Opcode) { 39 case ISD::ADD: 40 case ISD::MUL: 41 case ISD::AND: 42 case ISD::OR: 43 case ISD::XOR: return true; 44 default: return false; // FIXME: Need associative info for user ops! 45 } 46} 47 48static unsigned ExactLog2(uint64_t Val) { 49 unsigned Count = 0; 50 while (Val != 1) { 51 Val >>= 1; 52 ++Count; 53 } 54 return Count; 55} 56 57// isInvertibleForFree - Return true if there is no cost to emitting the logical 58// inverse of this node. 59static bool isInvertibleForFree(SDOperand N) { 60 if (isa<ConstantSDNode>(N.Val)) return true; 61 if (isa<SetCCSDNode>(N.Val) && N.Val->hasOneUse()) 62 return true; 63 return false; 64} 65 66 67/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 68/// when given the operation for (X op Y). 69ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 70 // To perform this operation, we just need to swap the L and G bits of the 71 // operation. 72 unsigned OldL = (Operation >> 2) & 1; 73 unsigned OldG = (Operation >> 1) & 1; 74 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 75 (OldL << 1) | // New G bit 76 (OldG << 2)); // New L bit. 77} 78 79/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 80/// 'op' is a valid SetCC operation. 81ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 82 unsigned Operation = Op; 83 if (isInteger) 84 Operation ^= 7; // Flip L, G, E bits, but not U. 85 else 86 Operation ^= 15; // Flip all of the condition bits. 87 if (Operation > ISD::SETTRUE2) 88 Operation &= ~8; // Don't let N and U bits get set. 89 return ISD::CondCode(Operation); 90} 91 92 93/// isSignedOp - For an integer comparison, return 1 if the comparison is a 94/// signed operation and 2 if the result is an unsigned comparison. Return zero 95/// if the operation does not depend on the sign of the input (setne and seteq). 96static int isSignedOp(ISD::CondCode Opcode) { 97 switch (Opcode) { 98 default: assert(0 && "Illegal integer setcc operation!"); 99 case ISD::SETEQ: 100 case ISD::SETNE: return 0; 101 case ISD::SETLT: 102 case ISD::SETLE: 103 case ISD::SETGT: 104 case ISD::SETGE: return 1; 105 case ISD::SETULT: 106 case ISD::SETULE: 107 case ISD::SETUGT: 108 case ISD::SETUGE: return 2; 109 } 110} 111 112/// getSetCCOrOperation - Return the result of a logical OR between different 113/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 114/// returns SETCC_INVALID if it is not possible to represent the resultant 115/// comparison. 116ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 117 bool isInteger) { 118 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 119 // Cannot fold a signed integer setcc with an unsigned integer setcc. 120 return ISD::SETCC_INVALID; 121 122 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 123 124 // If the N and U bits get set then the resultant comparison DOES suddenly 125 // care about orderedness, and is true when ordered. 126 if (Op > ISD::SETTRUE2) 127 Op &= ~16; // Clear the N bit. 128 return ISD::CondCode(Op); 129} 130 131/// getSetCCAndOperation - Return the result of a logical AND between different 132/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 133/// function returns zero if it is not possible to represent the resultant 134/// comparison. 135ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 136 bool isInteger) { 137 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 138 // Cannot fold a signed setcc with an unsigned setcc. 139 return ISD::SETCC_INVALID; 140 141 // Combine all of the condition bits. 142 return ISD::CondCode(Op1 & Op2); 143} 144 145const TargetMachine &SelectionDAG::getTarget() const { 146 return TLI.getTargetMachine(); 147} 148 149 150/// RemoveDeadNodes - This method deletes all unreachable nodes in the 151/// SelectionDAG, including nodes (like loads) that have uses of their token 152/// chain but no other uses and no side effect. If a node is passed in as an 153/// argument, it is used as the seed for node deletion. 154void SelectionDAG::RemoveDeadNodes(SDNode *N) { 155 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 156 157 // Create a dummy node (which is not added to allnodes), that adds a reference 158 // to the root node, preventing it from being deleted. 159 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 160 161 DeleteNodeIfDead(N, &AllNodeSet); 162 163 Restart: 164 unsigned NumNodes = AllNodeSet.size(); 165 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 166 I != E; ++I) { 167 // Try to delete this node. 168 DeleteNodeIfDead(*I, &AllNodeSet); 169 170 // If we actually deleted any nodes, do not use invalid iterators in 171 // AllNodeSet. 172 if (AllNodeSet.size() != NumNodes) 173 goto Restart; 174 } 175 176 // Restore AllNodes. 177 if (AllNodes.size() != NumNodes) 178 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 179 180 // If the root changed (e.g. it was a dead load, update the root). 181 setRoot(DummyNode->getOperand(0)); 182 183 // Now that we are done with the dummy node, delete it. 184 DummyNode->getOperand(0).Val->removeUser(DummyNode); 185 delete DummyNode; 186} 187 188void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 189 if (!N->use_empty()) 190 return; 191 192 // Okay, we really are going to delete this node. First take this out of the 193 // appropriate CSE map. 194 switch (N->getOpcode()) { 195 case ISD::Constant: 196 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 197 N->getValueType(0))); 198 break; 199 case ISD::ConstantFP: { 200 union { 201 double DV; 202 uint64_t IV; 203 }; 204 DV = cast<ConstantFPSDNode>(N)->getValue(); 205 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 206 break; 207 } 208 case ISD::GlobalAddress: 209 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 210 break; 211 case ISD::FrameIndex: 212 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 213 break; 214 case ISD::ConstantPool: 215 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 216 break; 217 case ISD::BasicBlock: 218 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 219 break; 220 case ISD::ExternalSymbol: 221 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 222 break; 223 case ISD::VALUETYPE: 224 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 225 break; 226 case ISD::LOAD: 227 Loads.erase(std::make_pair(N->getOperand(1), 228 std::make_pair(N->getOperand(0), 229 N->getValueType(0)))); 230 break; 231 case ISD::SETCC: 232 SetCCs.erase(std::make_pair(std::make_pair(N->getOperand(0), 233 N->getOperand(1)), 234 std::make_pair( 235 cast<SetCCSDNode>(N)->getCondition(), 236 N->getValueType(0)))); 237 break; 238 case ISD::TRUNCSTORE: 239 case ISD::EXTLOAD: 240 case ISD::SEXTLOAD: 241 case ISD::ZEXTLOAD: { 242 EVTStruct NN; 243 NN.Opcode = N->getOpcode(); 244 NN.VT = N->getValueType(0); 245 NN.EVT = cast<MVTSDNode>(N)->getExtraValueType(); 246 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 247 NN.Ops.push_back(N->getOperand(i)); 248 MVTSDNodes.erase(NN); 249 break; 250 } 251 default: 252 if (N->getNumOperands() == 1) 253 UnaryOps.erase(std::make_pair(N->getOpcode(), 254 std::make_pair(N->getOperand(0), 255 N->getValueType(0)))); 256 else if (N->getNumOperands() == 2) 257 BinaryOps.erase(std::make_pair(N->getOpcode(), 258 std::make_pair(N->getOperand(0), 259 N->getOperand(1)))); 260 else if (N->getNumValues() == 1) { 261 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 262 OneResultNodes.erase(std::make_pair(N->getOpcode(), 263 std::make_pair(N->getValueType(0), 264 Ops))); 265 } else { 266 // Remove the node from the ArbitraryNodes map. 267 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 268 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 269 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 270 std::make_pair(RV, Ops))); 271 } 272 break; 273 } 274 275 // Next, brutally remove the operand list. 276 while (!N->Operands.empty()) { 277 SDNode *O = N->Operands.back().Val; 278 N->Operands.pop_back(); 279 O->removeUser(N); 280 281 // Now that we removed this operand, see if there are no uses of it left. 282 DeleteNodeIfDead(O, NodeSet); 283 } 284 285 // Remove the node from the nodes set and delete it. 286 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 287 AllNodeSet.erase(N); 288 289 // Now that the node is gone, check to see if any of the operands of this node 290 // are dead now. 291 delete N; 292} 293 294 295SelectionDAG::~SelectionDAG() { 296 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 297 delete AllNodes[i]; 298} 299 300SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 301 if (Op.getValueType() == VT) return Op; 302 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 303 return getNode(ISD::AND, Op.getValueType(), Op, 304 getConstant(Imm, Op.getValueType())); 305} 306 307SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 308 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 309 // Mask out any bits that are not valid for this constant. 310 if (VT != MVT::i64) 311 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 312 313 SDNode *&N = Constants[std::make_pair(Val, VT)]; 314 if (N) return SDOperand(N, 0); 315 N = new ConstantSDNode(Val, VT); 316 AllNodes.push_back(N); 317 return SDOperand(N, 0); 318} 319 320SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 321 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 322 if (VT == MVT::f32) 323 Val = (float)Val; // Mask out extra precision. 324 325 // Do the map lookup using the actual bit pattern for the floating point 326 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 327 // we don't have issues with SNANs. 328 union { 329 double DV; 330 uint64_t IV; 331 }; 332 333 DV = Val; 334 335 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 336 if (N) return SDOperand(N, 0); 337 N = new ConstantFPSDNode(Val, VT); 338 AllNodes.push_back(N); 339 return SDOperand(N, 0); 340} 341 342 343 344SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 345 MVT::ValueType VT) { 346 SDNode *&N = GlobalValues[GV]; 347 if (N) return SDOperand(N, 0); 348 N = new GlobalAddressSDNode(GV,VT); 349 AllNodes.push_back(N); 350 return SDOperand(N, 0); 351} 352 353SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 354 SDNode *&N = FrameIndices[FI]; 355 if (N) return SDOperand(N, 0); 356 N = new FrameIndexSDNode(FI, VT); 357 AllNodes.push_back(N); 358 return SDOperand(N, 0); 359} 360 361SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 362 SDNode *N = ConstantPoolIndices[CPIdx]; 363 if (N) return SDOperand(N, 0); 364 N = new ConstantPoolSDNode(CPIdx, VT); 365 AllNodes.push_back(N); 366 return SDOperand(N, 0); 367} 368 369SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 370 SDNode *&N = BBNodes[MBB]; 371 if (N) return SDOperand(N, 0); 372 N = new BasicBlockSDNode(MBB); 373 AllNodes.push_back(N); 374 return SDOperand(N, 0); 375} 376 377SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 378 if ((unsigned)VT >= ValueTypeNodes.size()) 379 ValueTypeNodes.resize(VT+1); 380 if (ValueTypeNodes[VT] == 0) { 381 ValueTypeNodes[VT] = new VTSDNode(VT); 382 AllNodes.push_back(ValueTypeNodes[VT]); 383 } 384 385 return SDOperand(ValueTypeNodes[VT], 0); 386} 387 388SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 389 SDNode *&N = ExternalSymbols[Sym]; 390 if (N) return SDOperand(N, 0); 391 N = new ExternalSymbolSDNode(Sym, VT); 392 AllNodes.push_back(N); 393 return SDOperand(N, 0); 394} 395 396SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT, 397 SDOperand N1, SDOperand N2) { 398 // These setcc operations always fold. 399 switch (Cond) { 400 default: break; 401 case ISD::SETFALSE: 402 case ISD::SETFALSE2: return getConstant(0, VT); 403 case ISD::SETTRUE: 404 case ISD::SETTRUE2: return getConstant(1, VT); 405 } 406 407 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 408 uint64_t C2 = N2C->getValue(); 409 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 410 uint64_t C1 = N1C->getValue(); 411 412 // Sign extend the operands if required 413 if (ISD::isSignedIntSetCC(Cond)) { 414 C1 = N1C->getSignExtended(); 415 C2 = N2C->getSignExtended(); 416 } 417 418 switch (Cond) { 419 default: assert(0 && "Unknown integer setcc!"); 420 case ISD::SETEQ: return getConstant(C1 == C2, VT); 421 case ISD::SETNE: return getConstant(C1 != C2, VT); 422 case ISD::SETULT: return getConstant(C1 < C2, VT); 423 case ISD::SETUGT: return getConstant(C1 > C2, VT); 424 case ISD::SETULE: return getConstant(C1 <= C2, VT); 425 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 426 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 427 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 428 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 429 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 430 } 431 } else { 432 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 433 // the comparison on the input. 434 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 435 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 436 437 // If the comparison constant has bits in the upper part, the 438 // zero-extended value could never match. 439 if (C2 & (~0ULL << InSize)) { 440 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 441 switch (Cond) { 442 case ISD::SETUGT: 443 case ISD::SETUGE: 444 case ISD::SETEQ: return getConstant(0, VT); 445 case ISD::SETULT: 446 case ISD::SETULE: 447 case ISD::SETNE: return getConstant(1, VT); 448 case ISD::SETGT: 449 case ISD::SETGE: 450 // True if the sign bit of C2 is set. 451 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 452 case ISD::SETLT: 453 case ISD::SETLE: 454 // True if the sign bit of C2 isn't set. 455 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 456 default: 457 break; 458 } 459 } 460 461 // Otherwise, we can perform the comparison with the low bits. 462 switch (Cond) { 463 case ISD::SETEQ: 464 case ISD::SETNE: 465 case ISD::SETUGT: 466 case ISD::SETUGE: 467 case ISD::SETULT: 468 case ISD::SETULE: 469 return getSetCC(Cond, VT, N1.getOperand(0), 470 getConstant(C2, N1.getOperand(0).getValueType())); 471 default: 472 break; // todo, be more careful with signed comparisons 473 } 474 } 475 476 477 uint64_t MinVal, MaxVal; 478 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 479 if (ISD::isSignedIntSetCC(Cond)) { 480 MinVal = 1ULL << (OperandBitSize-1); 481 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 482 MaxVal = ~0ULL >> (65-OperandBitSize); 483 else 484 MaxVal = 0; 485 } else { 486 MinVal = 0; 487 MaxVal = ~0ULL >> (64-OperandBitSize); 488 } 489 490 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 491 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 492 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 493 --C2; // X >= C1 --> X > (C1-1) 494 Cond = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; 495 N2 = getConstant(C2, N2.getValueType()); 496 N2C = cast<ConstantSDNode>(N2.Val); 497 } 498 499 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 500 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 501 ++C2; // X <= C1 --> X < (C1+1) 502 Cond = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; 503 N2 = getConstant(C2, N2.getValueType()); 504 N2C = cast<ConstantSDNode>(N2.Val); 505 } 506 507 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 508 return getConstant(0, VT); // X < MIN --> false 509 510 // Canonicalize setgt X, Min --> setne X, Min 511 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 512 return getSetCC(ISD::SETNE, VT, N1, N2); 513 514 // If we have setult X, 1, turn it into seteq X, 0 515 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 516 return getSetCC(ISD::SETEQ, VT, N1, 517 getConstant(MinVal, N1.getValueType())); 518 // If we have setugt X, Max-1, turn it into seteq X, Max 519 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 520 return getSetCC(ISD::SETEQ, VT, N1, 521 getConstant(MaxVal, N1.getValueType())); 522 523 // If we have "setcc X, C1", check to see if we can shrink the immediate 524 // by changing cc. 525 526 // SETUGT X, SINTMAX -> SETLT X, 0 527 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 528 C2 == (~0ULL >> (65-OperandBitSize))) 529 return getSetCC(ISD::SETLT, VT, N1, getConstant(0, N2.getValueType())); 530 531 // FIXME: Implement the rest of these. 532 533 534 // Fold bit comparisons when we can. 535 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 536 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 537 if (ConstantSDNode *AndRHS = 538 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 539 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 540 // Perform the xform if the AND RHS is a single bit. 541 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 542 return getNode(ISD::SRL, VT, N1, 543 getConstant(ExactLog2(AndRHS->getValue()), 544 TLI.getShiftAmountTy())); 545 } 546 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 547 // (X & 8) == 8 --> (X & 8) >> 3 548 // Perform the xform if C2 is a single bit. 549 if ((C2 & (C2-1)) == 0) { 550 return getNode(ISD::SRL, VT, N1, 551 getConstant(ExactLog2(C2),TLI.getShiftAmountTy())); 552 } 553 } 554 } 555 } 556 } else if (isa<ConstantSDNode>(N1.Val)) { 557 // Ensure that the constant occurs on the RHS. 558 return getSetCC(ISD::getSetCCSwappedOperands(Cond), VT, N2, N1); 559 } 560 561 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 562 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 563 double C1 = N1C->getValue(), C2 = N2C->getValue(); 564 565 switch (Cond) { 566 default: break; // FIXME: Implement the rest of these! 567 case ISD::SETEQ: return getConstant(C1 == C2, VT); 568 case ISD::SETNE: return getConstant(C1 != C2, VT); 569 case ISD::SETLT: return getConstant(C1 < C2, VT); 570 case ISD::SETGT: return getConstant(C1 > C2, VT); 571 case ISD::SETLE: return getConstant(C1 <= C2, VT); 572 case ISD::SETGE: return getConstant(C1 >= C2, VT); 573 } 574 } else { 575 // Ensure that the constant occurs on the RHS. 576 Cond = ISD::getSetCCSwappedOperands(Cond); 577 std::swap(N1, N2); 578 } 579 580 if (N1 == N2) { 581 // We can always fold X == Y for integer setcc's. 582 if (MVT::isInteger(N1.getValueType())) 583 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 584 unsigned UOF = ISD::getUnorderedFlavor(Cond); 585 if (UOF == 2) // FP operators that are undefined on NaNs. 586 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 587 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 588 return getConstant(UOF, VT); 589 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 590 // if it is not already. 591 Cond = UOF == 0 ? ISD::SETUO : ISD::SETO; 592 } 593 594 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 595 MVT::isInteger(N1.getValueType())) { 596 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 597 N1.getOpcode() == ISD::XOR) { 598 // Simplify (X+Y) == (X+Z) --> Y == Z 599 if (N1.getOpcode() == N2.getOpcode()) { 600 if (N1.getOperand(0) == N2.getOperand(0)) 601 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(1)); 602 if (N1.getOperand(1) == N2.getOperand(1)) 603 return getSetCC(Cond, VT, N1.getOperand(0), N2.getOperand(0)); 604 if (isCommutativeBinOp(N1.getOpcode())) { 605 // If X op Y == Y op X, try other combinations. 606 if (N1.getOperand(0) == N2.getOperand(1)) 607 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(0)); 608 if (N1.getOperand(1) == N2.getOperand(0)) 609 return getSetCC(Cond, VT, N1.getOperand(1), N2.getOperand(1)); 610 } 611 } 612 613 // FIXME: move this stuff to the DAG Combiner when it exists! 614 615 // Simplify (X+Z) == X --> Z == 0 616 if (N1.getOperand(0) == N2) 617 return getSetCC(Cond, VT, N1.getOperand(1), 618 getConstant(0, N1.getValueType())); 619 if (N1.getOperand(1) == N2) { 620 if (isCommutativeBinOp(N1.getOpcode())) 621 return getSetCC(Cond, VT, N1.getOperand(0), 622 getConstant(0, N1.getValueType())); 623 else { 624 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 625 // (Z-X) == X --> Z == X<<1 626 return getSetCC(Cond, VT, N1.getOperand(0), 627 getNode(ISD::SHL, N2.getValueType(), 628 N2, getConstant(1, TLI.getShiftAmountTy()))); 629 } 630 } 631 } 632 633 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 634 N2.getOpcode() == ISD::XOR) { 635 // Simplify X == (X+Z) --> Z == 0 636 if (N2.getOperand(0) == N1) 637 return getSetCC(Cond, VT, N2.getOperand(1), 638 getConstant(0, N2.getValueType())); 639 else if (N2.getOperand(1) == N1) 640 return getSetCC(Cond, VT, N2.getOperand(0), 641 getConstant(0, N2.getValueType())); 642 } 643 } 644 645 // Fold away ALL boolean setcc's. 646 if (N1.getValueType() == MVT::i1) { 647 switch (Cond) { 648 default: assert(0 && "Unknown integer setcc!"); 649 case ISD::SETEQ: // X == Y -> (X^Y)^1 650 N1 = getNode(ISD::XOR, MVT::i1, 651 getNode(ISD::XOR, MVT::i1, N1, N2), 652 getConstant(1, MVT::i1)); 653 break; 654 case ISD::SETNE: // X != Y --> (X^Y) 655 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 656 break; 657 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 658 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 659 N1 = getNode(ISD::AND, MVT::i1, N2, 660 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 661 break; 662 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 663 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 664 N1 = getNode(ISD::AND, MVT::i1, N1, 665 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 666 break; 667 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 668 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 669 N1 = getNode(ISD::OR, MVT::i1, N2, 670 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 671 break; 672 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 673 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 674 N1 = getNode(ISD::OR, MVT::i1, N1, 675 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 676 break; 677 } 678 if (VT != MVT::i1) 679 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 680 return N1; 681 } 682 683 684 SetCCSDNode *&N = SetCCs[std::make_pair(std::make_pair(N1, N2), 685 std::make_pair(Cond, VT))]; 686 if (N) return SDOperand(N, 0); 687 N = new SetCCSDNode(Cond, N1, N2); 688 N->setValueTypes(VT); 689 AllNodes.push_back(N); 690 return SDOperand(N, 0); 691} 692 693 694 695/// getNode - Gets or creates the specified node. 696/// 697SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 698 SDNode *N = new SDNode(Opcode, VT); 699 AllNodes.push_back(N); 700 return SDOperand(N, 0); 701} 702 703SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 704 SDOperand Operand) { 705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 706 uint64_t Val = C->getValue(); 707 switch (Opcode) { 708 default: break; 709 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 710 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 711 case ISD::TRUNCATE: return getConstant(Val, VT); 712 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 713 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 714 } 715 } 716 717 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 718 switch (Opcode) { 719 case ISD::FNEG: 720 return getConstantFP(-C->getValue(), VT); 721 case ISD::FP_ROUND: 722 case ISD::FP_EXTEND: 723 return getConstantFP(C->getValue(), VT); 724 case ISD::FP_TO_SINT: 725 return getConstant((int64_t)C->getValue(), VT); 726 case ISD::FP_TO_UINT: 727 return getConstant((uint64_t)C->getValue(), VT); 728 } 729 730 unsigned OpOpcode = Operand.Val->getOpcode(); 731 switch (Opcode) { 732 case ISD::TokenFactor: 733 return Operand; // Factor of one node? No factor. 734 case ISD::SIGN_EXTEND: 735 if (Operand.getValueType() == VT) return Operand; // noop extension 736 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 737 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 738 break; 739 case ISD::ZERO_EXTEND: 740 if (Operand.getValueType() == VT) return Operand; // noop extension 741 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 742 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 743 break; 744 case ISD::TRUNCATE: 745 if (Operand.getValueType() == VT) return Operand; // noop truncate 746 if (OpOpcode == ISD::TRUNCATE) 747 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 748 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 749 // If the source is smaller than the dest, we still need an extend. 750 if (Operand.Val->getOperand(0).getValueType() < VT) 751 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 752 else if (Operand.Val->getOperand(0).getValueType() > VT) 753 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 754 else 755 return Operand.Val->getOperand(0); 756 } 757 break; 758 case ISD::FNEG: 759 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 760 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 761 Operand.Val->getOperand(0)); 762 if (OpOpcode == ISD::FNEG) // --X -> X 763 return Operand.Val->getOperand(0); 764 break; 765 case ISD::FABS: 766 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 767 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 768 break; 769 } 770 771 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 772 if (N) return SDOperand(N, 0); 773 N = new SDNode(Opcode, Operand); 774 N->setValueTypes(VT); 775 AllNodes.push_back(N); 776 return SDOperand(N, 0); 777} 778 779/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 780/// this predicate to simplify operations downstream. V and Mask are known to 781/// be the same type. 782static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 783 const TargetLowering &TLI) { 784 unsigned SrcBits; 785 if (Mask == 0) return true; 786 787 // If we know the result of a setcc has the top bits zero, use this info. 788 switch (Op.getOpcode()) { 789 case ISD::UNDEF: 790 return true; 791 case ISD::Constant: 792 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 793 794 case ISD::SETCC: 795 return ((Mask & 1) == 0) && 796 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 797 798 case ISD::ZEXTLOAD: 799 SrcBits = MVT::getSizeInBits(cast<MVTSDNode>(Op)->getExtraValueType()); 800 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 801 case ISD::ZERO_EXTEND: 802 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 803 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 804 805 case ISD::AND: 806 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 807 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 808 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 809 810 // FALL THROUGH 811 case ISD::OR: 812 case ISD::XOR: 813 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 814 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 815 case ISD::SELECT: 816 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 817 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 818 819 case ISD::SRL: 820 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 821 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 822 uint64_t NewVal = Mask << ShAmt->getValue(); 823 SrcBits = MVT::getSizeInBits(Op.getValueType()); 824 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 825 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 826 } 827 return false; 828 case ISD::SHL: 829 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 830 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 831 uint64_t NewVal = Mask >> ShAmt->getValue(); 832 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 833 } 834 return false; 835 // TODO we could handle some SRA cases here. 836 default: break; 837 } 838 839 return false; 840} 841 842 843 844SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 845 SDOperand N1, SDOperand N2) { 846#ifndef NDEBUG 847 switch (Opcode) { 848 case ISD::TokenFactor: 849 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 850 N2.getValueType() == MVT::Other && "Invalid token factor!"); 851 break; 852 case ISD::AND: 853 case ISD::OR: 854 case ISD::XOR: 855 case ISD::UDIV: 856 case ISD::UREM: 857 case ISD::MULHU: 858 case ISD::MULHS: 859 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 860 // fall through 861 case ISD::ADD: 862 case ISD::SUB: 863 case ISD::MUL: 864 case ISD::SDIV: 865 case ISD::SREM: 866 assert(N1.getValueType() == N2.getValueType() && 867 N1.getValueType() == VT && "Binary operator types must match!"); 868 break; 869 870 case ISD::SHL: 871 case ISD::SRA: 872 case ISD::SRL: 873 assert(VT == N1.getValueType() && 874 "Shift operators return type must be the same as their first arg"); 875 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 876 VT != MVT::i1 && "Shifts only work on integers"); 877 break; 878 case ISD::FP_ROUND_INREG: { 879 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 880 assert(VT == N1.getValueType() && "Not an inreg round!"); 881 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 882 "Cannot FP_ROUND_INREG integer types"); 883 assert(EVT <= VT && "Not rounding down!"); 884 break; 885 } 886 case ISD::SIGN_EXTEND_INREG: { 887 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 888 assert(VT == N1.getValueType() && "Not an inreg extend!"); 889 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 890 "Cannot *_EXTEND_INREG FP types"); 891 assert(EVT <= VT && "Not extending!"); 892 } 893 894 default: break; 895 } 896#endif 897 898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 899 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 900 if (N1C) { 901 if (N2C) { 902 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 903 switch (Opcode) { 904 case ISD::ADD: return getConstant(C1 + C2, VT); 905 case ISD::SUB: return getConstant(C1 - C2, VT); 906 case ISD::MUL: return getConstant(C1 * C2, VT); 907 case ISD::UDIV: 908 if (C2) return getConstant(C1 / C2, VT); 909 break; 910 case ISD::UREM : 911 if (C2) return getConstant(C1 % C2, VT); 912 break; 913 case ISD::SDIV : 914 if (C2) return getConstant(N1C->getSignExtended() / 915 N2C->getSignExtended(), VT); 916 break; 917 case ISD::SREM : 918 if (C2) return getConstant(N1C->getSignExtended() % 919 N2C->getSignExtended(), VT); 920 break; 921 case ISD::AND : return getConstant(C1 & C2, VT); 922 case ISD::OR : return getConstant(C1 | C2, VT); 923 case ISD::XOR : return getConstant(C1 ^ C2, VT); 924 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 925 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 926 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 927 default: break; 928 } 929 930 } else { // Cannonicalize constant to RHS if commutative 931 if (isCommutativeBinOp(Opcode)) { 932 std::swap(N1C, N2C); 933 std::swap(N1, N2); 934 } 935 } 936 937 switch (Opcode) { 938 default: break; 939 case ISD::SHL: // shl 0, X -> 0 940 if (N1C->isNullValue()) return N1; 941 break; 942 case ISD::SRL: // srl 0, X -> 0 943 if (N1C->isNullValue()) return N1; 944 break; 945 case ISD::SRA: // sra -1, X -> -1 946 if (N1C->isAllOnesValue()) return N1; 947 break; 948 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 949 // Extending a constant? Just return the extended constant. 950 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 951 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 952 } 953 } 954 955 if (N2C) { 956 uint64_t C2 = N2C->getValue(); 957 958 switch (Opcode) { 959 case ISD::ADD: 960 if (!C2) return N1; // add X, 0 -> X 961 break; 962 case ISD::SUB: 963 if (!C2) return N1; // sub X, 0 -> X 964 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 965 case ISD::MUL: 966 if (!C2) return N2; // mul X, 0 -> 0 967 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 968 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 969 970 // FIXME: Move this to the DAG combiner when it exists. 971 if ((C2 & C2-1) == 0) { 972 SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy()); 973 return getNode(ISD::SHL, VT, N1, ShAmt); 974 } 975 break; 976 977 case ISD::MULHU: 978 case ISD::MULHS: 979 if (!C2) return N2; // mul X, 0 -> 0 980 981 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 982 return getConstant(0, VT); 983 984 // Many others could be handled here, including -1, powers of 2, etc. 985 break; 986 987 case ISD::UDIV: 988 // FIXME: Move this to the DAG combiner when it exists. 989 if ((C2 & C2-1) == 0 && C2) { 990 SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy()); 991 return getNode(ISD::SRL, VT, N1, ShAmt); 992 } 993 break; 994 995 case ISD::SHL: 996 case ISD::SRL: 997 case ISD::SRA: 998 // If the shift amount is bigger than the size of the data, then all the 999 // bits are shifted out. Simplify to undef. 1000 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1001 return getNode(ISD::UNDEF, N1.getValueType()); 1002 } 1003 if (C2 == 0) return N1; 1004 1005 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1006 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1007 unsigned OpSAC = OpSA->getValue(); 1008 if (N1.getOpcode() == ISD::SHL) { 1009 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1010 return getConstant(0, N1.getValueType()); 1011 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1012 getConstant(C2+OpSAC, N2.getValueType())); 1013 } else if (N1.getOpcode() == ISD::SRL) { 1014 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1015 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1016 getConstant(~0ULL << OpSAC, VT)); 1017 if (C2 > OpSAC) { 1018 return getNode(ISD::SHL, VT, Mask, 1019 getConstant(C2-OpSAC, N2.getValueType())); 1020 } else { 1021 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1022 return getNode(ISD::SRL, VT, Mask, 1023 getConstant(OpSAC-C2, N2.getValueType())); 1024 } 1025 } else if (N1.getOpcode() == ISD::SRA) { 1026 // if C1 == C2, just mask out low bits. 1027 if (C2 == OpSAC) 1028 return getNode(ISD::AND, VT, N1.getOperand(0), 1029 getConstant(~0ULL << C2, VT)); 1030 } 1031 } 1032 break; 1033 1034 case ISD::AND: 1035 if (!C2) return N2; // X and 0 -> 0 1036 if (N2C->isAllOnesValue()) 1037 return N1; // X and -1 -> X 1038 1039 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1040 return getConstant(0, VT); 1041 1042 { 1043 uint64_t NotC2 = ~C2; 1044 if (VT != MVT::i64) 1045 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1046 1047 if (MaskedValueIsZero(N1, NotC2, TLI)) 1048 return N1; // if (X & ~C2) -> 0, the and is redundant 1049 } 1050 1051 // FIXME: Should add a corresponding version of this for 1052 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1053 // we don't have yet. 1054 1055 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1056 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1057 // If we are masking out the part of our input that was extended, just 1058 // mask the input to the extension directly. 1059 unsigned ExtendBits = 1060 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1061 if ((C2 & (~0ULL << ExtendBits)) == 0) 1062 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1063 } 1064 break; 1065 case ISD::OR: 1066 if (!C2)return N1; // X or 0 -> X 1067 if (N2C->isAllOnesValue()) 1068 return N2; // X or -1 -> -1 1069 break; 1070 case ISD::XOR: 1071 if (!C2) return N1; // X xor 0 -> X 1072 if (N2C->isAllOnesValue()) { 1073 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N1.Val)){ 1074 // !(X op Y) -> (X !op Y) 1075 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1076 return getSetCC(ISD::getSetCCInverse(SetCC->getCondition(),isInteger), 1077 SetCC->getValueType(0), 1078 SetCC->getOperand(0), SetCC->getOperand(1)); 1079 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1080 SDNode *Op = N1.Val; 1081 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1082 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1083 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1084 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1085 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1086 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1087 if (Op->getOpcode() == ISD::AND) 1088 return getNode(ISD::OR, VT, LHS, RHS); 1089 return getNode(ISD::AND, VT, LHS, RHS); 1090 } 1091 } 1092 // X xor -1 -> not(x) ? 1093 } 1094 break; 1095 } 1096 1097 // Reassociate ((X op C1) op C2) if possible. 1098 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1099 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1100 return getNode(Opcode, VT, N1.Val->getOperand(0), 1101 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1102 } 1103 1104 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1105 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1106 if (N1CFP) { 1107 if (N2CFP) { 1108 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1109 switch (Opcode) { 1110 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1111 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1112 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1113 case ISD::SDIV: 1114 if (C2) return getConstantFP(C1 / C2, VT); 1115 break; 1116 case ISD::SREM : 1117 if (C2) return getConstantFP(fmod(C1, C2), VT); 1118 break; 1119 default: break; 1120 } 1121 1122 } else { // Cannonicalize constant to RHS if commutative 1123 if (isCommutativeBinOp(Opcode)) { 1124 std::swap(N1CFP, N2CFP); 1125 std::swap(N1, N2); 1126 } 1127 } 1128 1129 if (Opcode == ISD::FP_ROUND_INREG) 1130 return getNode(ISD::FP_EXTEND, VT, 1131 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1132 } 1133 1134 // Finally, fold operations that do not require constants. 1135 switch (Opcode) { 1136 case ISD::TokenFactor: 1137 if (N1.getOpcode() == ISD::EntryToken) 1138 return N2; 1139 if (N2.getOpcode() == ISD::EntryToken) 1140 return N1; 1141 break; 1142 1143 case ISD::AND: 1144 case ISD::OR: 1145 if (SetCCSDNode *LHS = dyn_cast<SetCCSDNode>(N1.Val)) 1146 if (SetCCSDNode *RHS = dyn_cast<SetCCSDNode>(N2.Val)) { 1147 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1148 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1149 ISD::CondCode Op2 = RHS->getCondition(); 1150 1151 if (LR == RR && isa<ConstantSDNode>(LR) && 1152 Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) { 1153 // (X != 0) | (Y != 0) -> (X|Y != 0) 1154 // (X == 0) & (Y == 0) -> (X|Y == 0) 1155 // (X < 0) | (Y < 0) -> (X|Y < 0) 1156 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1157 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1158 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1159 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1160 return getSetCC(Op2, VT, 1161 getNode(ISD::OR, LR.getValueType(), LL, RL), LR); 1162 1163 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1164 // (X == -1) & (Y == -1) -> (X&Y == -1) 1165 // (X != -1) | (Y != -1) -> (X&Y != -1) 1166 // (X > -1) | (Y > -1) -> (X&Y > -1) 1167 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1168 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1169 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1170 return getSetCC(Op2, VT, 1171 getNode(ISD::AND, LR.getValueType(), LL, RL), LR); 1172 // (X > -1) & (Y > -1) -> (X|Y > -1) 1173 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1174 return getSetCC(Op2, VT, 1175 getNode(ISD::OR, LR.getValueType(), LL, RL), LR); 1176 } 1177 } 1178 1179 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1180 if (LL == RR && LR == RL) { 1181 Op2 = ISD::getSetCCSwappedOperands(Op2); 1182 goto MatchedBackwards; 1183 } 1184 1185 if (LL == RL && LR == RR) { 1186 MatchedBackwards: 1187 ISD::CondCode Result; 1188 bool isInteger = MVT::isInteger(LL.getValueType()); 1189 if (Opcode == ISD::OR) 1190 Result = ISD::getSetCCOrOperation(LHS->getCondition(), Op2, 1191 isInteger); 1192 else 1193 Result = ISD::getSetCCAndOperation(LHS->getCondition(), Op2, 1194 isInteger); 1195 if (Result != ISD::SETCC_INVALID) 1196 return getSetCC(Result, LHS->getValueType(0), LL, LR); 1197 } 1198 } 1199 1200 // and/or zext(a), zext(b) -> zext(and/or a, b) 1201 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1202 N2.getOpcode() == ISD::ZERO_EXTEND && 1203 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1204 return getNode(ISD::ZERO_EXTEND, VT, 1205 getNode(Opcode, N1.getOperand(0).getValueType(), 1206 N1.getOperand(0), N2.getOperand(0))); 1207 break; 1208 case ISD::XOR: 1209 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1210 break; 1211 case ISD::ADD: 1212 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1213 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1214 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1215 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1216 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1217 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1218 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1219 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1220 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1221 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1222 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1223 !MVT::isFloatingPoint(N2.getValueType())) 1224 return N2.Val->getOperand(0); // A+(B-A) -> B 1225 break; 1226 case ISD::SUB: 1227 if (N1.getOpcode() == ISD::ADD) { 1228 if (N1.Val->getOperand(0) == N2 && 1229 !MVT::isFloatingPoint(N2.getValueType())) 1230 return N1.Val->getOperand(1); // (A+B)-A == B 1231 if (N1.Val->getOperand(1) == N2 && 1232 !MVT::isFloatingPoint(N2.getValueType())) 1233 return N1.Val->getOperand(0); // (A+B)-B == A 1234 } 1235 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1236 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1237 break; 1238 case ISD::FP_ROUND_INREG: 1239 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1240 break; 1241 case ISD::SIGN_EXTEND_INREG: { 1242 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1243 if (EVT == VT) return N1; // Not actually extending 1244 1245 // If we are sign extending an extension, use the original source. 1246 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1247 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1248 return N1; 1249 1250 // If we are sign extending a sextload, return just the load. 1251 if (N1.getOpcode() == ISD::SEXTLOAD) 1252 if (cast<MVTSDNode>(N1)->getExtraValueType() <= EVT) 1253 return N1; 1254 1255 // If we are extending the result of a setcc, and we already know the 1256 // contents of the top bits, eliminate the extension. 1257 if (N1.getOpcode() == ISD::SETCC && 1258 TLI.getSetCCResultContents() == 1259 TargetLowering::ZeroOrNegativeOneSetCCResult) 1260 return N1; 1261 1262 // If we are sign extending the result of an (and X, C) operation, and we 1263 // know the extended bits are zeros already, don't do the extend. 1264 if (N1.getOpcode() == ISD::AND) 1265 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1266 uint64_t Mask = N1C->getValue(); 1267 unsigned NumBits = MVT::getSizeInBits(EVT); 1268 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1269 return N1; 1270 } 1271 break; 1272 } 1273 1274 // FIXME: figure out how to safely handle things like 1275 // int foo(int x) { return 1 << (x & 255); } 1276 // int bar() { return foo(256); } 1277#if 0 1278 case ISD::SHL: 1279 case ISD::SRL: 1280 case ISD::SRA: 1281 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1282 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1283 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1284 else if (N2.getOpcode() == ISD::AND) 1285 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1286 // If the and is only masking out bits that cannot effect the shift, 1287 // eliminate the and. 1288 unsigned NumBits = MVT::getSizeInBits(VT); 1289 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1290 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1291 } 1292 break; 1293#endif 1294 } 1295 1296 // Memoize this node if possible. 1297 SDNode *N; 1298 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1299 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1300 if (BON) return SDOperand(BON, 0); 1301 1302 BON = N = new SDNode(Opcode, N1, N2); 1303 } else { 1304 N = new SDNode(Opcode, N1, N2); 1305 } 1306 1307 N->setValueTypes(VT); 1308 AllNodes.push_back(N); 1309 return SDOperand(N, 0); 1310} 1311 1312// setAdjCallChain - This method changes the token chain of an 1313// CALLSEQ_START/END node to be the specified operand. 1314void SDNode::setAdjCallChain(SDOperand N) { 1315 assert(N.getValueType() == MVT::Other); 1316 assert((getOpcode() == ISD::CALLSEQ_START || 1317 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1318 1319 Operands[0].Val->removeUser(this); 1320 Operands[0] = N; 1321 N.Val->Uses.push_back(this); 1322} 1323 1324 1325 1326SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1327 SDOperand Chain, SDOperand Ptr, 1328 SDOperand SV) { 1329 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1330 if (N) return SDOperand(N, 0); 1331 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1332 1333 // Loads have a token chain. 1334 N->setValueTypes(VT, MVT::Other); 1335 AllNodes.push_back(N); 1336 return SDOperand(N, 0); 1337} 1338 1339SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1340 SDOperand N1, SDOperand N2, SDOperand N3) { 1341 // Perform various simplifications. 1342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1343 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1344 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1345 switch (Opcode) { 1346 case ISD::SELECT: 1347 if (N1C) 1348 if (N1C->getValue()) 1349 return N2; // select true, X, Y -> X 1350 else 1351 return N3; // select false, X, Y -> Y 1352 1353 if (N2 == N3) return N2; // select C, X, X -> X 1354 1355 if (VT == MVT::i1) { // Boolean SELECT 1356 if (N2C) { 1357 if (N2C->getValue()) // select C, 1, X -> C | X 1358 return getNode(ISD::OR, VT, N1, N3); 1359 else // select C, 0, X -> ~C & X 1360 return getNode(ISD::AND, VT, 1361 getNode(ISD::XOR, N1.getValueType(), N1, 1362 getConstant(1, N1.getValueType())), N3); 1363 } else if (N3C) { 1364 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1365 return getNode(ISD::OR, VT, 1366 getNode(ISD::XOR, N1.getValueType(), N1, 1367 getConstant(1, N1.getValueType())), N2); 1368 else // select C, X, 0 -> C & X 1369 return getNode(ISD::AND, VT, N1, N2); 1370 } 1371 1372 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1373 return getNode(ISD::OR, VT, N1, N3); 1374 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1375 return getNode(ISD::AND, VT, N1, N2); 1376 } 1377 1378 // If this is a selectcc, check to see if we can simplify the result. 1379 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N1)) { 1380 if (ConstantFPSDNode *CFP = 1381 dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1))) 1382 if (CFP->getValue() == 0.0) { // Allow either -0.0 or 0.0 1383 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1384 if ((SetCC->getCondition() == ISD::SETGE || 1385 SetCC->getCondition() == ISD::SETGT) && 1386 N2 == SetCC->getOperand(0) && N3.getOpcode() == ISD::FNEG && 1387 N3.getOperand(0) == N2) 1388 return getNode(ISD::FABS, VT, N2); 1389 1390 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1391 if ((SetCC->getCondition() == ISD::SETLT || 1392 SetCC->getCondition() == ISD::SETLE) && 1393 N3 == SetCC->getOperand(0) && N2.getOpcode() == ISD::FNEG && 1394 N2.getOperand(0) == N3) 1395 return getNode(ISD::FABS, VT, N3); 1396 } 1397 // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1), A 1398 if (ConstantSDNode *CN = 1399 dyn_cast<ConstantSDNode>(SetCC->getOperand(1))) 1400 if (CN->getValue() == 0 && N3C && N3C->getValue() == 0) 1401 if (SetCC->getCondition() == ISD::SETLT) { 1402 MVT::ValueType XType = SetCC->getOperand(0).getValueType(); 1403 MVT::ValueType AType = N2.getValueType(); 1404 if (XType >= AType) { 1405 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1406 // single-bit constant. FIXME: remove once the dag combiner 1407 // exists. 1408 if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2)) 1409 if ((AC->getValue() & (AC->getValue()-1)) == 0) { 1410 unsigned ShCtV = ExactLog2(AC->getValue()); 1411 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1412 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 1413 SDOperand Shift = getNode(ISD::SRL, XType, 1414 SetCC->getOperand(0), ShCt); 1415 if (XType > AType) 1416 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1417 return getNode(ISD::AND, AType, Shift, N2); 1418 } 1419 1420 1421 SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0), 1422 getConstant(MVT::getSizeInBits(XType)-1, 1423 TLI.getShiftAmountTy())); 1424 if (XType > AType) 1425 Shift = getNode(ISD::TRUNCATE, AType, Shift); 1426 return getNode(ISD::AND, AType, Shift, N2); 1427 } 1428 } 1429 } 1430 break; 1431 case ISD::BRCOND: 1432 if (N2C) 1433 if (N2C->getValue()) // Unconditional branch 1434 return getNode(ISD::BR, MVT::Other, N1, N3); 1435 else 1436 return N1; // Never-taken branch 1437 break; 1438 } 1439 1440 std::vector<SDOperand> Ops; 1441 Ops.reserve(3); 1442 Ops.push_back(N1); 1443 Ops.push_back(N2); 1444 Ops.push_back(N3); 1445 1446 // Memoize nodes. 1447 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1448 if (N) return SDOperand(N, 0); 1449 1450 N = new SDNode(Opcode, N1, N2, N3); 1451 N->setValueTypes(VT); 1452 AllNodes.push_back(N); 1453 return SDOperand(N, 0); 1454} 1455 1456SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1457 SDOperand N1, SDOperand N2, SDOperand N3, 1458 SDOperand N4) { 1459 std::vector<SDOperand> Ops; 1460 Ops.reserve(4); 1461 Ops.push_back(N1); 1462 Ops.push_back(N2); 1463 Ops.push_back(N3); 1464 Ops.push_back(N4); 1465 return getNode(Opcode, VT, Ops); 1466} 1467 1468SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1469 assert((!V || isa<PointerType>(V->getType())) && 1470 "SrcValue is not a pointer?"); 1471 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1472 if (N) return SDOperand(N, 0); 1473 1474 N = new SrcValueSDNode(V, Offset); 1475 AllNodes.push_back(N); 1476 return SDOperand(N, 0); 1477} 1478 1479SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1480 std::vector<SDOperand> &Ops) { 1481 switch (Ops.size()) { 1482 case 0: return getNode(Opcode, VT); 1483 case 1: return getNode(Opcode, VT, Ops[0]); 1484 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1485 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1486 default: break; 1487 } 1488 1489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1490 switch (Opcode) { 1491 default: break; 1492 case ISD::BRCONDTWOWAY: 1493 if (N1C) 1494 if (N1C->getValue()) // Unconditional branch to true dest. 1495 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1496 else // Unconditional branch to false dest. 1497 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1498 break; 1499 } 1500 1501 // Memoize nodes. 1502 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1503 if (N) return SDOperand(N, 0); 1504 N = new SDNode(Opcode, Ops); 1505 N->setValueTypes(VT); 1506 AllNodes.push_back(N); 1507 return SDOperand(N, 0); 1508} 1509 1510SDOperand SelectionDAG::getNode(unsigned Opcode, 1511 std::vector<MVT::ValueType> &ResultTys, 1512 std::vector<SDOperand> &Ops) { 1513 if (ResultTys.size() == 1) 1514 return getNode(Opcode, ResultTys[0], Ops); 1515 1516 // FIXME: figure out how to safely handle things like 1517 // int foo(int x) { return 1 << (x & 255); } 1518 // int bar() { return foo(256); } 1519#if 0 1520 switch (Opcode) { 1521 case ISD::SRA_PARTS: 1522 case ISD::SRL_PARTS: 1523 case ISD::SHL_PARTS: 1524 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1525 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1526 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1527 else if (N3.getOpcode() == ISD::AND) 1528 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1529 // If the and is only masking out bits that cannot effect the shift, 1530 // eliminate the and. 1531 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1532 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1533 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1534 } 1535 break; 1536 } 1537#endif 1538 1539 // Memoize the node. 1540 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1541 Ops))]; 1542 if (N) return SDOperand(N, 0); 1543 N = new SDNode(Opcode, Ops); 1544 N->setValueTypes(ResultTys); 1545 AllNodes.push_back(N); 1546 return SDOperand(N, 0); 1547} 1548 1549 1550SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1, 1551 MVT::ValueType EVT) { 1552 EVTStruct NN; 1553 NN.Opcode = Opcode; 1554 NN.VT = VT; 1555 NN.EVT = EVT; 1556 NN.Ops.push_back(N1); 1557 1558 SDNode *&N = MVTSDNodes[NN]; 1559 if (N) return SDOperand(N, 0); 1560 N = new MVTSDNode(Opcode, VT, N1, EVT); 1561 AllNodes.push_back(N); 1562 return SDOperand(N, 0); 1563} 1564 1565SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1, 1566 SDOperand N2, SDOperand N3, MVT::ValueType EVT) { 1567 switch (Opcode) { 1568 default: assert(0 && "Bad opcode for this accessor!"); 1569 case ISD::EXTLOAD: 1570 case ISD::SEXTLOAD: 1571 case ISD::ZEXTLOAD: 1572 // If they are asking for an extending load from/to the same thing, return a 1573 // normal load. 1574 if (VT == EVT) 1575 return getLoad(VT, N1, N2, N3); 1576 assert(EVT < VT && "Should only be an extending load, not truncating!"); 1577 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) && 1578 "Cannot sign/zero extend a FP load!"); 1579 assert(MVT::isInteger(VT) == MVT::isInteger(EVT) && 1580 "Cannot convert from FP to Int or Int -> FP!"); 1581 break; 1582 } 1583 1584 EVTStruct NN; 1585 NN.Opcode = Opcode; 1586 NN.VT = VT; 1587 NN.EVT = EVT; 1588 NN.Ops.push_back(N1); 1589 NN.Ops.push_back(N2); 1590 NN.Ops.push_back(N3); 1591 1592 SDNode *&N = MVTSDNodes[NN]; 1593 if (N) return SDOperand(N, 0); 1594 N = new MVTSDNode(Opcode, VT, MVT::Other, N1, N2, N3, EVT); 1595 AllNodes.push_back(N); 1596 return SDOperand(N, 0); 1597} 1598 1599SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1, 1600 SDOperand N2, SDOperand N3, SDOperand N4, 1601 MVT::ValueType EVT) { 1602 switch (Opcode) { 1603 default: assert(0 && "Bad opcode for this accessor!"); 1604 case ISD::TRUNCSTORE: 1605#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1606 // If this is a truncating store of a constant, convert to the desired type 1607 // and store it instead. 1608 if (isa<Constant>(N1)) { 1609 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1610 if (isa<Constant>(Op)) 1611 N1 = Op; 1612 } 1613 // Also for ConstantFP? 1614#endif 1615 if (N1.getValueType() == EVT) // Normal store? 1616 return getNode(ISD::STORE, VT, N1, N2, N3, N4); 1617 assert(N2.getValueType() > EVT && "Not a truncation?"); 1618 assert(MVT::isInteger(N2.getValueType()) == MVT::isInteger(EVT) && 1619 "Can't do FP-INT conversion!"); 1620 break; 1621 } 1622 1623 EVTStruct NN; 1624 NN.Opcode = Opcode; 1625 NN.VT = VT; 1626 NN.EVT = EVT; 1627 NN.Ops.push_back(N1); 1628 NN.Ops.push_back(N2); 1629 NN.Ops.push_back(N3); 1630 NN.Ops.push_back(N4); 1631 1632 SDNode *&N = MVTSDNodes[NN]; 1633 if (N) return SDOperand(N, 0); 1634 N = new MVTSDNode(Opcode, VT, N1, N2, N3, N4, EVT); 1635 AllNodes.push_back(N); 1636 return SDOperand(N, 0); 1637} 1638 1639 1640/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1641/// indicated value. This method ignores uses of other values defined by this 1642/// operation. 1643bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1644 assert(Value < getNumValues() && "Bad value!"); 1645 1646 // If there is only one value, this is easy. 1647 if (getNumValues() == 1) 1648 return use_size() == NUses; 1649 if (Uses.size() < NUses) return false; 1650 1651 SDOperand TheValue(this, Value); 1652 1653 std::set<SDNode*> UsersHandled; 1654 1655 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1656 UI != E; ++UI) { 1657 SDNode *User = *UI; 1658 if (User->getNumOperands() == 1 || 1659 UsersHandled.insert(User).second) // First time we've seen this? 1660 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1661 if (User->getOperand(i) == TheValue) { 1662 if (NUses == 0) 1663 return false; // too many uses 1664 --NUses; 1665 } 1666 } 1667 1668 // Found exactly the right number of uses? 1669 return NUses == 0; 1670} 1671 1672 1673const char *SDNode::getOperationName() const { 1674 switch (getOpcode()) { 1675 default: return "<<Unknown>>"; 1676 case ISD::PCMARKER: return "PCMarker"; 1677 case ISD::SRCVALUE: return "SrcValue"; 1678 case ISD::EntryToken: return "EntryToken"; 1679 case ISD::TokenFactor: return "TokenFactor"; 1680 case ISD::Constant: return "Constant"; 1681 case ISD::ConstantFP: return "ConstantFP"; 1682 case ISD::GlobalAddress: return "GlobalAddress"; 1683 case ISD::FrameIndex: return "FrameIndex"; 1684 case ISD::BasicBlock: return "BasicBlock"; 1685 case ISD::ExternalSymbol: return "ExternalSymbol"; 1686 case ISD::ConstantPool: return "ConstantPoolIndex"; 1687 case ISD::CopyToReg: return "CopyToReg"; 1688 case ISD::CopyFromReg: return "CopyFromReg"; 1689 case ISD::ImplicitDef: return "ImplicitDef"; 1690 case ISD::UNDEF: return "undef"; 1691 1692 // Unary operators 1693 case ISD::FABS: return "fabs"; 1694 case ISD::FNEG: return "fneg"; 1695 case ISD::FSQRT: return "fsqrt"; 1696 case ISD::FSIN: return "fsin"; 1697 case ISD::FCOS: return "fcos"; 1698 1699 // Binary operators 1700 case ISD::ADD: return "add"; 1701 case ISD::SUB: return "sub"; 1702 case ISD::MUL: return "mul"; 1703 case ISD::MULHU: return "mulhu"; 1704 case ISD::MULHS: return "mulhs"; 1705 case ISD::SDIV: return "sdiv"; 1706 case ISD::UDIV: return "udiv"; 1707 case ISD::SREM: return "srem"; 1708 case ISD::UREM: return "urem"; 1709 case ISD::AND: return "and"; 1710 case ISD::OR: return "or"; 1711 case ISD::XOR: return "xor"; 1712 case ISD::SHL: return "shl"; 1713 case ISD::SRA: return "sra"; 1714 case ISD::SRL: return "srl"; 1715 1716 case ISD::SELECT: return "select"; 1717 case ISD::ADD_PARTS: return "add_parts"; 1718 case ISD::SUB_PARTS: return "sub_parts"; 1719 case ISD::SHL_PARTS: return "shl_parts"; 1720 case ISD::SRA_PARTS: return "sra_parts"; 1721 case ISD::SRL_PARTS: return "srl_parts"; 1722 1723 // Conversion operators. 1724 case ISD::SIGN_EXTEND: return "sign_extend"; 1725 case ISD::ZERO_EXTEND: return "zero_extend"; 1726 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1727 case ISD::TRUNCATE: return "truncate"; 1728 case ISD::FP_ROUND: return "fp_round"; 1729 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1730 case ISD::FP_EXTEND: return "fp_extend"; 1731 1732 case ISD::SINT_TO_FP: return "sint_to_fp"; 1733 case ISD::UINT_TO_FP: return "uint_to_fp"; 1734 case ISD::FP_TO_SINT: return "fp_to_sint"; 1735 case ISD::FP_TO_UINT: return "fp_to_uint"; 1736 1737 // Control flow instructions 1738 case ISD::BR: return "br"; 1739 case ISD::BRCOND: return "brcond"; 1740 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1741 case ISD::RET: return "ret"; 1742 case ISD::CALL: return "call"; 1743 case ISD::TAILCALL:return "tailcall"; 1744 case ISD::CALLSEQ_START: return "callseq_start"; 1745 case ISD::CALLSEQ_END: return "callseq_end"; 1746 1747 // Other operators 1748 case ISD::LOAD: return "load"; 1749 case ISD::STORE: return "store"; 1750 case ISD::EXTLOAD: return "extload"; 1751 case ISD::SEXTLOAD: return "sextload"; 1752 case ISD::ZEXTLOAD: return "zextload"; 1753 case ISD::TRUNCSTORE: return "truncstore"; 1754 1755 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1756 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1757 case ISD::BUILD_PAIR: return "build_pair"; 1758 case ISD::MEMSET: return "memset"; 1759 case ISD::MEMCPY: return "memcpy"; 1760 case ISD::MEMMOVE: return "memmove"; 1761 1762 // Bit counting 1763 case ISD::CTPOP: return "ctpop"; 1764 case ISD::CTTZ: return "cttz"; 1765 case ISD::CTLZ: return "ctlz"; 1766 1767 // IO Intrinsics 1768 case ISD::READPORT: return "readport"; 1769 case ISD::WRITEPORT: return "writeport"; 1770 case ISD::READIO: return "readio"; 1771 case ISD::WRITEIO: return "writeio"; 1772 1773 case ISD::SETCC: 1774 const SetCCSDNode *SetCC = cast<SetCCSDNode>(this); 1775 switch (SetCC->getCondition()) { 1776 default: assert(0 && "Unknown setcc condition!"); 1777 case ISD::SETOEQ: return "setcc:setoeq"; 1778 case ISD::SETOGT: return "setcc:setogt"; 1779 case ISD::SETOGE: return "setcc:setoge"; 1780 case ISD::SETOLT: return "setcc:setolt"; 1781 case ISD::SETOLE: return "setcc:setole"; 1782 case ISD::SETONE: return "setcc:setone"; 1783 1784 case ISD::SETO: return "setcc:seto"; 1785 case ISD::SETUO: return "setcc:setuo"; 1786 case ISD::SETUEQ: return "setcc:setue"; 1787 case ISD::SETUGT: return "setcc:setugt"; 1788 case ISD::SETUGE: return "setcc:setuge"; 1789 case ISD::SETULT: return "setcc:setult"; 1790 case ISD::SETULE: return "setcc:setule"; 1791 case ISD::SETUNE: return "setcc:setune"; 1792 1793 case ISD::SETEQ: return "setcc:seteq"; 1794 case ISD::SETGT: return "setcc:setgt"; 1795 case ISD::SETGE: return "setcc:setge"; 1796 case ISD::SETLT: return "setcc:setlt"; 1797 case ISD::SETLE: return "setcc:setle"; 1798 case ISD::SETNE: return "setcc:setne"; 1799 } 1800 } 1801} 1802 1803void SDNode::dump() const { 1804 std::cerr << (void*)this << ": "; 1805 1806 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 1807 if (i) std::cerr << ","; 1808 if (getValueType(i) == MVT::Other) 1809 std::cerr << "ch"; 1810 else 1811 std::cerr << MVT::getValueTypeString(getValueType(i)); 1812 } 1813 std::cerr << " = " << getOperationName(); 1814 1815 std::cerr << " "; 1816 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1817 if (i) std::cerr << ", "; 1818 std::cerr << (void*)getOperand(i).Val; 1819 if (unsigned RN = getOperand(i).ResNo) 1820 std::cerr << ":" << RN; 1821 } 1822 1823 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 1824 std::cerr << "<" << CSDN->getValue() << ">"; 1825 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 1826 std::cerr << "<" << CSDN->getValue() << ">"; 1827 } else if (const GlobalAddressSDNode *GADN = 1828 dyn_cast<GlobalAddressSDNode>(this)) { 1829 std::cerr << "<"; 1830 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 1831 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 1832 std::cerr << "<" << FIDN->getIndex() << ">"; 1833 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 1834 std::cerr << "<" << CP->getIndex() << ">"; 1835 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 1836 std::cerr << "<"; 1837 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 1838 if (LBB) 1839 std::cerr << LBB->getName() << " "; 1840 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 1841 } else if (const RegSDNode *C2V = dyn_cast<RegSDNode>(this)) { 1842 std::cerr << "<reg #" << C2V->getReg() << ">"; 1843 } else if (const ExternalSymbolSDNode *ES = 1844 dyn_cast<ExternalSymbolSDNode>(this)) { 1845 std::cerr << "'" << ES->getSymbol() << "'"; 1846 } else if (const MVTSDNode *M = dyn_cast<MVTSDNode>(this)) { 1847 std::cerr << " - Ty = " << MVT::getValueTypeString(M->getExtraValueType()); 1848 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 1849 if (M->getValue()) 1850 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 1851 else 1852 std::cerr << "<null:" << M->getOffset() << ">"; 1853 } 1854} 1855 1856static void DumpNodes(SDNode *N, unsigned indent) { 1857 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1858 if (N->getOperand(i).Val->hasOneUse()) 1859 DumpNodes(N->getOperand(i).Val, indent+2); 1860 else 1861 std::cerr << "\n" << std::string(indent+2, ' ') 1862 << (void*)N->getOperand(i).Val << ": <multiple use>"; 1863 1864 1865 std::cerr << "\n" << std::string(indent, ' '); 1866 N->dump(); 1867} 1868 1869void SelectionDAG::dump() const { 1870 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 1871 std::vector<SDNode*> Nodes(AllNodes); 1872 std::sort(Nodes.begin(), Nodes.end()); 1873 1874 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 1875 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 1876 DumpNodes(Nodes[i], 2); 1877 } 1878 1879 DumpNodes(getRoot().Val, 2); 1880 1881 std::cerr << "\n\n"; 1882} 1883 1884