SelectionDAG.cpp revision 5839bf2b3bd22689d9dd0e9de66c2dce71d130ae
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/MRegisterInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include <iostream> 25#include <set> 26#include <cmath> 27#include <algorithm> 28using namespace llvm; 29 30static bool isCommutativeBinOp(unsigned Opcode) { 31 switch (Opcode) { 32 case ISD::ADD: 33 case ISD::MUL: 34 case ISD::AND: 35 case ISD::OR: 36 case ISD::XOR: return true; 37 default: return false; // FIXME: Need commutative info for user ops! 38 } 39} 40 41static bool isAssociativeBinOp(unsigned Opcode) { 42 switch (Opcode) { 43 case ISD::ADD: 44 case ISD::MUL: 45 case ISD::AND: 46 case ISD::OR: 47 case ISD::XOR: return true; 48 default: return false; // FIXME: Need associative info for user ops! 49 } 50} 51 52// isInvertibleForFree - Return true if there is no cost to emitting the logical 53// inverse of this node. 54static bool isInvertibleForFree(SDOperand N) { 55 if (isa<ConstantSDNode>(N.Val)) return true; 56 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 57 return true; 58 return false; 59} 60 61//===----------------------------------------------------------------------===// 62// ConstantFPSDNode Class 63//===----------------------------------------------------------------------===// 64 65/// isExactlyValue - We don't rely on operator== working on double values, as 66/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 67/// As such, this method can be used to do an exact bit-for-bit comparison of 68/// two floating point values. 69bool ConstantFPSDNode::isExactlyValue(double V) const { 70 return DoubleToBits(V) == DoubleToBits(Value); 71} 72 73//===----------------------------------------------------------------------===// 74// ISD Class 75//===----------------------------------------------------------------------===// 76 77/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 78/// when given the operation for (X op Y). 79ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 80 // To perform this operation, we just need to swap the L and G bits of the 81 // operation. 82 unsigned OldL = (Operation >> 2) & 1; 83 unsigned OldG = (Operation >> 1) & 1; 84 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 85 (OldL << 1) | // New G bit 86 (OldG << 2)); // New L bit. 87} 88 89/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 90/// 'op' is a valid SetCC operation. 91ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 92 unsigned Operation = Op; 93 if (isInteger) 94 Operation ^= 7; // Flip L, G, E bits, but not U. 95 else 96 Operation ^= 15; // Flip all of the condition bits. 97 if (Operation > ISD::SETTRUE2) 98 Operation &= ~8; // Don't let N and U bits get set. 99 return ISD::CondCode(Operation); 100} 101 102 103/// isSignedOp - For an integer comparison, return 1 if the comparison is a 104/// signed operation and 2 if the result is an unsigned comparison. Return zero 105/// if the operation does not depend on the sign of the input (setne and seteq). 106static int isSignedOp(ISD::CondCode Opcode) { 107 switch (Opcode) { 108 default: assert(0 && "Illegal integer setcc operation!"); 109 case ISD::SETEQ: 110 case ISD::SETNE: return 0; 111 case ISD::SETLT: 112 case ISD::SETLE: 113 case ISD::SETGT: 114 case ISD::SETGE: return 1; 115 case ISD::SETULT: 116 case ISD::SETULE: 117 case ISD::SETUGT: 118 case ISD::SETUGE: return 2; 119 } 120} 121 122/// getSetCCOrOperation - Return the result of a logical OR between different 123/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 124/// returns SETCC_INVALID if it is not possible to represent the resultant 125/// comparison. 126ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 127 bool isInteger) { 128 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 129 // Cannot fold a signed integer setcc with an unsigned integer setcc. 130 return ISD::SETCC_INVALID; 131 132 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 133 134 // If the N and U bits get set then the resultant comparison DOES suddenly 135 // care about orderedness, and is true when ordered. 136 if (Op > ISD::SETTRUE2) 137 Op &= ~16; // Clear the N bit. 138 return ISD::CondCode(Op); 139} 140 141/// getSetCCAndOperation - Return the result of a logical AND between different 142/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 143/// function returns zero if it is not possible to represent the resultant 144/// comparison. 145ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 146 bool isInteger) { 147 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 148 // Cannot fold a signed setcc with an unsigned setcc. 149 return ISD::SETCC_INVALID; 150 151 // Combine all of the condition bits. 152 return ISD::CondCode(Op1 & Op2); 153} 154 155const TargetMachine &SelectionDAG::getTarget() const { 156 return TLI.getTargetMachine(); 157} 158 159//===----------------------------------------------------------------------===// 160// SelectionDAG Class 161//===----------------------------------------------------------------------===// 162 163/// RemoveDeadNodes - This method deletes all unreachable nodes in the 164/// SelectionDAG, including nodes (like loads) that have uses of their token 165/// chain but no other uses and no side effect. If a node is passed in as an 166/// argument, it is used as the seed for node deletion. 167void SelectionDAG::RemoveDeadNodes(SDNode *N) { 168 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 169 170 // Create a dummy node (which is not added to allnodes), that adds a reference 171 // to the root node, preventing it from being deleted. 172 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 173 174 // If we have a hint to start from, use it. 175 if (N) DeleteNodeIfDead(N, &AllNodeSet); 176 177 Restart: 178 unsigned NumNodes = AllNodeSet.size(); 179 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 180 I != E; ++I) { 181 // Try to delete this node. 182 DeleteNodeIfDead(*I, &AllNodeSet); 183 184 // If we actually deleted any nodes, do not use invalid iterators in 185 // AllNodeSet. 186 if (AllNodeSet.size() != NumNodes) 187 goto Restart; 188 } 189 190 // Restore AllNodes. 191 if (AllNodes.size() != NumNodes) 192 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 193 194 // If the root changed (e.g. it was a dead load, update the root). 195 setRoot(DummyNode->getOperand(0)); 196 197 // Now that we are done with the dummy node, delete it. 198 DummyNode->getOperand(0).Val->removeUser(DummyNode); 199 delete DummyNode; 200} 201 202 203void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 204 if (!N->use_empty()) 205 return; 206 207 // Okay, we really are going to delete this node. First take this out of the 208 // appropriate CSE map. 209 RemoveNodeFromCSEMaps(N); 210 211 // Next, brutally remove the operand list. This is safe to do, as there are 212 // no cycles in the graph. 213 while (!N->Operands.empty()) { 214 SDNode *O = N->Operands.back().Val; 215 N->Operands.pop_back(); 216 O->removeUser(N); 217 218 // Now that we removed this operand, see if there are no uses of it left. 219 DeleteNodeIfDead(O, NodeSet); 220 } 221 222 // Remove the node from the nodes set and delete it. 223 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 224 AllNodeSet.erase(N); 225 226 // Now that the node is gone, check to see if any of the operands of this node 227 // are dead now. 228 delete N; 229} 230 231/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 232/// correspond to it. This is useful when we're about to delete or repurpose 233/// the node. We don't want future request for structurally identical nodes 234/// to return N anymore. 235void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 236 switch (N->getOpcode()) { 237 case ISD::Constant: 238 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 239 N->getValueType(0))); 240 break; 241 case ISD::TargetConstant: 242 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 243 N->getValueType(0))); 244 break; 245 case ISD::ConstantFP: { 246 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 247 ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 248 break; 249 } 250 case ISD::CONDCODE: 251 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 252 "Cond code doesn't exist!"); 253 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 254 break; 255 case ISD::GlobalAddress: 256 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 257 break; 258 case ISD::TargetGlobalAddress: 259 TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 260 break; 261 case ISD::FrameIndex: 262 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 263 break; 264 case ISD::TargetFrameIndex: 265 TargetFrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 266 break; 267 case ISD::ConstantPool: 268 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->get()); 269 break; 270 case ISD::TargetConstantPool: 271 TargetConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->get()); 272 break; 273 case ISD::BasicBlock: 274 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 275 break; 276 case ISD::ExternalSymbol: 277 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 278 break; 279 case ISD::VALUETYPE: 280 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 281 break; 282 case ISD::Register: 283 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 284 break; 285 case ISD::SRCVALUE: { 286 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 287 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 288 break; 289 } 290 case ISD::LOAD: 291 Loads.erase(std::make_pair(N->getOperand(1), 292 std::make_pair(N->getOperand(0), 293 N->getValueType(0)))); 294 break; 295 default: 296 if (N->getNumOperands() == 1) 297 UnaryOps.erase(std::make_pair(N->getOpcode(), 298 std::make_pair(N->getOperand(0), 299 N->getValueType(0)))); 300 else if (N->getNumOperands() == 2) 301 BinaryOps.erase(std::make_pair(N->getOpcode(), 302 std::make_pair(N->getOperand(0), 303 N->getOperand(1)))); 304 else if (N->getNumValues() == 1) { 305 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 306 OneResultNodes.erase(std::make_pair(N->getOpcode(), 307 std::make_pair(N->getValueType(0), 308 Ops))); 309 } else { 310 // Remove the node from the ArbitraryNodes map. 311 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 312 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 313 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 314 std::make_pair(RV, Ops))); 315 } 316 break; 317 } 318} 319 320/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 321/// has been taken out and modified in some way. If the specified node already 322/// exists in the CSE maps, do not modify the maps, but return the existing node 323/// instead. If it doesn't exist, add it and return null. 324/// 325SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 326 assert(N->getNumOperands() && "This is a leaf node!"); 327 if (N->getOpcode() == ISD::LOAD) { 328 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 329 std::make_pair(N->getOperand(0), 330 N->getValueType(0)))]; 331 if (L) return L; 332 L = N; 333 } else if (N->getNumOperands() == 1) { 334 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 335 std::make_pair(N->getOperand(0), 336 N->getValueType(0)))]; 337 if (U) return U; 338 U = N; 339 } else if (N->getNumOperands() == 2) { 340 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 341 std::make_pair(N->getOperand(0), 342 N->getOperand(1)))]; 343 if (B) return B; 344 B = N; 345 } else if (N->getNumValues() == 1) { 346 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 347 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 348 std::make_pair(N->getValueType(0), Ops))]; 349 if (ORN) return ORN; 350 ORN = N; 351 } else { 352 // Remove the node from the ArbitraryNodes map. 353 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 354 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 355 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 356 std::make_pair(RV, Ops))]; 357 if (AN) return AN; 358 AN = N; 359 } 360 return 0; 361 362} 363 364 365 366SelectionDAG::~SelectionDAG() { 367 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 368 delete AllNodes[i]; 369} 370 371SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 372 if (Op.getValueType() == VT) return Op; 373 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 374 return getNode(ISD::AND, Op.getValueType(), Op, 375 getConstant(Imm, Op.getValueType())); 376} 377 378SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 379 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 380 // Mask out any bits that are not valid for this constant. 381 if (VT != MVT::i64) 382 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 383 384 SDNode *&N = Constants[std::make_pair(Val, VT)]; 385 if (N) return SDOperand(N, 0); 386 N = new ConstantSDNode(false, Val, VT); 387 AllNodes.push_back(N); 388 return SDOperand(N, 0); 389} 390 391SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 392 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 393 // Mask out any bits that are not valid for this constant. 394 if (VT != MVT::i64) 395 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 396 397 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 398 if (N) return SDOperand(N, 0); 399 N = new ConstantSDNode(true, Val, VT); 400 AllNodes.push_back(N); 401 return SDOperand(N, 0); 402} 403 404SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 405 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 406 if (VT == MVT::f32) 407 Val = (float)Val; // Mask out extra precision. 408 409 // Do the map lookup using the actual bit pattern for the floating point 410 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 411 // we don't have issues with SNANs. 412 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 413 if (N) return SDOperand(N, 0); 414 N = new ConstantFPSDNode(Val, VT); 415 AllNodes.push_back(N); 416 return SDOperand(N, 0); 417} 418 419 420 421SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 422 MVT::ValueType VT) { 423 SDNode *&N = GlobalValues[GV]; 424 if (N) return SDOperand(N, 0); 425 N = new GlobalAddressSDNode(false, GV, VT); 426 AllNodes.push_back(N); 427 return SDOperand(N, 0); 428} 429 430SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 431 MVT::ValueType VT) { 432 SDNode *&N = TargetGlobalValues[GV]; 433 if (N) return SDOperand(N, 0); 434 N = new GlobalAddressSDNode(true, GV, VT); 435 AllNodes.push_back(N); 436 return SDOperand(N, 0); 437} 438 439SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 440 SDNode *&N = FrameIndices[FI]; 441 if (N) return SDOperand(N, 0); 442 N = new FrameIndexSDNode(FI, VT, false); 443 AllNodes.push_back(N); 444 return SDOperand(N, 0); 445} 446 447SDOperand SelectionDAG::getTargetFrameIndex(int FI, MVT::ValueType VT) { 448 SDNode *&N = TargetFrameIndices[FI]; 449 if (N) return SDOperand(N, 0); 450 N = new FrameIndexSDNode(FI, VT, true); 451 AllNodes.push_back(N); 452 return SDOperand(N, 0); 453} 454 455SDOperand SelectionDAG::getConstantPool(Constant *C, MVT::ValueType VT) { 456 SDNode *&N = ConstantPoolIndices[C]; 457 if (N) return SDOperand(N, 0); 458 N = new ConstantPoolSDNode(C, VT, false); 459 AllNodes.push_back(N); 460 return SDOperand(N, 0); 461} 462 463SDOperand SelectionDAG::getTargetConstantPool(Constant *C, MVT::ValueType VT) { 464 SDNode *&N = TargetConstantPoolIndices[C]; 465 if (N) return SDOperand(N, 0); 466 N = new ConstantPoolSDNode(C, VT, true); 467 AllNodes.push_back(N); 468 return SDOperand(N, 0); 469} 470 471SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 472 SDNode *&N = BBNodes[MBB]; 473 if (N) return SDOperand(N, 0); 474 N = new BasicBlockSDNode(MBB); 475 AllNodes.push_back(N); 476 return SDOperand(N, 0); 477} 478 479SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 480 if ((unsigned)VT >= ValueTypeNodes.size()) 481 ValueTypeNodes.resize(VT+1); 482 if (ValueTypeNodes[VT] == 0) { 483 ValueTypeNodes[VT] = new VTSDNode(VT); 484 AllNodes.push_back(ValueTypeNodes[VT]); 485 } 486 487 return SDOperand(ValueTypeNodes[VT], 0); 488} 489 490SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 491 SDNode *&N = ExternalSymbols[Sym]; 492 if (N) return SDOperand(N, 0); 493 N = new ExternalSymbolSDNode(Sym, VT); 494 AllNodes.push_back(N); 495 return SDOperand(N, 0); 496} 497 498SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 499 if ((unsigned)Cond >= CondCodeNodes.size()) 500 CondCodeNodes.resize(Cond+1); 501 502 if (CondCodeNodes[Cond] == 0) { 503 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 504 AllNodes.push_back(CondCodeNodes[Cond]); 505 } 506 return SDOperand(CondCodeNodes[Cond], 0); 507} 508 509SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 510 if (Reg >= RegNodes.size()) 511 RegNodes.resize(Reg+1); 512 RegisterSDNode *&Result = RegNodes[Reg]; 513 if (Result) { 514 assert(Result->getValueType(0) == VT && 515 "Inconsistent value types for machine registers"); 516 } else { 517 Result = new RegisterSDNode(Reg, VT); 518 AllNodes.push_back(Result); 519 } 520 return SDOperand(Result, 0); 521} 522 523SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 524 SDOperand N2, ISD::CondCode Cond) { 525 // These setcc operations always fold. 526 switch (Cond) { 527 default: break; 528 case ISD::SETFALSE: 529 case ISD::SETFALSE2: return getConstant(0, VT); 530 case ISD::SETTRUE: 531 case ISD::SETTRUE2: return getConstant(1, VT); 532 } 533 534 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 535 uint64_t C2 = N2C->getValue(); 536 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 537 uint64_t C1 = N1C->getValue(); 538 539 // Sign extend the operands if required 540 if (ISD::isSignedIntSetCC(Cond)) { 541 C1 = N1C->getSignExtended(); 542 C2 = N2C->getSignExtended(); 543 } 544 545 switch (Cond) { 546 default: assert(0 && "Unknown integer setcc!"); 547 case ISD::SETEQ: return getConstant(C1 == C2, VT); 548 case ISD::SETNE: return getConstant(C1 != C2, VT); 549 case ISD::SETULT: return getConstant(C1 < C2, VT); 550 case ISD::SETUGT: return getConstant(C1 > C2, VT); 551 case ISD::SETULE: return getConstant(C1 <= C2, VT); 552 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 553 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 554 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 555 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 556 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 557 } 558 } else { 559 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 560 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 561 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 562 563 // If the comparison constant has bits in the upper part, the 564 // zero-extended value could never match. 565 if (C2 & (~0ULL << InSize)) { 566 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 567 switch (Cond) { 568 case ISD::SETUGT: 569 case ISD::SETUGE: 570 case ISD::SETEQ: return getConstant(0, VT); 571 case ISD::SETULT: 572 case ISD::SETULE: 573 case ISD::SETNE: return getConstant(1, VT); 574 case ISD::SETGT: 575 case ISD::SETGE: 576 // True if the sign bit of C2 is set. 577 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 578 case ISD::SETLT: 579 case ISD::SETLE: 580 // True if the sign bit of C2 isn't set. 581 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 582 default: 583 break; 584 } 585 } 586 587 // Otherwise, we can perform the comparison with the low bits. 588 switch (Cond) { 589 case ISD::SETEQ: 590 case ISD::SETNE: 591 case ISD::SETUGT: 592 case ISD::SETUGE: 593 case ISD::SETULT: 594 case ISD::SETULE: 595 return getSetCC(VT, N1.getOperand(0), 596 getConstant(C2, N1.getOperand(0).getValueType()), 597 Cond); 598 default: 599 break; // todo, be more careful with signed comparisons 600 } 601 } else if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG && 602 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 603 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N1.getOperand(1))->getVT(); 604 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 605 MVT::ValueType ExtDstTy = N1.getValueType(); 606 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 607 608 // If the extended part has any inconsistent bits, it cannot ever 609 // compare equal. In other words, they have to be all ones or all 610 // zeros. 611 uint64_t ExtBits = 612 (~0ULL >> 64-ExtSrcTyBits) & (~0ULL << (ExtDstTyBits-1)); 613 if ((C2 & ExtBits) != 0 && (C2 & ExtBits) != ExtBits) 614 return getConstant(Cond == ISD::SETNE, VT); 615 616 // Otherwise, make this a use of a zext. 617 return getSetCC(VT, getZeroExtendInReg(N1.getOperand(0), ExtSrcTy), 618 getConstant(C2 & (~0ULL >> 64-ExtSrcTyBits), ExtDstTy), 619 Cond); 620 } 621 622 uint64_t MinVal, MaxVal; 623 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 624 if (ISD::isSignedIntSetCC(Cond)) { 625 MinVal = 1ULL << (OperandBitSize-1); 626 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 627 MaxVal = ~0ULL >> (65-OperandBitSize); 628 else 629 MaxVal = 0; 630 } else { 631 MinVal = 0; 632 MaxVal = ~0ULL >> (64-OperandBitSize); 633 } 634 635 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 636 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 637 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 638 --C2; // X >= C1 --> X > (C1-1) 639 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 640 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 641 } 642 643 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 644 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 645 ++C2; // X <= C1 --> X < (C1+1) 646 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 647 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 648 } 649 650 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 651 return getConstant(0, VT); // X < MIN --> false 652 653 // Canonicalize setgt X, Min --> setne X, Min 654 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 655 return getSetCC(VT, N1, N2, ISD::SETNE); 656 657 // If we have setult X, 1, turn it into seteq X, 0 658 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 659 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 660 ISD::SETEQ); 661 // If we have setugt X, Max-1, turn it into seteq X, Max 662 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 663 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 664 ISD::SETEQ); 665 666 // If we have "setcc X, C1", check to see if we can shrink the immediate 667 // by changing cc. 668 669 // SETUGT X, SINTMAX -> SETLT X, 0 670 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 671 C2 == (~0ULL >> (65-OperandBitSize))) 672 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 673 674 // FIXME: Implement the rest of these. 675 676 677 // Fold bit comparisons when we can. 678 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 679 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 680 if (ConstantSDNode *AndRHS = 681 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 682 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 683 // Perform the xform if the AND RHS is a single bit. 684 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 685 return getNode(ISD::SRL, VT, N1, 686 getConstant(Log2_64(AndRHS->getValue()), 687 TLI.getShiftAmountTy())); 688 } 689 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 690 // (X & 8) == 8 --> (X & 8) >> 3 691 // Perform the xform if C2 is a single bit. 692 if ((C2 & (C2-1)) == 0) { 693 return getNode(ISD::SRL, VT, N1, 694 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 695 } 696 } 697 } 698 } 699 } else if (isa<ConstantSDNode>(N1.Val)) { 700 // Ensure that the constant occurs on the RHS. 701 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 702 } 703 704 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 705 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 706 double C1 = N1C->getValue(), C2 = N2C->getValue(); 707 708 switch (Cond) { 709 default: break; // FIXME: Implement the rest of these! 710 case ISD::SETEQ: return getConstant(C1 == C2, VT); 711 case ISD::SETNE: return getConstant(C1 != C2, VT); 712 case ISD::SETLT: return getConstant(C1 < C2, VT); 713 case ISD::SETGT: return getConstant(C1 > C2, VT); 714 case ISD::SETLE: return getConstant(C1 <= C2, VT); 715 case ISD::SETGE: return getConstant(C1 >= C2, VT); 716 } 717 } else { 718 // Ensure that the constant occurs on the RHS. 719 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 720 } 721 722 if (N1 == N2) { 723 // We can always fold X == Y for integer setcc's. 724 if (MVT::isInteger(N1.getValueType())) 725 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 726 unsigned UOF = ISD::getUnorderedFlavor(Cond); 727 if (UOF == 2) // FP operators that are undefined on NaNs. 728 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 729 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 730 return getConstant(UOF, VT); 731 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 732 // if it is not already. 733 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 734 if (NewCond != Cond) 735 return getSetCC(VT, N1, N2, NewCond); 736 } 737 738 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 739 MVT::isInteger(N1.getValueType())) { 740 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 741 N1.getOpcode() == ISD::XOR) { 742 // Simplify (X+Y) == (X+Z) --> Y == Z 743 if (N1.getOpcode() == N2.getOpcode()) { 744 if (N1.getOperand(0) == N2.getOperand(0)) 745 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 746 if (N1.getOperand(1) == N2.getOperand(1)) 747 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 748 if (isCommutativeBinOp(N1.getOpcode())) { 749 // If X op Y == Y op X, try other combinations. 750 if (N1.getOperand(0) == N2.getOperand(1)) 751 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 752 if (N1.getOperand(1) == N2.getOperand(0)) 753 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 754 } 755 } 756 757 // FIXME: move this stuff to the DAG Combiner when it exists! 758 759 // Simplify (X+Z) == X --> Z == 0 760 if (N1.getOperand(0) == N2) 761 return getSetCC(VT, N1.getOperand(1), 762 getConstant(0, N1.getValueType()), Cond); 763 if (N1.getOperand(1) == N2) { 764 if (isCommutativeBinOp(N1.getOpcode())) 765 return getSetCC(VT, N1.getOperand(0), 766 getConstant(0, N1.getValueType()), Cond); 767 else { 768 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 769 // (Z-X) == X --> Z == X<<1 770 return getSetCC(VT, N1.getOperand(0), 771 getNode(ISD::SHL, N2.getValueType(), 772 N2, getConstant(1, TLI.getShiftAmountTy())), 773 Cond); 774 } 775 } 776 } 777 778 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 779 N2.getOpcode() == ISD::XOR) { 780 // Simplify X == (X+Z) --> Z == 0 781 if (N2.getOperand(0) == N1) { 782 return getSetCC(VT, N2.getOperand(1), 783 getConstant(0, N2.getValueType()), Cond); 784 } else if (N2.getOperand(1) == N1) { 785 if (isCommutativeBinOp(N2.getOpcode())) { 786 return getSetCC(VT, N2.getOperand(0), 787 getConstant(0, N2.getValueType()), Cond); 788 } else { 789 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 790 // X == (Z-X) --> X<<1 == Z 791 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 792 getConstant(1, TLI.getShiftAmountTy())), 793 N2.getOperand(0), Cond); 794 } 795 } 796 } 797 } 798 799 // Fold away ALL boolean setcc's. 800 if (N1.getValueType() == MVT::i1) { 801 switch (Cond) { 802 default: assert(0 && "Unknown integer setcc!"); 803 case ISD::SETEQ: // X == Y -> (X^Y)^1 804 N1 = getNode(ISD::XOR, MVT::i1, 805 getNode(ISD::XOR, MVT::i1, N1, N2), 806 getConstant(1, MVT::i1)); 807 break; 808 case ISD::SETNE: // X != Y --> (X^Y) 809 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 810 break; 811 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 812 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 813 N1 = getNode(ISD::AND, MVT::i1, N2, 814 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 815 break; 816 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 817 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 818 N1 = getNode(ISD::AND, MVT::i1, N1, 819 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 820 break; 821 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 822 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 823 N1 = getNode(ISD::OR, MVT::i1, N2, 824 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 825 break; 826 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 827 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 828 N1 = getNode(ISD::OR, MVT::i1, N1, 829 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 830 break; 831 } 832 if (VT != MVT::i1) 833 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 834 return N1; 835 } 836 837 // Could not fold it. 838 return SDOperand(); 839} 840 841SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 842 SDOperand N3, SDOperand N4, 843 ISD::CondCode CC) { 844 MVT::ValueType VT = N3.getValueType(); 845 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 846 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 847 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 848 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 849 850 // Check to see if we can simplify the select into an fabs node 851 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 852 // Allow either -0.0 or 0.0 853 if (CFP->getValue() == 0.0) { 854 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 855 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 856 N1 == N3 && N4.getOpcode() == ISD::FNEG && 857 N1 == N4.getOperand(0)) 858 return getNode(ISD::FABS, VT, N1); 859 860 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 861 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 862 N1 == N4 && N3.getOpcode() == ISD::FNEG && 863 N3.getOperand(0) == N4) 864 return getNode(ISD::FABS, VT, N4); 865 } 866 } 867 868 // check to see if we're select_cc'ing a select_cc. 869 // this allows us to turn: 870 // select_cc set[eq,ne] (select_cc cc, lhs, rhs, 1, 0), 0, true, false -> 871 // select_cc cc, lhs, rhs, true, false 872 if ((N1C && N1C->isNullValue() && N2.getOpcode() == ISD::SELECT_CC) || 873 (N2C && N2C->isNullValue() && N1.getOpcode() == ISD::SELECT_CC) && 874 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 875 SDOperand SCC = N1C ? N2 : N1; 876 ConstantSDNode *SCCT = dyn_cast<ConstantSDNode>(SCC.getOperand(2)); 877 ConstantSDNode *SCCF = dyn_cast<ConstantSDNode>(SCC.getOperand(3)); 878 if (SCCT && SCCF && SCCF->isNullValue() && SCCT->getValue() == 1ULL) { 879 if (CC == ISD::SETEQ) std::swap(N3, N4); 880 return getNode(ISD::SELECT_CC, N3.getValueType(), SCC.getOperand(0), 881 SCC.getOperand(1), N3, N4, SCC.getOperand(4)); 882 } 883 } 884 885 // Check to see if we can perform the "gzip trick", transforming 886 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 887 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 888 MVT::isInteger(N1.getValueType()) && 889 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 890 MVT::ValueType XType = N1.getValueType(); 891 MVT::ValueType AType = N3.getValueType(); 892 if (XType >= AType) { 893 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 894 // single-bit constant. FIXME: remove once the dag combiner 895 // exists. 896 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 897 unsigned ShCtV = Log2_64(N3C->getValue()); 898 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 899 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 900 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 901 if (XType > AType) 902 Shift = getNode(ISD::TRUNCATE, AType, Shift); 903 return getNode(ISD::AND, AType, Shift, N3); 904 } 905 SDOperand Shift = getNode(ISD::SRA, XType, N1, 906 getConstant(MVT::getSizeInBits(XType)-1, 907 TLI.getShiftAmountTy())); 908 if (XType > AType) 909 Shift = getNode(ISD::TRUNCATE, AType, Shift); 910 return getNode(ISD::AND, AType, Shift, N3); 911 } 912 } 913 914 // Check to see if this is the equivalent of setcc 915 if (N4C && N4C->isNullValue() && N3C && (N3C->getValue() == 1ULL)) { 916 MVT::ValueType XType = N1.getValueType(); 917 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) 918 return getSetCC(TLI.getSetCCResultTy(), N1, N2, CC); 919 920 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 921 if (N2C && N2C->isNullValue() && CC == ISD::SETEQ && 922 TLI.isOperationLegal(ISD::CTLZ, XType)) { 923 SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1); 924 return getNode(ISD::SRL, XType, Ctlz, 925 getConstant(Log2_32(MVT::getSizeInBits(XType)), 926 TLI.getShiftAmountTy())); 927 } 928 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 929 if (N2C && N2C->isNullValue() && CC == ISD::SETGT) { 930 SDOperand NegN1 = getNode(ISD::SUB, XType, getConstant(0, XType), N1); 931 SDOperand NotN1 = getNode(ISD::XOR, XType, N1, getConstant(~0ULL, XType)); 932 return getNode(ISD::SRL, XType, getNode(ISD::AND, XType, NegN1, NotN1), 933 getConstant(MVT::getSizeInBits(XType)-1, 934 TLI.getShiftAmountTy())); 935 } 936 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 937 if (N2C && N2C->isAllOnesValue() && CC == ISD::SETGT) { 938 SDOperand Sign = getNode(ISD::SRL, XType, N1, 939 getConstant(MVT::getSizeInBits(XType)-1, 940 TLI.getShiftAmountTy())); 941 return getNode(ISD::XOR, XType, Sign, getConstant(1, XType)); 942 } 943 } 944 945 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 946 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 947 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 948 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 949 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 950 MVT::ValueType XType = N1.getValueType(); 951 if (SubC->isNullValue() && MVT::isInteger(XType)) { 952 SDOperand Shift = getNode(ISD::SRA, XType, N1, 953 getConstant(MVT::getSizeInBits(XType)-1, 954 TLI.getShiftAmountTy())); 955 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 956 Shift); 957 } 958 } 959 } 960 961 // Could not fold it. 962 return SDOperand(); 963} 964 965/// getNode - Gets or creates the specified node. 966/// 967SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 968 SDNode *N = new SDNode(Opcode, VT); 969 AllNodes.push_back(N); 970 return SDOperand(N, 0); 971} 972 973SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 974 SDOperand Operand) { 975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 976 uint64_t Val = C->getValue(); 977 switch (Opcode) { 978 default: break; 979 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 980 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 981 case ISD::TRUNCATE: return getConstant(Val, VT); 982 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 983 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 984 } 985 } 986 987 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 988 switch (Opcode) { 989 case ISD::FNEG: 990 return getConstantFP(-C->getValue(), VT); 991 case ISD::FP_ROUND: 992 case ISD::FP_EXTEND: 993 return getConstantFP(C->getValue(), VT); 994 case ISD::FP_TO_SINT: 995 return getConstant((int64_t)C->getValue(), VT); 996 case ISD::FP_TO_UINT: 997 return getConstant((uint64_t)C->getValue(), VT); 998 } 999 1000 unsigned OpOpcode = Operand.Val->getOpcode(); 1001 switch (Opcode) { 1002 case ISD::TokenFactor: 1003 return Operand; // Factor of one node? No factor. 1004 case ISD::SIGN_EXTEND: 1005 if (Operand.getValueType() == VT) return Operand; // noop extension 1006 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 1007 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1008 break; 1009 case ISD::ZERO_EXTEND: 1010 if (Operand.getValueType() == VT) return Operand; // noop extension 1011 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 1012 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 1013 break; 1014 case ISD::TRUNCATE: 1015 if (Operand.getValueType() == VT) return Operand; // noop truncate 1016 if (OpOpcode == ISD::TRUNCATE) 1017 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1018 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 1019 // If the source is smaller than the dest, we still need an extend. 1020 if (Operand.Val->getOperand(0).getValueType() < VT) 1021 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 1022 else if (Operand.Val->getOperand(0).getValueType() > VT) 1023 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 1024 else 1025 return Operand.Val->getOperand(0); 1026 } 1027 break; 1028 case ISD::FNEG: 1029 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 1030 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 1031 Operand.Val->getOperand(0)); 1032 if (OpOpcode == ISD::FNEG) // --X -> X 1033 return Operand.Val->getOperand(0); 1034 break; 1035 case ISD::FABS: 1036 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 1037 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 1038 break; 1039 } 1040 1041 SDNode *N; 1042 if (VT != MVT::Flag) { // Don't CSE flag producing nodes 1043 SDNode *&E = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 1044 if (E) return SDOperand(E, 0); 1045 E = N = new SDNode(Opcode, Operand); 1046 } else { 1047 N = new SDNode(Opcode, Operand); 1048 } 1049 N->setValueTypes(VT); 1050 AllNodes.push_back(N); 1051 return SDOperand(N, 0); 1052} 1053 1054/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1055/// this predicate to simplify operations downstream. V and Mask are known to 1056/// be the same type. 1057static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 1058 const TargetLowering &TLI) { 1059 unsigned SrcBits; 1060 if (Mask == 0) return true; 1061 1062 // If we know the result of a setcc has the top bits zero, use this info. 1063 switch (Op.getOpcode()) { 1064 case ISD::Constant: 1065 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 1066 1067 case ISD::SETCC: 1068 return ((Mask & 1) == 0) && 1069 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 1070 1071 case ISD::ZEXTLOAD: 1072 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 1073 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 1074 case ISD::ZERO_EXTEND: 1075 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 1076 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 1077 1078 case ISD::AND: 1079 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 1080 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1081 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 1082 1083 // FALL THROUGH 1084 case ISD::OR: 1085 case ISD::XOR: 1086 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 1087 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 1088 case ISD::SELECT: 1089 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 1090 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 1091 case ISD::SELECT_CC: 1092 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 1093 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 1094 case ISD::SRL: 1095 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 1096 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1097 uint64_t NewVal = Mask << ShAmt->getValue(); 1098 SrcBits = MVT::getSizeInBits(Op.getValueType()); 1099 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 1100 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1101 } 1102 return false; 1103 case ISD::SHL: 1104 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 1105 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1106 uint64_t NewVal = Mask >> ShAmt->getValue(); 1107 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1108 } 1109 return false; 1110 case ISD::CTTZ: 1111 case ISD::CTLZ: 1112 case ISD::CTPOP: 1113 // Bit counting instructions can not set the high bits of the result 1114 // register. The max number of bits sets depends on the input. 1115 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 1116 1117 // TODO we could handle some SRA cases here. 1118 default: break; 1119 } 1120 1121 return false; 1122} 1123 1124 1125 1126SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1127 SDOperand N1, SDOperand N2) { 1128#ifndef NDEBUG 1129 switch (Opcode) { 1130 case ISD::TokenFactor: 1131 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1132 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1133 break; 1134 case ISD::AND: 1135 case ISD::OR: 1136 case ISD::XOR: 1137 case ISD::UDIV: 1138 case ISD::UREM: 1139 case ISD::MULHU: 1140 case ISD::MULHS: 1141 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1142 // fall through 1143 case ISD::ADD: 1144 case ISD::SUB: 1145 case ISD::MUL: 1146 case ISD::SDIV: 1147 case ISD::SREM: 1148 assert(N1.getValueType() == N2.getValueType() && 1149 N1.getValueType() == VT && "Binary operator types must match!"); 1150 break; 1151 1152 case ISD::SHL: 1153 case ISD::SRA: 1154 case ISD::SRL: 1155 assert(VT == N1.getValueType() && 1156 "Shift operators return type must be the same as their first arg"); 1157 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1158 VT != MVT::i1 && "Shifts only work on integers"); 1159 break; 1160 case ISD::FP_ROUND_INREG: { 1161 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1162 assert(VT == N1.getValueType() && "Not an inreg round!"); 1163 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1164 "Cannot FP_ROUND_INREG integer types"); 1165 assert(EVT <= VT && "Not rounding down!"); 1166 break; 1167 } 1168 case ISD::SIGN_EXTEND_INREG: { 1169 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1170 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1171 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1172 "Cannot *_EXTEND_INREG FP types"); 1173 assert(EVT <= VT && "Not extending!"); 1174 } 1175 1176 default: break; 1177 } 1178#endif 1179 1180 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1181 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1182 if (N1C) { 1183 if (N2C) { 1184 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1185 switch (Opcode) { 1186 case ISD::ADD: return getConstant(C1 + C2, VT); 1187 case ISD::SUB: return getConstant(C1 - C2, VT); 1188 case ISD::MUL: return getConstant(C1 * C2, VT); 1189 case ISD::UDIV: 1190 if (C2) return getConstant(C1 / C2, VT); 1191 break; 1192 case ISD::UREM : 1193 if (C2) return getConstant(C1 % C2, VT); 1194 break; 1195 case ISD::SDIV : 1196 if (C2) return getConstant(N1C->getSignExtended() / 1197 N2C->getSignExtended(), VT); 1198 break; 1199 case ISD::SREM : 1200 if (C2) return getConstant(N1C->getSignExtended() % 1201 N2C->getSignExtended(), VT); 1202 break; 1203 case ISD::AND : return getConstant(C1 & C2, VT); 1204 case ISD::OR : return getConstant(C1 | C2, VT); 1205 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1206 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1207 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1208 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1209 default: break; 1210 } 1211 1212 } else { // Cannonicalize constant to RHS if commutative 1213 if (isCommutativeBinOp(Opcode)) { 1214 std::swap(N1C, N2C); 1215 std::swap(N1, N2); 1216 } 1217 } 1218 1219 switch (Opcode) { 1220 default: break; 1221 case ISD::SHL: // shl 0, X -> 0 1222 if (N1C->isNullValue()) return N1; 1223 break; 1224 case ISD::SRL: // srl 0, X -> 0 1225 if (N1C->isNullValue()) return N1; 1226 break; 1227 case ISD::SRA: // sra -1, X -> -1 1228 if (N1C->isAllOnesValue()) return N1; 1229 break; 1230 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1231 // Extending a constant? Just return the extended constant. 1232 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1233 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1234 } 1235 } 1236 1237 if (N2C) { 1238 uint64_t C2 = N2C->getValue(); 1239 1240 switch (Opcode) { 1241 case ISD::ADD: 1242 if (!C2) return N1; // add X, 0 -> X 1243 break; 1244 case ISD::SUB: 1245 if (!C2) return N1; // sub X, 0 -> X 1246 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1247 case ISD::MUL: 1248 if (!C2) return N2; // mul X, 0 -> 0 1249 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1250 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1251 1252 // FIXME: Move this to the DAG combiner when it exists. 1253 if ((C2 & C2-1) == 0) { 1254 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1255 return getNode(ISD::SHL, VT, N1, ShAmt); 1256 } 1257 break; 1258 1259 case ISD::MULHU: 1260 case ISD::MULHS: 1261 if (!C2) return N2; // mul X, 0 -> 0 1262 1263 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1264 return getConstant(0, VT); 1265 1266 // Many others could be handled here, including -1, powers of 2, etc. 1267 break; 1268 1269 case ISD::UDIV: 1270 // FIXME: Move this to the DAG combiner when it exists. 1271 if ((C2 & C2-1) == 0 && C2) { 1272 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1273 return getNode(ISD::SRL, VT, N1, ShAmt); 1274 } 1275 break; 1276 1277 case ISD::SHL: 1278 case ISD::SRL: 1279 case ISD::SRA: 1280 // If the shift amount is bigger than the size of the data, then all the 1281 // bits are shifted out. Simplify to undef. 1282 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1283 return getNode(ISD::UNDEF, N1.getValueType()); 1284 } 1285 if (C2 == 0) return N1; 1286 1287 if (Opcode == ISD::SRA) { 1288 // If the sign bit is known to be zero, switch this to a SRL. 1289 if (MaskedValueIsZero(N1, 1290 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1291 TLI)) 1292 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1293 } else { 1294 // If the part left over is known to be zero, the whole thing is zero. 1295 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1296 if (Opcode == ISD::SRL) { 1297 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1298 return getConstant(0, N1.getValueType()); 1299 } else if (Opcode == ISD::SHL) { 1300 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1301 return getConstant(0, N1.getValueType()); 1302 } 1303 } 1304 1305 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1306 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1307 unsigned OpSAC = OpSA->getValue(); 1308 if (N1.getOpcode() == ISD::SHL) { 1309 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1310 return getConstant(0, N1.getValueType()); 1311 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1312 getConstant(C2+OpSAC, N2.getValueType())); 1313 } else if (N1.getOpcode() == ISD::SRL) { 1314 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1315 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1316 getConstant(~0ULL << OpSAC, VT)); 1317 if (C2 > OpSAC) { 1318 return getNode(ISD::SHL, VT, Mask, 1319 getConstant(C2-OpSAC, N2.getValueType())); 1320 } else { 1321 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1322 return getNode(ISD::SRL, VT, Mask, 1323 getConstant(OpSAC-C2, N2.getValueType())); 1324 } 1325 } else if (N1.getOpcode() == ISD::SRA) { 1326 // if C1 == C2, just mask out low bits. 1327 if (C2 == OpSAC) 1328 return getNode(ISD::AND, VT, N1.getOperand(0), 1329 getConstant(~0ULL << C2, VT)); 1330 } 1331 } 1332 break; 1333 1334 case ISD::AND: 1335 if (!C2) return N2; // X and 0 -> 0 1336 if (N2C->isAllOnesValue()) 1337 return N1; // X and -1 -> X 1338 1339 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1340 return getConstant(0, VT); 1341 1342 { 1343 uint64_t NotC2 = ~C2; 1344 if (VT != MVT::i64) 1345 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1346 1347 if (MaskedValueIsZero(N1, NotC2, TLI)) 1348 return N1; // if (X & ~C2) -> 0, the and is redundant 1349 } 1350 1351 // FIXME: Should add a corresponding version of this for 1352 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1353 // we don't have yet. 1354 1355 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1356 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1357 // If we are masking out the part of our input that was extended, just 1358 // mask the input to the extension directly. 1359 unsigned ExtendBits = 1360 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1361 if ((C2 & (~0ULL << ExtendBits)) == 0) 1362 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1363 } else if (N1.getOpcode() == ISD::OR) { 1364 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1365 if ((ORI->getValue() & C2) == C2) { 1366 // If the 'or' is setting all of the bits that we are masking for, 1367 // we know the result of the AND will be the AND mask itself. 1368 return N2; 1369 } 1370 } 1371 break; 1372 case ISD::OR: 1373 if (!C2)return N1; // X or 0 -> X 1374 if (N2C->isAllOnesValue()) 1375 return N2; // X or -1 -> -1 1376 break; 1377 case ISD::XOR: 1378 if (!C2) return N1; // X xor 0 -> X 1379 if (N2C->isAllOnesValue()) { 1380 if (N1.Val->getOpcode() == ISD::SETCC){ 1381 SDNode *SetCC = N1.Val; 1382 // !(X op Y) -> (X !op Y) 1383 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1384 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1385 return getSetCC(SetCC->getValueType(0), 1386 SetCC->getOperand(0), SetCC->getOperand(1), 1387 ISD::getSetCCInverse(CC, isInteger)); 1388 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1389 SDNode *Op = N1.Val; 1390 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1391 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1392 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1393 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1394 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1395 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1396 if (Op->getOpcode() == ISD::AND) 1397 return getNode(ISD::OR, VT, LHS, RHS); 1398 return getNode(ISD::AND, VT, LHS, RHS); 1399 } 1400 } 1401 // X xor -1 -> not(x) ? 1402 } 1403 break; 1404 } 1405 1406 // Reassociate ((X op C1) op C2) if possible. 1407 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1408 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1409 return getNode(Opcode, VT, N1.Val->getOperand(0), 1410 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1411 } 1412 1413 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1414 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1415 if (N1CFP) { 1416 if (N2CFP) { 1417 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1418 switch (Opcode) { 1419 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1420 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1421 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1422 case ISD::SDIV: 1423 if (C2) return getConstantFP(C1 / C2, VT); 1424 break; 1425 case ISD::SREM : 1426 if (C2) return getConstantFP(fmod(C1, C2), VT); 1427 break; 1428 default: break; 1429 } 1430 1431 } else { // Cannonicalize constant to RHS if commutative 1432 if (isCommutativeBinOp(Opcode)) { 1433 std::swap(N1CFP, N2CFP); 1434 std::swap(N1, N2); 1435 } 1436 } 1437 1438 if (Opcode == ISD::FP_ROUND_INREG) 1439 return getNode(ISD::FP_EXTEND, VT, 1440 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1441 } 1442 1443 // Finally, fold operations that do not require constants. 1444 switch (Opcode) { 1445 case ISD::TokenFactor: 1446 if (N1.getOpcode() == ISD::EntryToken) 1447 return N2; 1448 if (N2.getOpcode() == ISD::EntryToken) 1449 return N1; 1450 break; 1451 1452 case ISD::AND: 1453 case ISD::OR: 1454 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1455 SDNode *LHS = N1.Val, *RHS = N2.Val; 1456 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1457 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1458 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1459 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1460 1461 if (LR == RR && isa<ConstantSDNode>(LR) && 1462 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1463 // (X != 0) | (Y != 0) -> (X|Y != 0) 1464 // (X == 0) & (Y == 0) -> (X|Y == 0) 1465 // (X < 0) | (Y < 0) -> (X|Y < 0) 1466 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1467 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1468 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1469 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1470 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1471 Op2); 1472 1473 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1474 // (X == -1) & (Y == -1) -> (X&Y == -1) 1475 // (X != -1) | (Y != -1) -> (X&Y != -1) 1476 // (X > -1) | (Y > -1) -> (X&Y > -1) 1477 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1478 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1479 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1480 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1481 LR, Op2); 1482 // (X > -1) & (Y > -1) -> (X|Y > -1) 1483 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1484 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1485 LR, Op2); 1486 } 1487 } 1488 1489 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1490 if (LL == RR && LR == RL) { 1491 Op2 = ISD::getSetCCSwappedOperands(Op2); 1492 goto MatchedBackwards; 1493 } 1494 1495 if (LL == RL && LR == RR) { 1496 MatchedBackwards: 1497 ISD::CondCode Result; 1498 bool isInteger = MVT::isInteger(LL.getValueType()); 1499 if (Opcode == ISD::OR) 1500 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1501 else 1502 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1503 1504 if (Result != ISD::SETCC_INVALID) 1505 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1506 } 1507 } 1508 1509 // and/or zext(a), zext(b) -> zext(and/or a, b) 1510 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1511 N2.getOpcode() == ISD::ZERO_EXTEND && 1512 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1513 return getNode(ISD::ZERO_EXTEND, VT, 1514 getNode(Opcode, N1.getOperand(0).getValueType(), 1515 N1.getOperand(0), N2.getOperand(0))); 1516 break; 1517 case ISD::XOR: 1518 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1519 break; 1520 case ISD::ADD: 1521 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1522 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1523 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1524 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1525 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1526 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1527 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1528 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1529 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1530 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1531 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1532 !MVT::isFloatingPoint(N2.getValueType())) 1533 return N2.Val->getOperand(0); // A+(B-A) -> B 1534 break; 1535 case ISD::SUB: 1536 if (N1.getOpcode() == ISD::ADD) { 1537 if (N1.Val->getOperand(0) == N2 && 1538 !MVT::isFloatingPoint(N2.getValueType())) 1539 return N1.Val->getOperand(1); // (A+B)-A == B 1540 if (N1.Val->getOperand(1) == N2 && 1541 !MVT::isFloatingPoint(N2.getValueType())) 1542 return N1.Val->getOperand(0); // (A+B)-B == A 1543 } 1544 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1545 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1546 break; 1547 case ISD::FP_ROUND_INREG: 1548 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1549 break; 1550 case ISD::SIGN_EXTEND_INREG: { 1551 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1552 if (EVT == VT) return N1; // Not actually extending 1553 1554 // If we are sign extending an extension, use the original source. 1555 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1556 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1557 return N1; 1558 1559 // If we are sign extending a sextload, return just the load. 1560 if (N1.getOpcode() == ISD::SEXTLOAD) 1561 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1562 return N1; 1563 1564 // If we are extending the result of a setcc, and we already know the 1565 // contents of the top bits, eliminate the extension. 1566 if (N1.getOpcode() == ISD::SETCC && 1567 TLI.getSetCCResultContents() == 1568 TargetLowering::ZeroOrNegativeOneSetCCResult) 1569 return N1; 1570 1571 // If we are sign extending the result of an (and X, C) operation, and we 1572 // know the extended bits are zeros already, don't do the extend. 1573 if (N1.getOpcode() == ISD::AND) 1574 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1575 uint64_t Mask = N1C->getValue(); 1576 unsigned NumBits = MVT::getSizeInBits(EVT); 1577 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1578 return N1; 1579 } 1580 break; 1581 } 1582 1583 // FIXME: figure out how to safely handle things like 1584 // int foo(int x) { return 1 << (x & 255); } 1585 // int bar() { return foo(256); } 1586#if 0 1587 case ISD::SHL: 1588 case ISD::SRL: 1589 case ISD::SRA: 1590 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1591 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1592 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1593 else if (N2.getOpcode() == ISD::AND) 1594 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1595 // If the and is only masking out bits that cannot effect the shift, 1596 // eliminate the and. 1597 unsigned NumBits = MVT::getSizeInBits(VT); 1598 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1599 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1600 } 1601 break; 1602#endif 1603 } 1604 1605 // Memoize this node if possible. 1606 SDNode *N; 1607 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END && 1608 VT != MVT::Flag) { 1609 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1610 if (BON) return SDOperand(BON, 0); 1611 1612 BON = N = new SDNode(Opcode, N1, N2); 1613 } else { 1614 N = new SDNode(Opcode, N1, N2); 1615 } 1616 1617 N->setValueTypes(VT); 1618 AllNodes.push_back(N); 1619 return SDOperand(N, 0); 1620} 1621 1622// setAdjCallChain - This method changes the token chain of an 1623// CALLSEQ_START/END node to be the specified operand. 1624void SDNode::setAdjCallChain(SDOperand N) { 1625 assert(N.getValueType() == MVT::Other); 1626 assert((getOpcode() == ISD::CALLSEQ_START || 1627 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1628 1629 Operands[0].Val->removeUser(this); 1630 Operands[0] = N; 1631 N.Val->Uses.push_back(this); 1632} 1633 1634 1635 1636SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1637 SDOperand Chain, SDOperand Ptr, 1638 SDOperand SV) { 1639 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1640 if (N) return SDOperand(N, 0); 1641 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1642 1643 // Loads have a token chain. 1644 N->setValueTypes(VT, MVT::Other); 1645 AllNodes.push_back(N); 1646 return SDOperand(N, 0); 1647} 1648 1649 1650SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1651 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1652 MVT::ValueType EVT) { 1653 std::vector<SDOperand> Ops; 1654 Ops.reserve(4); 1655 Ops.push_back(Chain); 1656 Ops.push_back(Ptr); 1657 Ops.push_back(SV); 1658 Ops.push_back(getValueType(EVT)); 1659 std::vector<MVT::ValueType> VTs; 1660 VTs.reserve(2); 1661 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1662 return getNode(Opcode, VTs, Ops); 1663} 1664 1665SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1666 SDOperand N1, SDOperand N2, SDOperand N3) { 1667 // Perform various simplifications. 1668 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1669 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1670 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1671 switch (Opcode) { 1672 case ISD::SETCC: { 1673 // Use SimplifySetCC to simplify SETCC's. 1674 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1675 if (Simp.Val) return Simp; 1676 break; 1677 } 1678 case ISD::SELECT: 1679 if (N1C) 1680 if (N1C->getValue()) 1681 return N2; // select true, X, Y -> X 1682 else 1683 return N3; // select false, X, Y -> Y 1684 1685 if (N2 == N3) return N2; // select C, X, X -> X 1686 1687 if (VT == MVT::i1) { // Boolean SELECT 1688 if (N2C) { 1689 if (N2C->getValue()) // select C, 1, X -> C | X 1690 return getNode(ISD::OR, VT, N1, N3); 1691 else // select C, 0, X -> ~C & X 1692 return getNode(ISD::AND, VT, 1693 getNode(ISD::XOR, N1.getValueType(), N1, 1694 getConstant(1, N1.getValueType())), N3); 1695 } else if (N3C) { 1696 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1697 return getNode(ISD::OR, VT, 1698 getNode(ISD::XOR, N1.getValueType(), N1, 1699 getConstant(1, N1.getValueType())), N2); 1700 else // select C, X, 0 -> C & X 1701 return getNode(ISD::AND, VT, N1, N2); 1702 } 1703 1704 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1705 return getNode(ISD::OR, VT, N1, N3); 1706 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1707 return getNode(ISD::AND, VT, N1, N2); 1708 } 1709 if (N1.getOpcode() == ISD::SETCC) { 1710 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1711 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1712 if (Simp.Val) return Simp; 1713 } 1714 break; 1715 case ISD::BRCOND: 1716 if (N2C) 1717 if (N2C->getValue()) // Unconditional branch 1718 return getNode(ISD::BR, MVT::Other, N1, N3); 1719 else 1720 return N1; // Never-taken branch 1721 break; 1722 } 1723 1724 std::vector<SDOperand> Ops; 1725 Ops.reserve(3); 1726 Ops.push_back(N1); 1727 Ops.push_back(N2); 1728 Ops.push_back(N3); 1729 1730 // Memoize node if it doesn't produce a flag. 1731 SDNode *N; 1732 if (VT != MVT::Flag) { 1733 SDNode *&E = OneResultNodes[std::make_pair(Opcode,std::make_pair(VT, Ops))]; 1734 if (E) return SDOperand(E, 0); 1735 E = N = new SDNode(Opcode, N1, N2, N3); 1736 } else { 1737 N = new SDNode(Opcode, N1, N2, N3); 1738 } 1739 N->setValueTypes(VT); 1740 AllNodes.push_back(N); 1741 return SDOperand(N, 0); 1742} 1743 1744SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1745 SDOperand N1, SDOperand N2, SDOperand N3, 1746 SDOperand N4) { 1747 std::vector<SDOperand> Ops; 1748 Ops.reserve(4); 1749 Ops.push_back(N1); 1750 Ops.push_back(N2); 1751 Ops.push_back(N3); 1752 Ops.push_back(N4); 1753 return getNode(Opcode, VT, Ops); 1754} 1755 1756SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1757 SDOperand N1, SDOperand N2, SDOperand N3, 1758 SDOperand N4, SDOperand N5) { 1759 std::vector<SDOperand> Ops; 1760 Ops.reserve(5); 1761 Ops.push_back(N1); 1762 Ops.push_back(N2); 1763 Ops.push_back(N3); 1764 Ops.push_back(N4); 1765 Ops.push_back(N5); 1766 return getNode(Opcode, VT, Ops); 1767} 1768 1769 1770SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1771 assert((!V || isa<PointerType>(V->getType())) && 1772 "SrcValue is not a pointer?"); 1773 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1774 if (N) return SDOperand(N, 0); 1775 1776 N = new SrcValueSDNode(V, Offset); 1777 AllNodes.push_back(N); 1778 return SDOperand(N, 0); 1779} 1780 1781SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1782 std::vector<SDOperand> &Ops) { 1783 switch (Ops.size()) { 1784 case 0: return getNode(Opcode, VT); 1785 case 1: return getNode(Opcode, VT, Ops[0]); 1786 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1787 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1788 default: break; 1789 } 1790 1791 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1792 switch (Opcode) { 1793 default: break; 1794 case ISD::BRCONDTWOWAY: 1795 if (N1C) 1796 if (N1C->getValue()) // Unconditional branch to true dest. 1797 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1798 else // Unconditional branch to false dest. 1799 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1800 break; 1801 case ISD::BRTWOWAY_CC: 1802 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1803 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1804 "LHS and RHS of comparison must have same type!"); 1805 break; 1806 case ISD::TRUNCSTORE: { 1807 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1808 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1809#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1810 // If this is a truncating store of a constant, convert to the desired type 1811 // and store it instead. 1812 if (isa<Constant>(Ops[0])) { 1813 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1814 if (isa<Constant>(Op)) 1815 N1 = Op; 1816 } 1817 // Also for ConstantFP? 1818#endif 1819 if (Ops[0].getValueType() == EVT) // Normal store? 1820 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1821 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1822 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1823 "Can't do FP-INT conversion!"); 1824 break; 1825 } 1826 case ISD::SELECT_CC: { 1827 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1828 assert(Ops[0].getValueType() == Ops[1].getValueType() && 1829 "LHS and RHS of condition must have same type!"); 1830 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1831 "True and False arms of SelectCC must have same type!"); 1832 assert(Ops[2].getValueType() == VT && 1833 "select_cc node must be of same type as true and false value!"); 1834 SDOperand Simp = SimplifySelectCC(Ops[0], Ops[1], Ops[2], Ops[3], 1835 cast<CondCodeSDNode>(Ops[4])->get()); 1836 if (Simp.Val) return Simp; 1837 break; 1838 } 1839 case ISD::BR_CC: { 1840 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1841 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1842 "LHS/RHS of comparison should match types!"); 1843 // Use SimplifySetCC to simplify SETCC's. 1844 SDOperand Simp = SimplifySetCC(MVT::i1, Ops[2], Ops[3], 1845 cast<CondCodeSDNode>(Ops[1])->get()); 1846 if (Simp.Val) { 1847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Simp)) { 1848 if (C->getValue() & 1) // Unconditional branch 1849 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[4]); 1850 else 1851 return Ops[0]; // Unconditional Fall through 1852 } else if (Simp.Val->getOpcode() == ISD::SETCC) { 1853 Ops[2] = Simp.getOperand(0); 1854 Ops[3] = Simp.getOperand(1); 1855 Ops[1] = Simp.getOperand(2); 1856 } 1857 } 1858 break; 1859 } 1860 } 1861 1862 // Memoize nodes. 1863 SDNode *N; 1864 if (VT != MVT::Flag) { 1865 SDNode *&E = 1866 OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1867 if (E) return SDOperand(E, 0); 1868 E = N = new SDNode(Opcode, Ops); 1869 } else { 1870 N = new SDNode(Opcode, Ops); 1871 } 1872 N->setValueTypes(VT); 1873 AllNodes.push_back(N); 1874 return SDOperand(N, 0); 1875} 1876 1877SDOperand SelectionDAG::getNode(unsigned Opcode, 1878 std::vector<MVT::ValueType> &ResultTys, 1879 std::vector<SDOperand> &Ops) { 1880 if (ResultTys.size() == 1) 1881 return getNode(Opcode, ResultTys[0], Ops); 1882 1883 switch (Opcode) { 1884 case ISD::EXTLOAD: 1885 case ISD::SEXTLOAD: 1886 case ISD::ZEXTLOAD: { 1887 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1888 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1889 // If they are asking for an extending load from/to the same thing, return a 1890 // normal load. 1891 if (ResultTys[0] == EVT) 1892 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1893 assert(EVT < ResultTys[0] && 1894 "Should only be an extending load, not truncating!"); 1895 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1896 "Cannot sign/zero extend a FP load!"); 1897 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1898 "Cannot convert from FP to Int or Int -> FP!"); 1899 break; 1900 } 1901 1902 // FIXME: figure out how to safely handle things like 1903 // int foo(int x) { return 1 << (x & 255); } 1904 // int bar() { return foo(256); } 1905#if 0 1906 case ISD::SRA_PARTS: 1907 case ISD::SRL_PARTS: 1908 case ISD::SHL_PARTS: 1909 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1910 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1911 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1912 else if (N3.getOpcode() == ISD::AND) 1913 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1914 // If the and is only masking out bits that cannot effect the shift, 1915 // eliminate the and. 1916 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1917 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1918 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1919 } 1920 break; 1921#endif 1922 } 1923 1924 // Memoize the node unless it returns a flag. 1925 SDNode *N; 1926 if (ResultTys.back() != MVT::Flag) { 1927 SDNode *&E = 1928 ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, Ops))]; 1929 if (E) return SDOperand(E, 0); 1930 E = N = new SDNode(Opcode, Ops); 1931 } else { 1932 N = new SDNode(Opcode, Ops); 1933 } 1934 N->setValueTypes(ResultTys); 1935 AllNodes.push_back(N); 1936 return SDOperand(N, 0); 1937} 1938 1939 1940/// SelectNodeTo - These are used for target selectors to *mutate* the 1941/// specified node to have the specified return type, Target opcode, and 1942/// operands. Note that target opcodes are stored as 1943/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1944void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1945 MVT::ValueType VT) { 1946 RemoveNodeFromCSEMaps(N); 1947 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1948 N->setValueTypes(VT); 1949} 1950void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1951 MVT::ValueType VT, SDOperand Op1) { 1952 RemoveNodeFromCSEMaps(N); 1953 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1954 N->setValueTypes(VT); 1955 N->setOperands(Op1); 1956} 1957void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1958 MVT::ValueType VT, SDOperand Op1, 1959 SDOperand Op2) { 1960 RemoveNodeFromCSEMaps(N); 1961 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1962 N->setValueTypes(VT); 1963 N->setOperands(Op1, Op2); 1964} 1965void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1966 MVT::ValueType VT1, MVT::ValueType VT2, 1967 SDOperand Op1, SDOperand Op2) { 1968 RemoveNodeFromCSEMaps(N); 1969 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1970 N->setValueTypes(VT1, VT2); 1971 N->setOperands(Op1, Op2); 1972} 1973void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1974 MVT::ValueType VT, SDOperand Op1, 1975 SDOperand Op2, SDOperand Op3) { 1976 RemoveNodeFromCSEMaps(N); 1977 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1978 N->setValueTypes(VT); 1979 N->setOperands(Op1, Op2, Op3); 1980} 1981void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1982 MVT::ValueType VT1, MVT::ValueType VT2, 1983 SDOperand Op1, SDOperand Op2, SDOperand Op3) { 1984 RemoveNodeFromCSEMaps(N); 1985 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1986 N->setValueTypes(VT1, VT2); 1987 N->setOperands(Op1, Op2, Op3); 1988} 1989 1990void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1991 MVT::ValueType VT, SDOperand Op1, 1992 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 1993 RemoveNodeFromCSEMaps(N); 1994 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1995 N->setValueTypes(VT); 1996 N->setOperands(Op1, Op2, Op3, Op4); 1997} 1998void SelectionDAG::SelectNodeTo(SDNode *N, unsigned TargetOpc, 1999 MVT::ValueType VT, SDOperand Op1, 2000 SDOperand Op2, SDOperand Op3, SDOperand Op4, 2001 SDOperand Op5) { 2002 RemoveNodeFromCSEMaps(N); 2003 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 2004 N->setValueTypes(VT); 2005 N->setOperands(Op1, Op2, Op3, Op4, Op5); 2006} 2007 2008/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 2009/// This can cause recursive merging of nodes in the DAG. 2010/// 2011void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 2012 assert(From != To && "Cannot replace uses of with self"); 2013 while (!From->use_empty()) { 2014 // Process users until they are all gone. 2015 SDNode *U = *From->use_begin(); 2016 2017 // This node is about to morph, remove its old self from the CSE maps. 2018 RemoveNodeFromCSEMaps(U); 2019 2020 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2021 if (U->getOperand(i).Val == From) { 2022 assert(U->getOperand(i).getValueType() == 2023 To->getValueType(U->getOperand(i).ResNo)); 2024 From->removeUser(U); 2025 U->Operands[i].Val = To; 2026 To->addUser(U); 2027 } 2028 2029 // Now that we have modified U, add it back to the CSE maps. If it already 2030 // exists there, recursively merge the results together. 2031 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 2032 ReplaceAllUsesWith(U, Existing); 2033 // U is now dead. 2034 } 2035} 2036 2037void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 2038 const std::vector<SDOperand> &To) { 2039 assert(From->getNumValues() == To.size() && 2040 "Incorrect number of values to replace with!"); 2041 if (To.size() == 1 && To[0].ResNo == 0) { 2042 // Degenerate case handled above. 2043 ReplaceAllUsesWith(From, To[0].Val); 2044 return; 2045 } 2046 2047 while (!From->use_empty()) { 2048 // Process users until they are all gone. 2049 SDNode *U = *From->use_begin(); 2050 2051 // This node is about to morph, remove its old self from the CSE maps. 2052 RemoveNodeFromCSEMaps(U); 2053 2054 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 2055 if (U->getOperand(i).Val == From) { 2056 const SDOperand &ToOp = To[U->getOperand(i).ResNo]; 2057 assert(U->getOperand(i).getValueType() == ToOp.getValueType()); 2058 From->removeUser(U); 2059 U->Operands[i] = ToOp; 2060 ToOp.Val->addUser(U); 2061 } 2062 2063 // Now that we have modified U, add it back to the CSE maps. If it already 2064 // exists there, recursively merge the results together. 2065 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 2066 ReplaceAllUsesWith(U, Existing); 2067 // U is now dead. 2068 } 2069} 2070 2071 2072//===----------------------------------------------------------------------===// 2073// SDNode Class 2074//===----------------------------------------------------------------------===// 2075 2076/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 2077/// indicated value. This method ignores uses of other values defined by this 2078/// operation. 2079bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 2080 assert(Value < getNumValues() && "Bad value!"); 2081 2082 // If there is only one value, this is easy. 2083 if (getNumValues() == 1) 2084 return use_size() == NUses; 2085 if (Uses.size() < NUses) return false; 2086 2087 SDOperand TheValue(this, Value); 2088 2089 std::set<SDNode*> UsersHandled; 2090 2091 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 2092 UI != E; ++UI) { 2093 SDNode *User = *UI; 2094 if (User->getNumOperands() == 1 || 2095 UsersHandled.insert(User).second) // First time we've seen this? 2096 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2097 if (User->getOperand(i) == TheValue) { 2098 if (NUses == 0) 2099 return false; // too many uses 2100 --NUses; 2101 } 2102 } 2103 2104 // Found exactly the right number of uses? 2105 return NUses == 0; 2106} 2107 2108 2109const char *SDNode::getOperationName(const SelectionDAG *G) const { 2110 switch (getOpcode()) { 2111 default: 2112 if (getOpcode() < ISD::BUILTIN_OP_END) 2113 return "<<Unknown DAG Node>>"; 2114 else { 2115 if (G) 2116 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 2117 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 2118 return "<<Unknown Target Node>>"; 2119 } 2120 2121 case ISD::PCMARKER: return "PCMarker"; 2122 case ISD::SRCVALUE: return "SrcValue"; 2123 case ISD::VALUETYPE: return "ValueType"; 2124 case ISD::EntryToken: return "EntryToken"; 2125 case ISD::TokenFactor: return "TokenFactor"; 2126 case ISD::Constant: return "Constant"; 2127 case ISD::TargetConstant: return "TargetConstant"; 2128 case ISD::ConstantFP: return "ConstantFP"; 2129 case ISD::GlobalAddress: return "GlobalAddress"; 2130 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 2131 case ISD::FrameIndex: return "FrameIndex"; 2132 case ISD::TargetFrameIndex: return "TargetFrameIndex"; 2133 case ISD::BasicBlock: return "BasicBlock"; 2134 case ISD::Register: return "Register"; 2135 case ISD::ExternalSymbol: return "ExternalSymbol"; 2136 case ISD::ConstantPool: return "ConstantPool"; 2137 case ISD::TargetConstantPool: return "TargetConstantPool"; 2138 case ISD::CopyToReg: return "CopyToReg"; 2139 case ISD::CopyFromReg: return "CopyFromReg"; 2140 case ISD::ImplicitDef: return "ImplicitDef"; 2141 case ISD::UNDEF: return "undef"; 2142 2143 // Unary operators 2144 case ISD::FABS: return "fabs"; 2145 case ISD::FNEG: return "fneg"; 2146 case ISD::FSQRT: return "fsqrt"; 2147 case ISD::FSIN: return "fsin"; 2148 case ISD::FCOS: return "fcos"; 2149 2150 // Binary operators 2151 case ISD::ADD: return "add"; 2152 case ISD::SUB: return "sub"; 2153 case ISD::MUL: return "mul"; 2154 case ISD::MULHU: return "mulhu"; 2155 case ISD::MULHS: return "mulhs"; 2156 case ISD::SDIV: return "sdiv"; 2157 case ISD::UDIV: return "udiv"; 2158 case ISD::SREM: return "srem"; 2159 case ISD::UREM: return "urem"; 2160 case ISD::AND: return "and"; 2161 case ISD::OR: return "or"; 2162 case ISD::XOR: return "xor"; 2163 case ISD::SHL: return "shl"; 2164 case ISD::SRA: return "sra"; 2165 case ISD::SRL: return "srl"; 2166 2167 case ISD::SETCC: return "setcc"; 2168 case ISD::SELECT: return "select"; 2169 case ISD::SELECT_CC: return "select_cc"; 2170 case ISD::ADD_PARTS: return "add_parts"; 2171 case ISD::SUB_PARTS: return "sub_parts"; 2172 case ISD::SHL_PARTS: return "shl_parts"; 2173 case ISD::SRA_PARTS: return "sra_parts"; 2174 case ISD::SRL_PARTS: return "srl_parts"; 2175 2176 // Conversion operators. 2177 case ISD::SIGN_EXTEND: return "sign_extend"; 2178 case ISD::ZERO_EXTEND: return "zero_extend"; 2179 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 2180 case ISD::TRUNCATE: return "truncate"; 2181 case ISD::FP_ROUND: return "fp_round"; 2182 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2183 case ISD::FP_EXTEND: return "fp_extend"; 2184 2185 case ISD::SINT_TO_FP: return "sint_to_fp"; 2186 case ISD::UINT_TO_FP: return "uint_to_fp"; 2187 case ISD::FP_TO_SINT: return "fp_to_sint"; 2188 case ISD::FP_TO_UINT: return "fp_to_uint"; 2189 2190 // Control flow instructions 2191 case ISD::BR: return "br"; 2192 case ISD::BRCOND: return "brcond"; 2193 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2194 case ISD::BR_CC: return "br_cc"; 2195 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2196 case ISD::RET: return "ret"; 2197 case ISD::CALL: return "call"; 2198 case ISD::TAILCALL:return "tailcall"; 2199 case ISD::CALLSEQ_START: return "callseq_start"; 2200 case ISD::CALLSEQ_END: return "callseq_end"; 2201 2202 // Other operators 2203 case ISD::LOAD: return "load"; 2204 case ISD::STORE: return "store"; 2205 case ISD::EXTLOAD: return "extload"; 2206 case ISD::SEXTLOAD: return "sextload"; 2207 case ISD::ZEXTLOAD: return "zextload"; 2208 case ISD::TRUNCSTORE: return "truncstore"; 2209 2210 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2211 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2212 case ISD::BUILD_PAIR: return "build_pair"; 2213 case ISD::MEMSET: return "memset"; 2214 case ISD::MEMCPY: return "memcpy"; 2215 case ISD::MEMMOVE: return "memmove"; 2216 2217 // Bit counting 2218 case ISD::CTPOP: return "ctpop"; 2219 case ISD::CTTZ: return "cttz"; 2220 case ISD::CTLZ: return "ctlz"; 2221 2222 // IO Intrinsics 2223 case ISD::READPORT: return "readport"; 2224 case ISD::WRITEPORT: return "writeport"; 2225 case ISD::READIO: return "readio"; 2226 case ISD::WRITEIO: return "writeio"; 2227 2228 case ISD::CONDCODE: 2229 switch (cast<CondCodeSDNode>(this)->get()) { 2230 default: assert(0 && "Unknown setcc condition!"); 2231 case ISD::SETOEQ: return "setoeq"; 2232 case ISD::SETOGT: return "setogt"; 2233 case ISD::SETOGE: return "setoge"; 2234 case ISD::SETOLT: return "setolt"; 2235 case ISD::SETOLE: return "setole"; 2236 case ISD::SETONE: return "setone"; 2237 2238 case ISD::SETO: return "seto"; 2239 case ISD::SETUO: return "setuo"; 2240 case ISD::SETUEQ: return "setue"; 2241 case ISD::SETUGT: return "setugt"; 2242 case ISD::SETUGE: return "setuge"; 2243 case ISD::SETULT: return "setult"; 2244 case ISD::SETULE: return "setule"; 2245 case ISD::SETUNE: return "setune"; 2246 2247 case ISD::SETEQ: return "seteq"; 2248 case ISD::SETGT: return "setgt"; 2249 case ISD::SETGE: return "setge"; 2250 case ISD::SETLT: return "setlt"; 2251 case ISD::SETLE: return "setle"; 2252 case ISD::SETNE: return "setne"; 2253 } 2254 } 2255} 2256 2257void SDNode::dump() const { dump(0); } 2258void SDNode::dump(const SelectionDAG *G) const { 2259 std::cerr << (void*)this << ": "; 2260 2261 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2262 if (i) std::cerr << ","; 2263 if (getValueType(i) == MVT::Other) 2264 std::cerr << "ch"; 2265 else 2266 std::cerr << MVT::getValueTypeString(getValueType(i)); 2267 } 2268 std::cerr << " = " << getOperationName(G); 2269 2270 std::cerr << " "; 2271 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2272 if (i) std::cerr << ", "; 2273 std::cerr << (void*)getOperand(i).Val; 2274 if (unsigned RN = getOperand(i).ResNo) 2275 std::cerr << ":" << RN; 2276 } 2277 2278 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2279 std::cerr << "<" << CSDN->getValue() << ">"; 2280 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2281 std::cerr << "<" << CSDN->getValue() << ">"; 2282 } else if (const GlobalAddressSDNode *GADN = 2283 dyn_cast<GlobalAddressSDNode>(this)) { 2284 std::cerr << "<"; 2285 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2286 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2287 std::cerr << "<" << FIDN->getIndex() << ">"; 2288 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2289 std::cerr << "<" << *CP->get() << ">"; 2290 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2291 std::cerr << "<"; 2292 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2293 if (LBB) 2294 std::cerr << LBB->getName() << " "; 2295 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2296 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2297 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2298 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2299 } else { 2300 std::cerr << " #" << R->getReg(); 2301 } 2302 } else if (const ExternalSymbolSDNode *ES = 2303 dyn_cast<ExternalSymbolSDNode>(this)) { 2304 std::cerr << "'" << ES->getSymbol() << "'"; 2305 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2306 if (M->getValue()) 2307 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2308 else 2309 std::cerr << "<null:" << M->getOffset() << ">"; 2310 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2311 std::cerr << ":" << getValueTypeString(N->getVT()); 2312 } 2313} 2314 2315static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2316 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2317 if (N->getOperand(i).Val->hasOneUse()) 2318 DumpNodes(N->getOperand(i).Val, indent+2, G); 2319 else 2320 std::cerr << "\n" << std::string(indent+2, ' ') 2321 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2322 2323 2324 std::cerr << "\n" << std::string(indent, ' '); 2325 N->dump(G); 2326} 2327 2328void SelectionDAG::dump() const { 2329 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2330 std::vector<SDNode*> Nodes(AllNodes); 2331 std::sort(Nodes.begin(), Nodes.end()); 2332 2333 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2334 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2335 DumpNodes(Nodes[i], 2, this); 2336 } 2337 2338 DumpNodes(getRoot().Val, 2, this); 2339 2340 std::cerr << "\n\n"; 2341} 2342 2343