SelectionDAG.cpp revision 7b2880c4cd29f5a90ac8af897f970b3199a9bbb1
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/MRegisterInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetInstrInfo.h" 23#include "llvm/Target/TargetMachine.h" 24#include <iostream> 25#include <set> 26#include <cmath> 27#include <algorithm> 28using namespace llvm; 29 30static bool isCommutativeBinOp(unsigned Opcode) { 31 switch (Opcode) { 32 case ISD::ADD: 33 case ISD::MUL: 34 case ISD::AND: 35 case ISD::OR: 36 case ISD::XOR: return true; 37 default: return false; // FIXME: Need commutative info for user ops! 38 } 39} 40 41static bool isAssociativeBinOp(unsigned Opcode) { 42 switch (Opcode) { 43 case ISD::ADD: 44 case ISD::MUL: 45 case ISD::AND: 46 case ISD::OR: 47 case ISD::XOR: return true; 48 default: return false; // FIXME: Need associative info for user ops! 49 } 50} 51 52// isInvertibleForFree - Return true if there is no cost to emitting the logical 53// inverse of this node. 54static bool isInvertibleForFree(SDOperand N) { 55 if (isa<ConstantSDNode>(N.Val)) return true; 56 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 57 return true; 58 return false; 59} 60 61//===----------------------------------------------------------------------===// 62// ConstantFPSDNode Class 63//===----------------------------------------------------------------------===// 64 65/// isExactlyValue - We don't rely on operator== working on double values, as 66/// it returns true for things that are clearly not equal, like -0.0 and 0.0. 67/// As such, this method can be used to do an exact bit-for-bit comparison of 68/// two floating point values. 69bool ConstantFPSDNode::isExactlyValue(double V) const { 70 return DoubleToBits(V) == DoubleToBits(Value); 71} 72 73//===----------------------------------------------------------------------===// 74// ISD Class 75//===----------------------------------------------------------------------===// 76 77/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 78/// when given the operation for (X op Y). 79ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 80 // To perform this operation, we just need to swap the L and G bits of the 81 // operation. 82 unsigned OldL = (Operation >> 2) & 1; 83 unsigned OldG = (Operation >> 1) & 1; 84 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 85 (OldL << 1) | // New G bit 86 (OldG << 2)); // New L bit. 87} 88 89/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 90/// 'op' is a valid SetCC operation. 91ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 92 unsigned Operation = Op; 93 if (isInteger) 94 Operation ^= 7; // Flip L, G, E bits, but not U. 95 else 96 Operation ^= 15; // Flip all of the condition bits. 97 if (Operation > ISD::SETTRUE2) 98 Operation &= ~8; // Don't let N and U bits get set. 99 return ISD::CondCode(Operation); 100} 101 102 103/// isSignedOp - For an integer comparison, return 1 if the comparison is a 104/// signed operation and 2 if the result is an unsigned comparison. Return zero 105/// if the operation does not depend on the sign of the input (setne and seteq). 106static int isSignedOp(ISD::CondCode Opcode) { 107 switch (Opcode) { 108 default: assert(0 && "Illegal integer setcc operation!"); 109 case ISD::SETEQ: 110 case ISD::SETNE: return 0; 111 case ISD::SETLT: 112 case ISD::SETLE: 113 case ISD::SETGT: 114 case ISD::SETGE: return 1; 115 case ISD::SETULT: 116 case ISD::SETULE: 117 case ISD::SETUGT: 118 case ISD::SETUGE: return 2; 119 } 120} 121 122/// getSetCCOrOperation - Return the result of a logical OR between different 123/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 124/// returns SETCC_INVALID if it is not possible to represent the resultant 125/// comparison. 126ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 127 bool isInteger) { 128 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 129 // Cannot fold a signed integer setcc with an unsigned integer setcc. 130 return ISD::SETCC_INVALID; 131 132 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 133 134 // If the N and U bits get set then the resultant comparison DOES suddenly 135 // care about orderedness, and is true when ordered. 136 if (Op > ISD::SETTRUE2) 137 Op &= ~16; // Clear the N bit. 138 return ISD::CondCode(Op); 139} 140 141/// getSetCCAndOperation - Return the result of a logical AND between different 142/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 143/// function returns zero if it is not possible to represent the resultant 144/// comparison. 145ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 146 bool isInteger) { 147 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 148 // Cannot fold a signed setcc with an unsigned setcc. 149 return ISD::SETCC_INVALID; 150 151 // Combine all of the condition bits. 152 return ISD::CondCode(Op1 & Op2); 153} 154 155const TargetMachine &SelectionDAG::getTarget() const { 156 return TLI.getTargetMachine(); 157} 158 159//===----------------------------------------------------------------------===// 160// SelectionDAG Class 161//===----------------------------------------------------------------------===// 162 163/// RemoveDeadNodes - This method deletes all unreachable nodes in the 164/// SelectionDAG, including nodes (like loads) that have uses of their token 165/// chain but no other uses and no side effect. If a node is passed in as an 166/// argument, it is used as the seed for node deletion. 167void SelectionDAG::RemoveDeadNodes(SDNode *N) { 168 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 169 170 // Create a dummy node (which is not added to allnodes), that adds a reference 171 // to the root node, preventing it from being deleted. 172 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 173 174 // If we have a hint to start from, use it. 175 if (N) DeleteNodeIfDead(N, &AllNodeSet); 176 177 Restart: 178 unsigned NumNodes = AllNodeSet.size(); 179 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 180 I != E; ++I) { 181 // Try to delete this node. 182 DeleteNodeIfDead(*I, &AllNodeSet); 183 184 // If we actually deleted any nodes, do not use invalid iterators in 185 // AllNodeSet. 186 if (AllNodeSet.size() != NumNodes) 187 goto Restart; 188 } 189 190 // Restore AllNodes. 191 if (AllNodes.size() != NumNodes) 192 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 193 194 // If the root changed (e.g. it was a dead load, update the root). 195 setRoot(DummyNode->getOperand(0)); 196 197 // Now that we are done with the dummy node, delete it. 198 DummyNode->getOperand(0).Val->removeUser(DummyNode); 199 delete DummyNode; 200} 201 202 203void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 204 if (!N->use_empty()) 205 return; 206 207 // Okay, we really are going to delete this node. First take this out of the 208 // appropriate CSE map. 209 RemoveNodeFromCSEMaps(N); 210 211 // Next, brutally remove the operand list. This is safe to do, as there are 212 // no cycles in the graph. 213 while (!N->Operands.empty()) { 214 SDNode *O = N->Operands.back().Val; 215 N->Operands.pop_back(); 216 O->removeUser(N); 217 218 // Now that we removed this operand, see if there are no uses of it left. 219 DeleteNodeIfDead(O, NodeSet); 220 } 221 222 // Remove the node from the nodes set and delete it. 223 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 224 AllNodeSet.erase(N); 225 226 // Now that the node is gone, check to see if any of the operands of this node 227 // are dead now. 228 delete N; 229} 230 231/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 232/// correspond to it. This is useful when we're about to delete or repurpose 233/// the node. We don't want future request for structurally identical nodes 234/// to return N anymore. 235void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 236 switch (N->getOpcode()) { 237 case ISD::Constant: 238 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 239 N->getValueType(0))); 240 break; 241 case ISD::TargetConstant: 242 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 243 N->getValueType(0))); 244 break; 245 case ISD::ConstantFP: { 246 uint64_t V = DoubleToBits(cast<ConstantFPSDNode>(N)->getValue()); 247 ConstantFPs.erase(std::make_pair(V, N->getValueType(0))); 248 break; 249 } 250 case ISD::CONDCODE: 251 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 252 "Cond code doesn't exist!"); 253 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 254 break; 255 case ISD::GlobalAddress: 256 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 257 break; 258 case ISD::TargetGlobalAddress: 259 TargetGlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 260 break; 261 case ISD::FrameIndex: 262 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 263 break; 264 case ISD::ConstantPool: 265 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 266 break; 267 case ISD::BasicBlock: 268 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 269 break; 270 case ISD::ExternalSymbol: 271 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 272 break; 273 case ISD::VALUETYPE: 274 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 275 break; 276 case ISD::Register: 277 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 278 break; 279 case ISD::SRCVALUE: { 280 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 281 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 282 break; 283 } 284 case ISD::LOAD: 285 Loads.erase(std::make_pair(N->getOperand(1), 286 std::make_pair(N->getOperand(0), 287 N->getValueType(0)))); 288 break; 289 default: 290 if (N->getNumOperands() == 1) 291 UnaryOps.erase(std::make_pair(N->getOpcode(), 292 std::make_pair(N->getOperand(0), 293 N->getValueType(0)))); 294 else if (N->getNumOperands() == 2) 295 BinaryOps.erase(std::make_pair(N->getOpcode(), 296 std::make_pair(N->getOperand(0), 297 N->getOperand(1)))); 298 else if (N->getNumValues() == 1) { 299 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 300 OneResultNodes.erase(std::make_pair(N->getOpcode(), 301 std::make_pair(N->getValueType(0), 302 Ops))); 303 } else { 304 // Remove the node from the ArbitraryNodes map. 305 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 306 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 307 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 308 std::make_pair(RV, Ops))); 309 } 310 break; 311 } 312} 313 314/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 315/// has been taken out and modified in some way. If the specified node already 316/// exists in the CSE maps, do not modify the maps, but return the existing node 317/// instead. If it doesn't exist, add it and return null. 318/// 319SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 320 assert(N->getNumOperands() && "This is a leaf node!"); 321 if (N->getOpcode() == ISD::LOAD) { 322 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 323 std::make_pair(N->getOperand(0), 324 N->getValueType(0)))]; 325 if (L) return L; 326 L = N; 327 } else if (N->getNumOperands() == 1) { 328 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 329 std::make_pair(N->getOperand(0), 330 N->getValueType(0)))]; 331 if (U) return U; 332 U = N; 333 } else if (N->getNumOperands() == 2) { 334 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 335 std::make_pair(N->getOperand(0), 336 N->getOperand(1)))]; 337 if (B) return B; 338 B = N; 339 } else if (N->getNumValues() == 1) { 340 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 341 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 342 std::make_pair(N->getValueType(0), Ops))]; 343 if (ORN) return ORN; 344 ORN = N; 345 } else { 346 // Remove the node from the ArbitraryNodes map. 347 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 348 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 349 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 350 std::make_pair(RV, Ops))]; 351 if (AN) return AN; 352 AN = N; 353 } 354 return 0; 355 356} 357 358 359 360SelectionDAG::~SelectionDAG() { 361 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 362 delete AllNodes[i]; 363} 364 365SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 366 if (Op.getValueType() == VT) return Op; 367 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 368 return getNode(ISD::AND, Op.getValueType(), Op, 369 getConstant(Imm, Op.getValueType())); 370} 371 372SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 373 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 374 // Mask out any bits that are not valid for this constant. 375 if (VT != MVT::i64) 376 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 377 378 SDNode *&N = Constants[std::make_pair(Val, VT)]; 379 if (N) return SDOperand(N, 0); 380 N = new ConstantSDNode(false, Val, VT); 381 AllNodes.push_back(N); 382 return SDOperand(N, 0); 383} 384 385SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 386 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 387 // Mask out any bits that are not valid for this constant. 388 if (VT != MVT::i64) 389 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 390 391 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 392 if (N) return SDOperand(N, 0); 393 N = new ConstantSDNode(true, Val, VT); 394 AllNodes.push_back(N); 395 return SDOperand(N, 0); 396} 397 398SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 399 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 400 if (VT == MVT::f32) 401 Val = (float)Val; // Mask out extra precision. 402 403 // Do the map lookup using the actual bit pattern for the floating point 404 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 405 // we don't have issues with SNANs. 406 SDNode *&N = ConstantFPs[std::make_pair(DoubleToBits(Val), VT)]; 407 if (N) return SDOperand(N, 0); 408 N = new ConstantFPSDNode(Val, VT); 409 AllNodes.push_back(N); 410 return SDOperand(N, 0); 411} 412 413 414 415SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 416 MVT::ValueType VT) { 417 SDNode *&N = GlobalValues[GV]; 418 if (N) return SDOperand(N, 0); 419 N = new GlobalAddressSDNode(false, GV, VT); 420 AllNodes.push_back(N); 421 return SDOperand(N, 0); 422} 423 424SDOperand SelectionDAG::getTargetGlobalAddress(const GlobalValue *GV, 425 MVT::ValueType VT) { 426 SDNode *&N = TargetGlobalValues[GV]; 427 if (N) return SDOperand(N, 0); 428 N = new GlobalAddressSDNode(true, GV, VT); 429 AllNodes.push_back(N); 430 return SDOperand(N, 0); 431} 432 433SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 434 SDNode *&N = FrameIndices[FI]; 435 if (N) return SDOperand(N, 0); 436 N = new FrameIndexSDNode(FI, VT); 437 AllNodes.push_back(N); 438 return SDOperand(N, 0); 439} 440 441SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 442 SDNode *N = ConstantPoolIndices[CPIdx]; 443 if (N) return SDOperand(N, 0); 444 N = new ConstantPoolSDNode(CPIdx, VT); 445 AllNodes.push_back(N); 446 return SDOperand(N, 0); 447} 448 449SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 450 SDNode *&N = BBNodes[MBB]; 451 if (N) return SDOperand(N, 0); 452 N = new BasicBlockSDNode(MBB); 453 AllNodes.push_back(N); 454 return SDOperand(N, 0); 455} 456 457SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 458 if ((unsigned)VT >= ValueTypeNodes.size()) 459 ValueTypeNodes.resize(VT+1); 460 if (ValueTypeNodes[VT] == 0) { 461 ValueTypeNodes[VT] = new VTSDNode(VT); 462 AllNodes.push_back(ValueTypeNodes[VT]); 463 } 464 465 return SDOperand(ValueTypeNodes[VT], 0); 466} 467 468SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 469 SDNode *&N = ExternalSymbols[Sym]; 470 if (N) return SDOperand(N, 0); 471 N = new ExternalSymbolSDNode(Sym, VT); 472 AllNodes.push_back(N); 473 return SDOperand(N, 0); 474} 475 476SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 477 if ((unsigned)Cond >= CondCodeNodes.size()) 478 CondCodeNodes.resize(Cond+1); 479 480 if (CondCodeNodes[Cond] == 0) { 481 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 482 AllNodes.push_back(CondCodeNodes[Cond]); 483 } 484 return SDOperand(CondCodeNodes[Cond], 0); 485} 486 487SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 488 if (Reg >= RegNodes.size()) 489 RegNodes.resize(Reg+1); 490 RegisterSDNode *&Result = RegNodes[Reg]; 491 if (Result) { 492 assert(Result->getValueType(0) == VT && 493 "Inconsistent value types for machine registers"); 494 } else { 495 Result = new RegisterSDNode(Reg, VT); 496 AllNodes.push_back(Result); 497 } 498 return SDOperand(Result, 0); 499} 500 501SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 502 SDOperand N2, ISD::CondCode Cond) { 503 // These setcc operations always fold. 504 switch (Cond) { 505 default: break; 506 case ISD::SETFALSE: 507 case ISD::SETFALSE2: return getConstant(0, VT); 508 case ISD::SETTRUE: 509 case ISD::SETTRUE2: return getConstant(1, VT); 510 } 511 512 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 513 uint64_t C2 = N2C->getValue(); 514 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 515 uint64_t C1 = N1C->getValue(); 516 517 // Sign extend the operands if required 518 if (ISD::isSignedIntSetCC(Cond)) { 519 C1 = N1C->getSignExtended(); 520 C2 = N2C->getSignExtended(); 521 } 522 523 switch (Cond) { 524 default: assert(0 && "Unknown integer setcc!"); 525 case ISD::SETEQ: return getConstant(C1 == C2, VT); 526 case ISD::SETNE: return getConstant(C1 != C2, VT); 527 case ISD::SETULT: return getConstant(C1 < C2, VT); 528 case ISD::SETUGT: return getConstant(C1 > C2, VT); 529 case ISD::SETULE: return getConstant(C1 <= C2, VT); 530 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 531 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 532 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 533 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 534 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 535 } 536 } else { 537 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 538 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 539 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 540 541 // If the comparison constant has bits in the upper part, the 542 // zero-extended value could never match. 543 if (C2 & (~0ULL << InSize)) { 544 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 545 switch (Cond) { 546 case ISD::SETUGT: 547 case ISD::SETUGE: 548 case ISD::SETEQ: return getConstant(0, VT); 549 case ISD::SETULT: 550 case ISD::SETULE: 551 case ISD::SETNE: return getConstant(1, VT); 552 case ISD::SETGT: 553 case ISD::SETGE: 554 // True if the sign bit of C2 is set. 555 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 556 case ISD::SETLT: 557 case ISD::SETLE: 558 // True if the sign bit of C2 isn't set. 559 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 560 default: 561 break; 562 } 563 } 564 565 // Otherwise, we can perform the comparison with the low bits. 566 switch (Cond) { 567 case ISD::SETEQ: 568 case ISD::SETNE: 569 case ISD::SETUGT: 570 case ISD::SETUGE: 571 case ISD::SETULT: 572 case ISD::SETULE: 573 return getSetCC(VT, N1.getOperand(0), 574 getConstant(C2, N1.getOperand(0).getValueType()), 575 Cond); 576 default: 577 break; // todo, be more careful with signed comparisons 578 } 579 } else if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG && 580 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 581 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N1.getOperand(1))->getVT(); 582 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 583 MVT::ValueType ExtDstTy = N1.getValueType(); 584 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 585 586 // If the extended part has any inconsistent bits, it cannot ever 587 // compare equal. In other words, they have to be all ones or all 588 // zeros. 589 uint64_t ExtBits = 590 (~0ULL >> 64-ExtSrcTyBits) & (~0ULL << (ExtDstTyBits-1)); 591 if ((C2 & ExtBits) != 0 && (C2 & ExtBits) != ExtBits) 592 return getConstant(Cond == ISD::SETNE, VT); 593 594 // Otherwise, make this a use of a zext. 595 return getSetCC(VT, getZeroExtendInReg(N1.getOperand(0), ExtSrcTy), 596 getConstant(C2 & (~0ULL >> 64-ExtSrcTyBits), ExtDstTy), 597 Cond); 598 } 599 600 uint64_t MinVal, MaxVal; 601 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 602 if (ISD::isSignedIntSetCC(Cond)) { 603 MinVal = 1ULL << (OperandBitSize-1); 604 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 605 MaxVal = ~0ULL >> (65-OperandBitSize); 606 else 607 MaxVal = 0; 608 } else { 609 MinVal = 0; 610 MaxVal = ~0ULL >> (64-OperandBitSize); 611 } 612 613 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 614 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 615 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 616 --C2; // X >= C1 --> X > (C1-1) 617 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 618 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 619 } 620 621 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 622 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 623 ++C2; // X <= C1 --> X < (C1+1) 624 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 625 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 626 } 627 628 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 629 return getConstant(0, VT); // X < MIN --> false 630 631 // Canonicalize setgt X, Min --> setne X, Min 632 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 633 return getSetCC(VT, N1, N2, ISD::SETNE); 634 635 // If we have setult X, 1, turn it into seteq X, 0 636 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 637 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 638 ISD::SETEQ); 639 // If we have setugt X, Max-1, turn it into seteq X, Max 640 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 641 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 642 ISD::SETEQ); 643 644 // If we have "setcc X, C1", check to see if we can shrink the immediate 645 // by changing cc. 646 647 // SETUGT X, SINTMAX -> SETLT X, 0 648 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 649 C2 == (~0ULL >> (65-OperandBitSize))) 650 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 651 652 // FIXME: Implement the rest of these. 653 654 655 // Fold bit comparisons when we can. 656 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 657 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 658 if (ConstantSDNode *AndRHS = 659 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 660 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 661 // Perform the xform if the AND RHS is a single bit. 662 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 663 return getNode(ISD::SRL, VT, N1, 664 getConstant(Log2_64(AndRHS->getValue()), 665 TLI.getShiftAmountTy())); 666 } 667 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 668 // (X & 8) == 8 --> (X & 8) >> 3 669 // Perform the xform if C2 is a single bit. 670 if ((C2 & (C2-1)) == 0) { 671 return getNode(ISD::SRL, VT, N1, 672 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 673 } 674 } 675 } 676 } 677 } else if (isa<ConstantSDNode>(N1.Val)) { 678 // Ensure that the constant occurs on the RHS. 679 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 680 } 681 682 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 683 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 684 double C1 = N1C->getValue(), C2 = N2C->getValue(); 685 686 switch (Cond) { 687 default: break; // FIXME: Implement the rest of these! 688 case ISD::SETEQ: return getConstant(C1 == C2, VT); 689 case ISD::SETNE: return getConstant(C1 != C2, VT); 690 case ISD::SETLT: return getConstant(C1 < C2, VT); 691 case ISD::SETGT: return getConstant(C1 > C2, VT); 692 case ISD::SETLE: return getConstant(C1 <= C2, VT); 693 case ISD::SETGE: return getConstant(C1 >= C2, VT); 694 } 695 } else { 696 // Ensure that the constant occurs on the RHS. 697 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 698 } 699 700 if (N1 == N2) { 701 // We can always fold X == Y for integer setcc's. 702 if (MVT::isInteger(N1.getValueType())) 703 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 704 unsigned UOF = ISD::getUnorderedFlavor(Cond); 705 if (UOF == 2) // FP operators that are undefined on NaNs. 706 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 707 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 708 return getConstant(UOF, VT); 709 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 710 // if it is not already. 711 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 712 if (NewCond != Cond) 713 return getSetCC(VT, N1, N2, NewCond); 714 } 715 716 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 717 MVT::isInteger(N1.getValueType())) { 718 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 719 N1.getOpcode() == ISD::XOR) { 720 // Simplify (X+Y) == (X+Z) --> Y == Z 721 if (N1.getOpcode() == N2.getOpcode()) { 722 if (N1.getOperand(0) == N2.getOperand(0)) 723 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 724 if (N1.getOperand(1) == N2.getOperand(1)) 725 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 726 if (isCommutativeBinOp(N1.getOpcode())) { 727 // If X op Y == Y op X, try other combinations. 728 if (N1.getOperand(0) == N2.getOperand(1)) 729 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 730 if (N1.getOperand(1) == N2.getOperand(0)) 731 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 732 } 733 } 734 735 // FIXME: move this stuff to the DAG Combiner when it exists! 736 737 // Simplify (X+Z) == X --> Z == 0 738 if (N1.getOperand(0) == N2) 739 return getSetCC(VT, N1.getOperand(1), 740 getConstant(0, N1.getValueType()), Cond); 741 if (N1.getOperand(1) == N2) { 742 if (isCommutativeBinOp(N1.getOpcode())) 743 return getSetCC(VT, N1.getOperand(0), 744 getConstant(0, N1.getValueType()), Cond); 745 else { 746 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 747 // (Z-X) == X --> Z == X<<1 748 return getSetCC(VT, N1.getOperand(0), 749 getNode(ISD::SHL, N2.getValueType(), 750 N2, getConstant(1, TLI.getShiftAmountTy())), 751 Cond); 752 } 753 } 754 } 755 756 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 757 N2.getOpcode() == ISD::XOR) { 758 // Simplify X == (X+Z) --> Z == 0 759 if (N2.getOperand(0) == N1) { 760 return getSetCC(VT, N2.getOperand(1), 761 getConstant(0, N2.getValueType()), Cond); 762 } else if (N2.getOperand(1) == N1) { 763 if (isCommutativeBinOp(N2.getOpcode())) { 764 return getSetCC(VT, N2.getOperand(0), 765 getConstant(0, N2.getValueType()), Cond); 766 } else { 767 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 768 // X == (Z-X) --> X<<1 == Z 769 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 770 getConstant(1, TLI.getShiftAmountTy())), 771 N2.getOperand(0), Cond); 772 } 773 } 774 } 775 } 776 777 // Fold away ALL boolean setcc's. 778 if (N1.getValueType() == MVT::i1) { 779 switch (Cond) { 780 default: assert(0 && "Unknown integer setcc!"); 781 case ISD::SETEQ: // X == Y -> (X^Y)^1 782 N1 = getNode(ISD::XOR, MVT::i1, 783 getNode(ISD::XOR, MVT::i1, N1, N2), 784 getConstant(1, MVT::i1)); 785 break; 786 case ISD::SETNE: // X != Y --> (X^Y) 787 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 788 break; 789 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 790 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 791 N1 = getNode(ISD::AND, MVT::i1, N2, 792 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 793 break; 794 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 795 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 796 N1 = getNode(ISD::AND, MVT::i1, N1, 797 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 798 break; 799 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 800 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 801 N1 = getNode(ISD::OR, MVT::i1, N2, 802 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 803 break; 804 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 805 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 806 N1 = getNode(ISD::OR, MVT::i1, N1, 807 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 808 break; 809 } 810 if (VT != MVT::i1) 811 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 812 return N1; 813 } 814 815 // Could not fold it. 816 return SDOperand(); 817} 818 819SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 820 SDOperand N3, SDOperand N4, 821 ISD::CondCode CC) { 822 MVT::ValueType VT = N3.getValueType(); 823 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 824 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 825 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 826 827 // Check to see if we can simplify the select into an fabs node 828 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 829 // Allow either -0.0 or 0.0 830 if (CFP->getValue() == 0.0) { 831 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 832 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 833 N1 == N3 && N4.getOpcode() == ISD::FNEG && 834 N1 == N4.getOperand(0)) 835 return getNode(ISD::FABS, VT, N1); 836 837 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 838 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 839 N1 == N4 && N3.getOpcode() == ISD::FNEG && 840 N3.getOperand(0) == N4) 841 return getNode(ISD::FABS, VT, N4); 842 } 843 } 844 845 // Check to see if we can perform the "gzip trick", transforming 846 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 847 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 848 MVT::isInteger(N1.getValueType()) && 849 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 850 MVT::ValueType XType = N1.getValueType(); 851 MVT::ValueType AType = N3.getValueType(); 852 if (XType >= AType) { 853 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 854 // single-bit constant. FIXME: remove once the dag combiner 855 // exists. 856 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 857 unsigned ShCtV = Log2_64(N3C->getValue()); 858 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 859 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 860 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 861 if (XType > AType) 862 Shift = getNode(ISD::TRUNCATE, AType, Shift); 863 return getNode(ISD::AND, AType, Shift, N3); 864 } 865 SDOperand Shift = getNode(ISD::SRA, XType, N1, 866 getConstant(MVT::getSizeInBits(XType)-1, 867 TLI.getShiftAmountTy())); 868 if (XType > AType) 869 Shift = getNode(ISD::TRUNCATE, AType, Shift); 870 return getNode(ISD::AND, AType, Shift, N3); 871 } 872 } 873 874 // Check to see if this is the equivalent of setcc X, 0 875 if (N4C && N4C->isNullValue() && N3C && (N3C->getValue() == 1ULL)) { 876 MVT::ValueType XType = N1.getValueType(); 877 if (TLI.getOperationAction(ISD::SETCC, TLI.getSetCCResultTy()) == 878 TargetLowering::Legal) { 879 return getSetCC(TLI.getSetCCResultTy(), N1, N2, CC); 880 } 881 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 882 if (N2C && N2C->isNullValue() && CC == ISD::SETEQ && 883 TLI.getOperationAction(ISD::CTLZ, XType) == TargetLowering::Legal) { 884 SDOperand Ctlz = getNode(ISD::CTLZ, XType, N1); 885 return getNode(ISD::SRL, XType, Ctlz, 886 getConstant(Log2_32(MVT::getSizeInBits(XType)), 887 TLI.getShiftAmountTy())); 888 } 889 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 890 if (N2C && N2C->isNullValue() && CC == ISD::SETGT) { 891 SDOperand NegN1 = getNode(ISD::SUB, XType, getConstant(0, XType), N1); 892 SDOperand NotN1 = getNode(ISD::XOR, XType, N1, getConstant(~0ULL, XType)); 893 return getNode(ISD::SRL, XType, getNode(ISD::AND, XType, NegN1, NotN1), 894 getConstant(MVT::getSizeInBits(XType)-1, 895 TLI.getShiftAmountTy())); 896 } 897 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 898 if (N2C && N2C->isAllOnesValue() && CC == ISD::SETGT) { 899 SDOperand Sign = getNode(ISD::SRL, XType, N1, 900 getConstant(MVT::getSizeInBits(XType)-1, 901 TLI.getShiftAmountTy())); 902 return getNode(ISD::XOR, XType, Sign, getConstant(1, XType)); 903 } 904 } 905 906 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 907 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 908 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 909 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 910 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 911 MVT::ValueType XType = N1.getValueType(); 912 if (SubC->isNullValue() && MVT::isInteger(XType)) { 913 SDOperand Shift = getNode(ISD::SRA, XType, N1, 914 getConstant(MVT::getSizeInBits(XType)-1, 915 TLI.getShiftAmountTy())); 916 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 917 Shift); 918 } 919 } 920 } 921 922 // Could not fold it. 923 return SDOperand(); 924} 925 926/// getNode - Gets or creates the specified node. 927/// 928SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 929 SDNode *N = new SDNode(Opcode, VT); 930 AllNodes.push_back(N); 931 return SDOperand(N, 0); 932} 933 934SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 935 SDOperand Operand) { 936 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 937 uint64_t Val = C->getValue(); 938 switch (Opcode) { 939 default: break; 940 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 941 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 942 case ISD::TRUNCATE: return getConstant(Val, VT); 943 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 944 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 945 } 946 } 947 948 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 949 switch (Opcode) { 950 case ISD::FNEG: 951 return getConstantFP(-C->getValue(), VT); 952 case ISD::FP_ROUND: 953 case ISD::FP_EXTEND: 954 return getConstantFP(C->getValue(), VT); 955 case ISD::FP_TO_SINT: 956 return getConstant((int64_t)C->getValue(), VT); 957 case ISD::FP_TO_UINT: 958 return getConstant((uint64_t)C->getValue(), VT); 959 } 960 961 unsigned OpOpcode = Operand.Val->getOpcode(); 962 switch (Opcode) { 963 case ISD::TokenFactor: 964 return Operand; // Factor of one node? No factor. 965 case ISD::SIGN_EXTEND: 966 if (Operand.getValueType() == VT) return Operand; // noop extension 967 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 968 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 969 break; 970 case ISD::ZERO_EXTEND: 971 if (Operand.getValueType() == VT) return Operand; // noop extension 972 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 973 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 974 break; 975 case ISD::TRUNCATE: 976 if (Operand.getValueType() == VT) return Operand; // noop truncate 977 if (OpOpcode == ISD::TRUNCATE) 978 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 979 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 980 // If the source is smaller than the dest, we still need an extend. 981 if (Operand.Val->getOperand(0).getValueType() < VT) 982 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 983 else if (Operand.Val->getOperand(0).getValueType() > VT) 984 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 985 else 986 return Operand.Val->getOperand(0); 987 } 988 break; 989 case ISD::FNEG: 990 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 991 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 992 Operand.Val->getOperand(0)); 993 if (OpOpcode == ISD::FNEG) // --X -> X 994 return Operand.Val->getOperand(0); 995 break; 996 case ISD::FABS: 997 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 998 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 999 break; 1000 } 1001 1002 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 1003 if (N) return SDOperand(N, 0); 1004 N = new SDNode(Opcode, Operand); 1005 N->setValueTypes(VT); 1006 AllNodes.push_back(N); 1007 return SDOperand(N, 0); 1008} 1009 1010/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 1011/// this predicate to simplify operations downstream. V and Mask are known to 1012/// be the same type. 1013static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 1014 const TargetLowering &TLI) { 1015 unsigned SrcBits; 1016 if (Mask == 0) return true; 1017 1018 // If we know the result of a setcc has the top bits zero, use this info. 1019 switch (Op.getOpcode()) { 1020 case ISD::Constant: 1021 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 1022 1023 case ISD::SETCC: 1024 return ((Mask & 1) == 0) && 1025 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 1026 1027 case ISD::ZEXTLOAD: 1028 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 1029 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 1030 case ISD::ZERO_EXTEND: 1031 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 1032 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 1033 1034 case ISD::AND: 1035 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 1036 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 1037 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 1038 1039 // FALL THROUGH 1040 case ISD::OR: 1041 case ISD::XOR: 1042 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 1043 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 1044 case ISD::SELECT: 1045 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 1046 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 1047 case ISD::SELECT_CC: 1048 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 1049 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 1050 case ISD::SRL: 1051 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 1052 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1053 uint64_t NewVal = Mask << ShAmt->getValue(); 1054 SrcBits = MVT::getSizeInBits(Op.getValueType()); 1055 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 1056 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1057 } 1058 return false; 1059 case ISD::SHL: 1060 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 1061 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 1062 uint64_t NewVal = Mask >> ShAmt->getValue(); 1063 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 1064 } 1065 return false; 1066 case ISD::CTTZ: 1067 case ISD::CTLZ: 1068 case ISD::CTPOP: 1069 // Bit counting instructions can not set the high bits of the result 1070 // register. The max number of bits sets depends on the input. 1071 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 1072 1073 // TODO we could handle some SRA cases here. 1074 default: break; 1075 } 1076 1077 return false; 1078} 1079 1080 1081 1082SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1083 SDOperand N1, SDOperand N2) { 1084#ifndef NDEBUG 1085 switch (Opcode) { 1086 case ISD::TokenFactor: 1087 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1088 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1089 break; 1090 case ISD::AND: 1091 case ISD::OR: 1092 case ISD::XOR: 1093 case ISD::UDIV: 1094 case ISD::UREM: 1095 case ISD::MULHU: 1096 case ISD::MULHS: 1097 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1098 // fall through 1099 case ISD::ADD: 1100 case ISD::SUB: 1101 case ISD::MUL: 1102 case ISD::SDIV: 1103 case ISD::SREM: 1104 assert(N1.getValueType() == N2.getValueType() && 1105 N1.getValueType() == VT && "Binary operator types must match!"); 1106 break; 1107 1108 case ISD::SHL: 1109 case ISD::SRA: 1110 case ISD::SRL: 1111 assert(VT == N1.getValueType() && 1112 "Shift operators return type must be the same as their first arg"); 1113 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1114 VT != MVT::i1 && "Shifts only work on integers"); 1115 break; 1116 case ISD::FP_ROUND_INREG: { 1117 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1118 assert(VT == N1.getValueType() && "Not an inreg round!"); 1119 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1120 "Cannot FP_ROUND_INREG integer types"); 1121 assert(EVT <= VT && "Not rounding down!"); 1122 break; 1123 } 1124 case ISD::SIGN_EXTEND_INREG: { 1125 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1126 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1127 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1128 "Cannot *_EXTEND_INREG FP types"); 1129 assert(EVT <= VT && "Not extending!"); 1130 } 1131 1132 default: break; 1133 } 1134#endif 1135 1136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1137 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1138 if (N1C) { 1139 if (N2C) { 1140 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1141 switch (Opcode) { 1142 case ISD::ADD: return getConstant(C1 + C2, VT); 1143 case ISD::SUB: return getConstant(C1 - C2, VT); 1144 case ISD::MUL: return getConstant(C1 * C2, VT); 1145 case ISD::UDIV: 1146 if (C2) return getConstant(C1 / C2, VT); 1147 break; 1148 case ISD::UREM : 1149 if (C2) return getConstant(C1 % C2, VT); 1150 break; 1151 case ISD::SDIV : 1152 if (C2) return getConstant(N1C->getSignExtended() / 1153 N2C->getSignExtended(), VT); 1154 break; 1155 case ISD::SREM : 1156 if (C2) return getConstant(N1C->getSignExtended() % 1157 N2C->getSignExtended(), VT); 1158 break; 1159 case ISD::AND : return getConstant(C1 & C2, VT); 1160 case ISD::OR : return getConstant(C1 | C2, VT); 1161 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1162 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1163 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1164 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1165 default: break; 1166 } 1167 1168 } else { // Cannonicalize constant to RHS if commutative 1169 if (isCommutativeBinOp(Opcode)) { 1170 std::swap(N1C, N2C); 1171 std::swap(N1, N2); 1172 } 1173 } 1174 1175 switch (Opcode) { 1176 default: break; 1177 case ISD::SHL: // shl 0, X -> 0 1178 if (N1C->isNullValue()) return N1; 1179 break; 1180 case ISD::SRL: // srl 0, X -> 0 1181 if (N1C->isNullValue()) return N1; 1182 break; 1183 case ISD::SRA: // sra -1, X -> -1 1184 if (N1C->isAllOnesValue()) return N1; 1185 break; 1186 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1187 // Extending a constant? Just return the extended constant. 1188 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1189 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1190 } 1191 } 1192 1193 if (N2C) { 1194 uint64_t C2 = N2C->getValue(); 1195 1196 switch (Opcode) { 1197 case ISD::ADD: 1198 if (!C2) return N1; // add X, 0 -> X 1199 break; 1200 case ISD::SUB: 1201 if (!C2) return N1; // sub X, 0 -> X 1202 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1203 case ISD::MUL: 1204 if (!C2) return N2; // mul X, 0 -> 0 1205 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1206 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1207 1208 // FIXME: Move this to the DAG combiner when it exists. 1209 if ((C2 & C2-1) == 0) { 1210 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1211 return getNode(ISD::SHL, VT, N1, ShAmt); 1212 } 1213 break; 1214 1215 case ISD::MULHU: 1216 case ISD::MULHS: 1217 if (!C2) return N2; // mul X, 0 -> 0 1218 1219 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1220 return getConstant(0, VT); 1221 1222 // Many others could be handled here, including -1, powers of 2, etc. 1223 break; 1224 1225 case ISD::UDIV: 1226 // FIXME: Move this to the DAG combiner when it exists. 1227 if ((C2 & C2-1) == 0 && C2) { 1228 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1229 return getNode(ISD::SRL, VT, N1, ShAmt); 1230 } 1231 break; 1232 1233 case ISD::SHL: 1234 case ISD::SRL: 1235 case ISD::SRA: 1236 // If the shift amount is bigger than the size of the data, then all the 1237 // bits are shifted out. Simplify to undef. 1238 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1239 return getNode(ISD::UNDEF, N1.getValueType()); 1240 } 1241 if (C2 == 0) return N1; 1242 1243 if (Opcode == ISD::SRA) { 1244 // If the sign bit is known to be zero, switch this to a SRL. 1245 if (MaskedValueIsZero(N1, 1246 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), 1247 TLI)) 1248 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1249 } else { 1250 // If the part left over is known to be zero, the whole thing is zero. 1251 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1252 if (Opcode == ISD::SRL) { 1253 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1254 return getConstant(0, N1.getValueType()); 1255 } else if (Opcode == ISD::SHL) { 1256 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1257 return getConstant(0, N1.getValueType()); 1258 } 1259 } 1260 1261 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1262 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1263 unsigned OpSAC = OpSA->getValue(); 1264 if (N1.getOpcode() == ISD::SHL) { 1265 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1266 return getConstant(0, N1.getValueType()); 1267 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1268 getConstant(C2+OpSAC, N2.getValueType())); 1269 } else if (N1.getOpcode() == ISD::SRL) { 1270 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1271 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1272 getConstant(~0ULL << OpSAC, VT)); 1273 if (C2 > OpSAC) { 1274 return getNode(ISD::SHL, VT, Mask, 1275 getConstant(C2-OpSAC, N2.getValueType())); 1276 } else { 1277 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1278 return getNode(ISD::SRL, VT, Mask, 1279 getConstant(OpSAC-C2, N2.getValueType())); 1280 } 1281 } else if (N1.getOpcode() == ISD::SRA) { 1282 // if C1 == C2, just mask out low bits. 1283 if (C2 == OpSAC) 1284 return getNode(ISD::AND, VT, N1.getOperand(0), 1285 getConstant(~0ULL << C2, VT)); 1286 } 1287 } 1288 break; 1289 1290 case ISD::AND: 1291 if (!C2) return N2; // X and 0 -> 0 1292 if (N2C->isAllOnesValue()) 1293 return N1; // X and -1 -> X 1294 1295 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1296 return getConstant(0, VT); 1297 1298 { 1299 uint64_t NotC2 = ~C2; 1300 if (VT != MVT::i64) 1301 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1302 1303 if (MaskedValueIsZero(N1, NotC2, TLI)) 1304 return N1; // if (X & ~C2) -> 0, the and is redundant 1305 } 1306 1307 // FIXME: Should add a corresponding version of this for 1308 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1309 // we don't have yet. 1310 1311 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1312 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1313 // If we are masking out the part of our input that was extended, just 1314 // mask the input to the extension directly. 1315 unsigned ExtendBits = 1316 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1317 if ((C2 & (~0ULL << ExtendBits)) == 0) 1318 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1319 } else if (N1.getOpcode() == ISD::OR) { 1320 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1321 if ((ORI->getValue() & C2) == C2) { 1322 // If the 'or' is setting all of the bits that we are masking for, 1323 // we know the result of the AND will be the AND mask itself. 1324 return N2; 1325 } 1326 } 1327 break; 1328 case ISD::OR: 1329 if (!C2)return N1; // X or 0 -> X 1330 if (N2C->isAllOnesValue()) 1331 return N2; // X or -1 -> -1 1332 break; 1333 case ISD::XOR: 1334 if (!C2) return N1; // X xor 0 -> X 1335 if (N2C->isAllOnesValue()) { 1336 if (N1.Val->getOpcode() == ISD::SETCC){ 1337 SDNode *SetCC = N1.Val; 1338 // !(X op Y) -> (X !op Y) 1339 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1340 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1341 return getSetCC(SetCC->getValueType(0), 1342 SetCC->getOperand(0), SetCC->getOperand(1), 1343 ISD::getSetCCInverse(CC, isInteger)); 1344 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1345 SDNode *Op = N1.Val; 1346 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1347 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1348 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1349 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1350 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1351 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1352 if (Op->getOpcode() == ISD::AND) 1353 return getNode(ISD::OR, VT, LHS, RHS); 1354 return getNode(ISD::AND, VT, LHS, RHS); 1355 } 1356 } 1357 // X xor -1 -> not(x) ? 1358 } 1359 break; 1360 } 1361 1362 // Reassociate ((X op C1) op C2) if possible. 1363 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1364 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1365 return getNode(Opcode, VT, N1.Val->getOperand(0), 1366 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1367 } 1368 1369 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1370 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1371 if (N1CFP) { 1372 if (N2CFP) { 1373 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1374 switch (Opcode) { 1375 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1376 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1377 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1378 case ISD::SDIV: 1379 if (C2) return getConstantFP(C1 / C2, VT); 1380 break; 1381 case ISD::SREM : 1382 if (C2) return getConstantFP(fmod(C1, C2), VT); 1383 break; 1384 default: break; 1385 } 1386 1387 } else { // Cannonicalize constant to RHS if commutative 1388 if (isCommutativeBinOp(Opcode)) { 1389 std::swap(N1CFP, N2CFP); 1390 std::swap(N1, N2); 1391 } 1392 } 1393 1394 if (Opcode == ISD::FP_ROUND_INREG) 1395 return getNode(ISD::FP_EXTEND, VT, 1396 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1397 } 1398 1399 // Finally, fold operations that do not require constants. 1400 switch (Opcode) { 1401 case ISD::TokenFactor: 1402 if (N1.getOpcode() == ISD::EntryToken) 1403 return N2; 1404 if (N2.getOpcode() == ISD::EntryToken) 1405 return N1; 1406 break; 1407 1408 case ISD::AND: 1409 case ISD::OR: 1410 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1411 SDNode *LHS = N1.Val, *RHS = N2.Val; 1412 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1413 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1414 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1415 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1416 1417 if (LR == RR && isa<ConstantSDNode>(LR) && 1418 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1419 // (X != 0) | (Y != 0) -> (X|Y != 0) 1420 // (X == 0) & (Y == 0) -> (X|Y == 0) 1421 // (X < 0) | (Y < 0) -> (X|Y < 0) 1422 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1423 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1424 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1425 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1426 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1427 Op2); 1428 1429 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1430 // (X == -1) & (Y == -1) -> (X&Y == -1) 1431 // (X != -1) | (Y != -1) -> (X&Y != -1) 1432 // (X > -1) | (Y > -1) -> (X&Y > -1) 1433 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1434 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1435 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1436 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1437 LR, Op2); 1438 // (X > -1) & (Y > -1) -> (X|Y > -1) 1439 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1440 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1441 LR, Op2); 1442 } 1443 } 1444 1445 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1446 if (LL == RR && LR == RL) { 1447 Op2 = ISD::getSetCCSwappedOperands(Op2); 1448 goto MatchedBackwards; 1449 } 1450 1451 if (LL == RL && LR == RR) { 1452 MatchedBackwards: 1453 ISD::CondCode Result; 1454 bool isInteger = MVT::isInteger(LL.getValueType()); 1455 if (Opcode == ISD::OR) 1456 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1457 else 1458 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1459 1460 if (Result != ISD::SETCC_INVALID) 1461 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1462 } 1463 } 1464 1465 // and/or zext(a), zext(b) -> zext(and/or a, b) 1466 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1467 N2.getOpcode() == ISD::ZERO_EXTEND && 1468 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1469 return getNode(ISD::ZERO_EXTEND, VT, 1470 getNode(Opcode, N1.getOperand(0).getValueType(), 1471 N1.getOperand(0), N2.getOperand(0))); 1472 break; 1473 case ISD::XOR: 1474 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1475 break; 1476 case ISD::ADD: 1477 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1478 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1479 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1480 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1481 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1482 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1483 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1484 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1485 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1486 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1487 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1488 !MVT::isFloatingPoint(N2.getValueType())) 1489 return N2.Val->getOperand(0); // A+(B-A) -> B 1490 break; 1491 case ISD::SUB: 1492 if (N1.getOpcode() == ISD::ADD) { 1493 if (N1.Val->getOperand(0) == N2 && 1494 !MVT::isFloatingPoint(N2.getValueType())) 1495 return N1.Val->getOperand(1); // (A+B)-A == B 1496 if (N1.Val->getOperand(1) == N2 && 1497 !MVT::isFloatingPoint(N2.getValueType())) 1498 return N1.Val->getOperand(0); // (A+B)-B == A 1499 } 1500 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1501 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1502 break; 1503 case ISD::FP_ROUND_INREG: 1504 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1505 break; 1506 case ISD::SIGN_EXTEND_INREG: { 1507 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1508 if (EVT == VT) return N1; // Not actually extending 1509 1510 // If we are sign extending an extension, use the original source. 1511 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1512 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1513 return N1; 1514 1515 // If we are sign extending a sextload, return just the load. 1516 if (N1.getOpcode() == ISD::SEXTLOAD) 1517 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1518 return N1; 1519 1520 // If we are extending the result of a setcc, and we already know the 1521 // contents of the top bits, eliminate the extension. 1522 if (N1.getOpcode() == ISD::SETCC && 1523 TLI.getSetCCResultContents() == 1524 TargetLowering::ZeroOrNegativeOneSetCCResult) 1525 return N1; 1526 1527 // If we are sign extending the result of an (and X, C) operation, and we 1528 // know the extended bits are zeros already, don't do the extend. 1529 if (N1.getOpcode() == ISD::AND) 1530 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1531 uint64_t Mask = N1C->getValue(); 1532 unsigned NumBits = MVT::getSizeInBits(EVT); 1533 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1534 return N1; 1535 } 1536 break; 1537 } 1538 1539 // FIXME: figure out how to safely handle things like 1540 // int foo(int x) { return 1 << (x & 255); } 1541 // int bar() { return foo(256); } 1542#if 0 1543 case ISD::SHL: 1544 case ISD::SRL: 1545 case ISD::SRA: 1546 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1547 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1548 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1549 else if (N2.getOpcode() == ISD::AND) 1550 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1551 // If the and is only masking out bits that cannot effect the shift, 1552 // eliminate the and. 1553 unsigned NumBits = MVT::getSizeInBits(VT); 1554 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1555 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1556 } 1557 break; 1558#endif 1559 } 1560 1561 // Memoize this node if possible. 1562 SDNode *N; 1563 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1564 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1565 if (BON) return SDOperand(BON, 0); 1566 1567 BON = N = new SDNode(Opcode, N1, N2); 1568 } else { 1569 N = new SDNode(Opcode, N1, N2); 1570 } 1571 1572 N->setValueTypes(VT); 1573 AllNodes.push_back(N); 1574 return SDOperand(N, 0); 1575} 1576 1577// setAdjCallChain - This method changes the token chain of an 1578// CALLSEQ_START/END node to be the specified operand. 1579void SDNode::setAdjCallChain(SDOperand N) { 1580 assert(N.getValueType() == MVT::Other); 1581 assert((getOpcode() == ISD::CALLSEQ_START || 1582 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1583 1584 Operands[0].Val->removeUser(this); 1585 Operands[0] = N; 1586 N.Val->Uses.push_back(this); 1587} 1588 1589 1590 1591SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1592 SDOperand Chain, SDOperand Ptr, 1593 SDOperand SV) { 1594 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1595 if (N) return SDOperand(N, 0); 1596 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1597 1598 // Loads have a token chain. 1599 N->setValueTypes(VT, MVT::Other); 1600 AllNodes.push_back(N); 1601 return SDOperand(N, 0); 1602} 1603 1604 1605SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1606 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1607 MVT::ValueType EVT) { 1608 std::vector<SDOperand> Ops; 1609 Ops.reserve(4); 1610 Ops.push_back(Chain); 1611 Ops.push_back(Ptr); 1612 Ops.push_back(SV); 1613 Ops.push_back(getValueType(EVT)); 1614 std::vector<MVT::ValueType> VTs; 1615 VTs.reserve(2); 1616 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1617 return getNode(Opcode, VTs, Ops); 1618} 1619 1620SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1621 SDOperand N1, SDOperand N2, SDOperand N3) { 1622 // Perform various simplifications. 1623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1624 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1625 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1626 switch (Opcode) { 1627 case ISD::SETCC: { 1628 // Use SimplifySetCC to simplify SETCC's. 1629 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1630 if (Simp.Val) return Simp; 1631 break; 1632 } 1633 case ISD::SELECT: 1634 if (N1C) 1635 if (N1C->getValue()) 1636 return N2; // select true, X, Y -> X 1637 else 1638 return N3; // select false, X, Y -> Y 1639 1640 if (N2 == N3) return N2; // select C, X, X -> X 1641 1642 if (VT == MVT::i1) { // Boolean SELECT 1643 if (N2C) { 1644 if (N2C->getValue()) // select C, 1, X -> C | X 1645 return getNode(ISD::OR, VT, N1, N3); 1646 else // select C, 0, X -> ~C & X 1647 return getNode(ISD::AND, VT, 1648 getNode(ISD::XOR, N1.getValueType(), N1, 1649 getConstant(1, N1.getValueType())), N3); 1650 } else if (N3C) { 1651 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1652 return getNode(ISD::OR, VT, 1653 getNode(ISD::XOR, N1.getValueType(), N1, 1654 getConstant(1, N1.getValueType())), N2); 1655 else // select C, X, 0 -> C & X 1656 return getNode(ISD::AND, VT, N1, N2); 1657 } 1658 1659 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1660 return getNode(ISD::OR, VT, N1, N3); 1661 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1662 return getNode(ISD::AND, VT, N1, N2); 1663 } 1664 if (N1.getOpcode() == ISD::SETCC) { 1665 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1666 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1667 if (Simp.Val) return Simp; 1668 } 1669 break; 1670 case ISD::BRCOND: 1671 if (N2C) 1672 if (N2C->getValue()) // Unconditional branch 1673 return getNode(ISD::BR, MVT::Other, N1, N3); 1674 else 1675 return N1; // Never-taken branch 1676 break; 1677 } 1678 1679 std::vector<SDOperand> Ops; 1680 Ops.reserve(3); 1681 Ops.push_back(N1); 1682 Ops.push_back(N2); 1683 Ops.push_back(N3); 1684 1685 // Memoize nodes. 1686 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1687 if (N) return SDOperand(N, 0); 1688 1689 N = new SDNode(Opcode, N1, N2, N3); 1690 N->setValueTypes(VT); 1691 AllNodes.push_back(N); 1692 return SDOperand(N, 0); 1693} 1694 1695SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1696 SDOperand N1, SDOperand N2, SDOperand N3, 1697 SDOperand N4) { 1698 std::vector<SDOperand> Ops; 1699 Ops.reserve(4); 1700 Ops.push_back(N1); 1701 Ops.push_back(N2); 1702 Ops.push_back(N3); 1703 Ops.push_back(N4); 1704 return getNode(Opcode, VT, Ops); 1705} 1706 1707SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1708 SDOperand N1, SDOperand N2, SDOperand N3, 1709 SDOperand N4, SDOperand N5) { 1710 std::vector<SDOperand> Ops; 1711 Ops.reserve(5); 1712 Ops.push_back(N1); 1713 Ops.push_back(N2); 1714 Ops.push_back(N3); 1715 Ops.push_back(N4); 1716 Ops.push_back(N5); 1717 return getNode(Opcode, VT, Ops); 1718} 1719 1720 1721SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1722 assert((!V || isa<PointerType>(V->getType())) && 1723 "SrcValue is not a pointer?"); 1724 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1725 if (N) return SDOperand(N, 0); 1726 1727 N = new SrcValueSDNode(V, Offset); 1728 AllNodes.push_back(N); 1729 return SDOperand(N, 0); 1730} 1731 1732SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1733 std::vector<SDOperand> &Ops) { 1734 switch (Ops.size()) { 1735 case 0: return getNode(Opcode, VT); 1736 case 1: return getNode(Opcode, VT, Ops[0]); 1737 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1738 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1739 default: break; 1740 } 1741 1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1743 switch (Opcode) { 1744 default: break; 1745 case ISD::BRCONDTWOWAY: 1746 if (N1C) 1747 if (N1C->getValue()) // Unconditional branch to true dest. 1748 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1749 else // Unconditional branch to false dest. 1750 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1751 break; 1752 case ISD::BRTWOWAY_CC: 1753 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1754 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1755 "LHS and RHS of comparison must have same type!"); 1756 break; 1757 case ISD::TRUNCSTORE: { 1758 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1759 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1760#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1761 // If this is a truncating store of a constant, convert to the desired type 1762 // and store it instead. 1763 if (isa<Constant>(Ops[0])) { 1764 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1765 if (isa<Constant>(Op)) 1766 N1 = Op; 1767 } 1768 // Also for ConstantFP? 1769#endif 1770 if (Ops[0].getValueType() == EVT) // Normal store? 1771 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1772 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1773 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1774 "Can't do FP-INT conversion!"); 1775 break; 1776 } 1777 case ISD::SELECT_CC: { 1778 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1779 assert(Ops[0].getValueType() == Ops[1].getValueType() && 1780 "LHS and RHS of condition must have same type!"); 1781 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1782 "True and False arms of SelectCC must have same type!"); 1783 assert(Ops[2].getValueType() == VT && 1784 "select_cc node must be of same type as true and false value!"); 1785 SDOperand Simp = SimplifySelectCC(Ops[0], Ops[1], Ops[2], Ops[3], 1786 cast<CondCodeSDNode>(Ops[4])->get()); 1787 if (Simp.Val) return Simp; 1788 break; 1789 } 1790 case ISD::BR_CC: { 1791 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1792 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1793 "LHS/RHS of comparison should match types!"); 1794 // Use SimplifySetCC to simplify SETCC's. 1795 SDOperand Simp = SimplifySetCC(MVT::i1, Ops[2], Ops[3], 1796 cast<CondCodeSDNode>(Ops[1])->get()); 1797 if (Simp.Val) { 1798 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Simp)) { 1799 if (C->getValue() & 1) // Unconditional branch 1800 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[4]); 1801 else 1802 return Ops[0]; // Unconditional Fall through 1803 } else if (Simp.Val->getOpcode() == ISD::SETCC) { 1804 Ops[2] = Simp.getOperand(0); 1805 Ops[3] = Simp.getOperand(1); 1806 Ops[1] = Simp.getOperand(2); 1807 } 1808 } 1809 break; 1810 } 1811 } 1812 1813 // Memoize nodes. 1814 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1815 if (N) return SDOperand(N, 0); 1816 N = new SDNode(Opcode, Ops); 1817 N->setValueTypes(VT); 1818 AllNodes.push_back(N); 1819 return SDOperand(N, 0); 1820} 1821 1822SDOperand SelectionDAG::getNode(unsigned Opcode, 1823 std::vector<MVT::ValueType> &ResultTys, 1824 std::vector<SDOperand> &Ops) { 1825 if (ResultTys.size() == 1) 1826 return getNode(Opcode, ResultTys[0], Ops); 1827 1828 switch (Opcode) { 1829 case ISD::EXTLOAD: 1830 case ISD::SEXTLOAD: 1831 case ISD::ZEXTLOAD: { 1832 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1833 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1834 // If they are asking for an extending load from/to the same thing, return a 1835 // normal load. 1836 if (ResultTys[0] == EVT) 1837 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1838 assert(EVT < ResultTys[0] && 1839 "Should only be an extending load, not truncating!"); 1840 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1841 "Cannot sign/zero extend a FP load!"); 1842 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1843 "Cannot convert from FP to Int or Int -> FP!"); 1844 break; 1845 } 1846 1847 // FIXME: figure out how to safely handle things like 1848 // int foo(int x) { return 1 << (x & 255); } 1849 // int bar() { return foo(256); } 1850#if 0 1851 case ISD::SRA_PARTS: 1852 case ISD::SRL_PARTS: 1853 case ISD::SHL_PARTS: 1854 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1855 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1856 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1857 else if (N3.getOpcode() == ISD::AND) 1858 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1859 // If the and is only masking out bits that cannot effect the shift, 1860 // eliminate the and. 1861 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1862 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1863 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1864 } 1865 break; 1866#endif 1867 } 1868 1869 // Memoize the node. 1870 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1871 Ops))]; 1872 if (N) return SDOperand(N, 0); 1873 N = new SDNode(Opcode, Ops); 1874 N->setValueTypes(ResultTys); 1875 AllNodes.push_back(N); 1876 return SDOperand(N, 0); 1877} 1878 1879 1880/// SelectNodeTo - These are used for target selectors to *mutate* the 1881/// specified node to have the specified return type, Target opcode, and 1882/// operands. Note that target opcodes are stored as 1883/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1884void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1885 unsigned TargetOpc, SDOperand Op1) { 1886 RemoveNodeFromCSEMaps(N); 1887 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1888 N->setValueTypes(VT); 1889 N->setOperands(Op1); 1890} 1891void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1892 unsigned TargetOpc, SDOperand Op1, 1893 SDOperand Op2) { 1894 RemoveNodeFromCSEMaps(N); 1895 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1896 N->setValueTypes(VT); 1897 N->setOperands(Op1, Op2); 1898} 1899void SelectionDAG::SelectNodeTo(SDNode *N, 1900 MVT::ValueType VT1, MVT::ValueType VT2, 1901 unsigned TargetOpc, SDOperand Op1, 1902 SDOperand Op2) { 1903 RemoveNodeFromCSEMaps(N); 1904 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1905 N->setValueTypes(VT1, VT2); 1906 N->setOperands(Op1, Op2); 1907} 1908void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1909 unsigned TargetOpc, SDOperand Op1, 1910 SDOperand Op2, SDOperand Op3) { 1911 RemoveNodeFromCSEMaps(N); 1912 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1913 N->setValueTypes(VT); 1914 N->setOperands(Op1, Op2, Op3); 1915} 1916void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT1, 1917 MVT::ValueType VT2, 1918 unsigned TargetOpc, SDOperand Op1, 1919 SDOperand Op2, SDOperand Op3) { 1920 RemoveNodeFromCSEMaps(N); 1921 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1922 N->setValueTypes(VT1, VT2); 1923 N->setOperands(Op1, Op2, Op3); 1924} 1925 1926void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1927 unsigned TargetOpc, SDOperand Op1, 1928 SDOperand Op2, SDOperand Op3, SDOperand Op4) { 1929 RemoveNodeFromCSEMaps(N); 1930 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1931 N->setValueTypes(VT); 1932 N->setOperands(Op1, Op2, Op3, Op4); 1933} 1934void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1935 unsigned TargetOpc, SDOperand Op1, 1936 SDOperand Op2, SDOperand Op3, SDOperand Op4, 1937 SDOperand Op5) { 1938 RemoveNodeFromCSEMaps(N); 1939 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1940 N->setValueTypes(VT); 1941 N->setOperands(Op1, Op2, Op3, Op4, Op5); 1942} 1943 1944/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 1945/// This can cause recursive merging of nodes in the DAG. 1946/// 1947void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 1948 assert(From != To && "Cannot replace uses of with self"); 1949 while (!From->use_empty()) { 1950 // Process users until they are all gone. 1951 SDNode *U = *From->use_begin(); 1952 1953 // This node is about to morph, remove its old self from the CSE maps. 1954 RemoveNodeFromCSEMaps(U); 1955 1956 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 1957 if (U->getOperand(i).Val == From) { 1958 assert(U->getOperand(i).getValueType() == 1959 To->getValueType(U->getOperand(i).ResNo)); 1960 From->removeUser(U); 1961 U->Operands[i].Val = To; 1962 To->addUser(U); 1963 } 1964 1965 // Now that we have modified U, add it back to the CSE maps. If it already 1966 // exists there, recursively merge the results together. 1967 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 1968 ReplaceAllUsesWith(U, Existing); 1969 // U is now dead. 1970 } 1971} 1972 1973void SelectionDAG::ReplaceAllUsesWith(SDNode *From, 1974 const std::vector<SDOperand> &To) { 1975 assert(From->getNumValues() == To.size() && 1976 "Incorrect number of values to replace with!"); 1977 if (To.size() == 1 && To[0].ResNo == 0) { 1978 // Degenerate case handled above. 1979 ReplaceAllUsesWith(From, To[0].Val); 1980 return; 1981 } 1982 1983 while (!From->use_empty()) { 1984 // Process users until they are all gone. 1985 SDNode *U = *From->use_begin(); 1986 1987 // This node is about to morph, remove its old self from the CSE maps. 1988 RemoveNodeFromCSEMaps(U); 1989 1990 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 1991 if (U->getOperand(i).Val == From) { 1992 const SDOperand &ToOp = To[U->getOperand(i).ResNo]; 1993 assert(U->getOperand(i).getValueType() == ToOp.getValueType()); 1994 From->removeUser(U); 1995 U->Operands[i] = ToOp; 1996 ToOp.Val->addUser(U); 1997 } 1998 1999 // Now that we have modified U, add it back to the CSE maps. If it already 2000 // exists there, recursively merge the results together. 2001 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 2002 ReplaceAllUsesWith(U, Existing); 2003 // U is now dead. 2004 } 2005} 2006 2007 2008//===----------------------------------------------------------------------===// 2009// SDNode Class 2010//===----------------------------------------------------------------------===// 2011 2012/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 2013/// indicated value. This method ignores uses of other values defined by this 2014/// operation. 2015bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 2016 assert(Value < getNumValues() && "Bad value!"); 2017 2018 // If there is only one value, this is easy. 2019 if (getNumValues() == 1) 2020 return use_size() == NUses; 2021 if (Uses.size() < NUses) return false; 2022 2023 SDOperand TheValue(this, Value); 2024 2025 std::set<SDNode*> UsersHandled; 2026 2027 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 2028 UI != E; ++UI) { 2029 SDNode *User = *UI; 2030 if (User->getNumOperands() == 1 || 2031 UsersHandled.insert(User).second) // First time we've seen this? 2032 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2033 if (User->getOperand(i) == TheValue) { 2034 if (NUses == 0) 2035 return false; // too many uses 2036 --NUses; 2037 } 2038 } 2039 2040 // Found exactly the right number of uses? 2041 return NUses == 0; 2042} 2043 2044 2045const char *SDNode::getOperationName(const SelectionDAG *G) const { 2046 switch (getOpcode()) { 2047 default: 2048 if (getOpcode() < ISD::BUILTIN_OP_END) 2049 return "<<Unknown DAG Node>>"; 2050 else { 2051 if (G) 2052 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 2053 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 2054 return "<<Unknown Target Node>>"; 2055 } 2056 2057 case ISD::PCMARKER: return "PCMarker"; 2058 case ISD::SRCVALUE: return "SrcValue"; 2059 case ISD::VALUETYPE: return "ValueType"; 2060 case ISD::EntryToken: return "EntryToken"; 2061 case ISD::TokenFactor: return "TokenFactor"; 2062 case ISD::Constant: return "Constant"; 2063 case ISD::TargetConstant: return "TargetConstant"; 2064 case ISD::ConstantFP: return "ConstantFP"; 2065 case ISD::GlobalAddress: return "GlobalAddress"; 2066 case ISD::TargetGlobalAddress: return "TargetGlobalAddress"; 2067 case ISD::FrameIndex: return "FrameIndex"; 2068 case ISD::BasicBlock: return "BasicBlock"; 2069 case ISD::Register: return "Register"; 2070 case ISD::ExternalSymbol: return "ExternalSymbol"; 2071 case ISD::ConstantPool: return "ConstantPoolIndex"; 2072 case ISD::CopyToReg: return "CopyToReg"; 2073 case ISD::CopyFromReg: return "CopyFromReg"; 2074 case ISD::ImplicitDef: return "ImplicitDef"; 2075 case ISD::UNDEF: return "undef"; 2076 2077 // Unary operators 2078 case ISD::FABS: return "fabs"; 2079 case ISD::FNEG: return "fneg"; 2080 case ISD::FSQRT: return "fsqrt"; 2081 case ISD::FSIN: return "fsin"; 2082 case ISD::FCOS: return "fcos"; 2083 2084 // Binary operators 2085 case ISD::ADD: return "add"; 2086 case ISD::SUB: return "sub"; 2087 case ISD::MUL: return "mul"; 2088 case ISD::MULHU: return "mulhu"; 2089 case ISD::MULHS: return "mulhs"; 2090 case ISD::SDIV: return "sdiv"; 2091 case ISD::UDIV: return "udiv"; 2092 case ISD::SREM: return "srem"; 2093 case ISD::UREM: return "urem"; 2094 case ISD::AND: return "and"; 2095 case ISD::OR: return "or"; 2096 case ISD::XOR: return "xor"; 2097 case ISD::SHL: return "shl"; 2098 case ISD::SRA: return "sra"; 2099 case ISD::SRL: return "srl"; 2100 2101 case ISD::SETCC: return "setcc"; 2102 case ISD::SELECT: return "select"; 2103 case ISD::SELECT_CC: return "select_cc"; 2104 case ISD::ADD_PARTS: return "add_parts"; 2105 case ISD::SUB_PARTS: return "sub_parts"; 2106 case ISD::SHL_PARTS: return "shl_parts"; 2107 case ISD::SRA_PARTS: return "sra_parts"; 2108 case ISD::SRL_PARTS: return "srl_parts"; 2109 2110 // Conversion operators. 2111 case ISD::SIGN_EXTEND: return "sign_extend"; 2112 case ISD::ZERO_EXTEND: return "zero_extend"; 2113 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 2114 case ISD::TRUNCATE: return "truncate"; 2115 case ISD::FP_ROUND: return "fp_round"; 2116 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 2117 case ISD::FP_EXTEND: return "fp_extend"; 2118 2119 case ISD::SINT_TO_FP: return "sint_to_fp"; 2120 case ISD::UINT_TO_FP: return "uint_to_fp"; 2121 case ISD::FP_TO_SINT: return "fp_to_sint"; 2122 case ISD::FP_TO_UINT: return "fp_to_uint"; 2123 2124 // Control flow instructions 2125 case ISD::BR: return "br"; 2126 case ISD::BRCOND: return "brcond"; 2127 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 2128 case ISD::BR_CC: return "br_cc"; 2129 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 2130 case ISD::RET: return "ret"; 2131 case ISD::CALL: return "call"; 2132 case ISD::TAILCALL:return "tailcall"; 2133 case ISD::CALLSEQ_START: return "callseq_start"; 2134 case ISD::CALLSEQ_END: return "callseq_end"; 2135 2136 // Other operators 2137 case ISD::LOAD: return "load"; 2138 case ISD::STORE: return "store"; 2139 case ISD::EXTLOAD: return "extload"; 2140 case ISD::SEXTLOAD: return "sextload"; 2141 case ISD::ZEXTLOAD: return "zextload"; 2142 case ISD::TRUNCSTORE: return "truncstore"; 2143 2144 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 2145 case ISD::EXTRACT_ELEMENT: return "extract_element"; 2146 case ISD::BUILD_PAIR: return "build_pair"; 2147 case ISD::MEMSET: return "memset"; 2148 case ISD::MEMCPY: return "memcpy"; 2149 case ISD::MEMMOVE: return "memmove"; 2150 2151 // Bit counting 2152 case ISD::CTPOP: return "ctpop"; 2153 case ISD::CTTZ: return "cttz"; 2154 case ISD::CTLZ: return "ctlz"; 2155 2156 // IO Intrinsics 2157 case ISD::READPORT: return "readport"; 2158 case ISD::WRITEPORT: return "writeport"; 2159 case ISD::READIO: return "readio"; 2160 case ISD::WRITEIO: return "writeio"; 2161 2162 case ISD::CONDCODE: 2163 switch (cast<CondCodeSDNode>(this)->get()) { 2164 default: assert(0 && "Unknown setcc condition!"); 2165 case ISD::SETOEQ: return "setoeq"; 2166 case ISD::SETOGT: return "setogt"; 2167 case ISD::SETOGE: return "setoge"; 2168 case ISD::SETOLT: return "setolt"; 2169 case ISD::SETOLE: return "setole"; 2170 case ISD::SETONE: return "setone"; 2171 2172 case ISD::SETO: return "seto"; 2173 case ISD::SETUO: return "setuo"; 2174 case ISD::SETUEQ: return "setue"; 2175 case ISD::SETUGT: return "setugt"; 2176 case ISD::SETUGE: return "setuge"; 2177 case ISD::SETULT: return "setult"; 2178 case ISD::SETULE: return "setule"; 2179 case ISD::SETUNE: return "setune"; 2180 2181 case ISD::SETEQ: return "seteq"; 2182 case ISD::SETGT: return "setgt"; 2183 case ISD::SETGE: return "setge"; 2184 case ISD::SETLT: return "setlt"; 2185 case ISD::SETLE: return "setle"; 2186 case ISD::SETNE: return "setne"; 2187 } 2188 } 2189} 2190 2191void SDNode::dump() const { dump(0); } 2192void SDNode::dump(const SelectionDAG *G) const { 2193 std::cerr << (void*)this << ": "; 2194 2195 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2196 if (i) std::cerr << ","; 2197 if (getValueType(i) == MVT::Other) 2198 std::cerr << "ch"; 2199 else 2200 std::cerr << MVT::getValueTypeString(getValueType(i)); 2201 } 2202 std::cerr << " = " << getOperationName(G); 2203 2204 std::cerr << " "; 2205 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2206 if (i) std::cerr << ", "; 2207 std::cerr << (void*)getOperand(i).Val; 2208 if (unsigned RN = getOperand(i).ResNo) 2209 std::cerr << ":" << RN; 2210 } 2211 2212 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2213 std::cerr << "<" << CSDN->getValue() << ">"; 2214 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2215 std::cerr << "<" << CSDN->getValue() << ">"; 2216 } else if (const GlobalAddressSDNode *GADN = 2217 dyn_cast<GlobalAddressSDNode>(this)) { 2218 std::cerr << "<"; 2219 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2220 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2221 std::cerr << "<" << FIDN->getIndex() << ">"; 2222 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2223 std::cerr << "<" << CP->getIndex() << ">"; 2224 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2225 std::cerr << "<"; 2226 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2227 if (LBB) 2228 std::cerr << LBB->getName() << " "; 2229 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2230 } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { 2231 if (G && MRegisterInfo::isPhysicalRegister(R->getReg())) { 2232 std::cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); 2233 } else { 2234 std::cerr << " #" << R->getReg(); 2235 } 2236 } else if (const ExternalSymbolSDNode *ES = 2237 dyn_cast<ExternalSymbolSDNode>(this)) { 2238 std::cerr << "'" << ES->getSymbol() << "'"; 2239 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2240 if (M->getValue()) 2241 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2242 else 2243 std::cerr << "<null:" << M->getOffset() << ">"; 2244 } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { 2245 std::cerr << ":" << getValueTypeString(N->getVT()); 2246 } 2247} 2248 2249static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2250 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2251 if (N->getOperand(i).Val->hasOneUse()) 2252 DumpNodes(N->getOperand(i).Val, indent+2, G); 2253 else 2254 std::cerr << "\n" << std::string(indent+2, ' ') 2255 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2256 2257 2258 std::cerr << "\n" << std::string(indent, ' '); 2259 N->dump(G); 2260} 2261 2262void SelectionDAG::dump() const { 2263 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2264 std::vector<SDNode*> Nodes(AllNodes); 2265 std::sort(Nodes.begin(), Nodes.end()); 2266 2267 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2268 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2269 DumpNodes(Nodes[i], 2, this); 2270 } 2271 2272 DumpNodes(getRoot().Val, 2, this); 2273 2274 std::cerr << "\n\n"; 2275} 2276 2277