SelectionDAG.cpp revision 8b8749f367fd30a8a3d57284576a6d59b60b69eb
1//===-- SelectionDAG.cpp - Implement the SelectionDAG data structures -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the SelectionDAG class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/Constants.h" 16#include "llvm/GlobalValue.h" 17#include "llvm/Assembly/Writer.h" 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/Support/MathExtras.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetInstrInfo.h" 22#include "llvm/Target/TargetMachine.h" 23#include <iostream> 24#include <set> 25#include <cmath> 26#include <algorithm> 27using namespace llvm; 28 29static bool isCommutativeBinOp(unsigned Opcode) { 30 switch (Opcode) { 31 case ISD::ADD: 32 case ISD::MUL: 33 case ISD::AND: 34 case ISD::OR: 35 case ISD::XOR: return true; 36 default: return false; // FIXME: Need commutative info for user ops! 37 } 38} 39 40static bool isAssociativeBinOp(unsigned Opcode) { 41 switch (Opcode) { 42 case ISD::ADD: 43 case ISD::MUL: 44 case ISD::AND: 45 case ISD::OR: 46 case ISD::XOR: return true; 47 default: return false; // FIXME: Need associative info for user ops! 48 } 49} 50 51// isInvertibleForFree - Return true if there is no cost to emitting the logical 52// inverse of this node. 53static bool isInvertibleForFree(SDOperand N) { 54 if (isa<ConstantSDNode>(N.Val)) return true; 55 if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse()) 56 return true; 57 return false; 58} 59 60 61/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 62/// when given the operation for (X op Y). 63ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { 64 // To perform this operation, we just need to swap the L and G bits of the 65 // operation. 66 unsigned OldL = (Operation >> 2) & 1; 67 unsigned OldG = (Operation >> 1) & 1; 68 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits 69 (OldL << 1) | // New G bit 70 (OldG << 2)); // New L bit. 71} 72 73/// getSetCCInverse - Return the operation corresponding to !(X op Y), where 74/// 'op' is a valid SetCC operation. 75ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { 76 unsigned Operation = Op; 77 if (isInteger) 78 Operation ^= 7; // Flip L, G, E bits, but not U. 79 else 80 Operation ^= 15; // Flip all of the condition bits. 81 if (Operation > ISD::SETTRUE2) 82 Operation &= ~8; // Don't let N and U bits get set. 83 return ISD::CondCode(Operation); 84} 85 86 87/// isSignedOp - For an integer comparison, return 1 if the comparison is a 88/// signed operation and 2 if the result is an unsigned comparison. Return zero 89/// if the operation does not depend on the sign of the input (setne and seteq). 90static int isSignedOp(ISD::CondCode Opcode) { 91 switch (Opcode) { 92 default: assert(0 && "Illegal integer setcc operation!"); 93 case ISD::SETEQ: 94 case ISD::SETNE: return 0; 95 case ISD::SETLT: 96 case ISD::SETLE: 97 case ISD::SETGT: 98 case ISD::SETGE: return 1; 99 case ISD::SETULT: 100 case ISD::SETULE: 101 case ISD::SETUGT: 102 case ISD::SETUGE: return 2; 103 } 104} 105 106/// getSetCCOrOperation - Return the result of a logical OR between different 107/// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This function 108/// returns SETCC_INVALID if it is not possible to represent the resultant 109/// comparison. 110ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, 111 bool isInteger) { 112 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 113 // Cannot fold a signed integer setcc with an unsigned integer setcc. 114 return ISD::SETCC_INVALID; 115 116 unsigned Op = Op1 | Op2; // Combine all of the condition bits. 117 118 // If the N and U bits get set then the resultant comparison DOES suddenly 119 // care about orderedness, and is true when ordered. 120 if (Op > ISD::SETTRUE2) 121 Op &= ~16; // Clear the N bit. 122 return ISD::CondCode(Op); 123} 124 125/// getSetCCAndOperation - Return the result of a logical AND between different 126/// comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 127/// function returns zero if it is not possible to represent the resultant 128/// comparison. 129ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, 130 bool isInteger) { 131 if (isInteger && (isSignedOp(Op1) | isSignedOp(Op2)) == 3) 132 // Cannot fold a signed setcc with an unsigned setcc. 133 return ISD::SETCC_INVALID; 134 135 // Combine all of the condition bits. 136 return ISD::CondCode(Op1 & Op2); 137} 138 139const TargetMachine &SelectionDAG::getTarget() const { 140 return TLI.getTargetMachine(); 141} 142 143 144/// RemoveDeadNodes - This method deletes all unreachable nodes in the 145/// SelectionDAG, including nodes (like loads) that have uses of their token 146/// chain but no other uses and no side effect. If a node is passed in as an 147/// argument, it is used as the seed for node deletion. 148void SelectionDAG::RemoveDeadNodes(SDNode *N) { 149 std::set<SDNode*> AllNodeSet(AllNodes.begin(), AllNodes.end()); 150 151 // Create a dummy node (which is not added to allnodes), that adds a reference 152 // to the root node, preventing it from being deleted. 153 SDNode *DummyNode = new SDNode(ISD::EntryToken, getRoot()); 154 155 // If we have a hint to start from, use it. 156 if (N) DeleteNodeIfDead(N, &AllNodeSet); 157 158 Restart: 159 unsigned NumNodes = AllNodeSet.size(); 160 for (std::set<SDNode*>::iterator I = AllNodeSet.begin(), E = AllNodeSet.end(); 161 I != E; ++I) { 162 // Try to delete this node. 163 DeleteNodeIfDead(*I, &AllNodeSet); 164 165 // If we actually deleted any nodes, do not use invalid iterators in 166 // AllNodeSet. 167 if (AllNodeSet.size() != NumNodes) 168 goto Restart; 169 } 170 171 // Restore AllNodes. 172 if (AllNodes.size() != NumNodes) 173 AllNodes.assign(AllNodeSet.begin(), AllNodeSet.end()); 174 175 // If the root changed (e.g. it was a dead load, update the root). 176 setRoot(DummyNode->getOperand(0)); 177 178 // Now that we are done with the dummy node, delete it. 179 DummyNode->getOperand(0).Val->removeUser(DummyNode); 180 delete DummyNode; 181} 182 183 184void SelectionDAG::DeleteNodeIfDead(SDNode *N, void *NodeSet) { 185 if (!N->use_empty()) 186 return; 187 188 // Okay, we really are going to delete this node. First take this out of the 189 // appropriate CSE map. 190 RemoveNodeFromCSEMaps(N); 191 192 // Next, brutally remove the operand list. This is safe to do, as there are 193 // no cycles in the graph. 194 while (!N->Operands.empty()) { 195 SDNode *O = N->Operands.back().Val; 196 N->Operands.pop_back(); 197 O->removeUser(N); 198 199 // Now that we removed this operand, see if there are no uses of it left. 200 DeleteNodeIfDead(O, NodeSet); 201 } 202 203 // Remove the node from the nodes set and delete it. 204 std::set<SDNode*> &AllNodeSet = *(std::set<SDNode*>*)NodeSet; 205 AllNodeSet.erase(N); 206 207 // Now that the node is gone, check to see if any of the operands of this node 208 // are dead now. 209 delete N; 210} 211 212/// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that 213/// correspond to it. This is useful when we're about to delete or repurpose 214/// the node. We don't want future request for structurally identical nodes 215/// to return N anymore. 216void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { 217 switch (N->getOpcode()) { 218 case ISD::Constant: 219 Constants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 220 N->getValueType(0))); 221 break; 222 case ISD::TargetConstant: 223 TargetConstants.erase(std::make_pair(cast<ConstantSDNode>(N)->getValue(), 224 N->getValueType(0))); 225 break; 226 case ISD::ConstantFP: { 227 union { 228 double DV; 229 uint64_t IV; 230 }; 231 DV = cast<ConstantFPSDNode>(N)->getValue(); 232 ConstantFPs.erase(std::make_pair(IV, N->getValueType(0))); 233 break; 234 } 235 case ISD::CONDCODE: 236 assert(CondCodeNodes[cast<CondCodeSDNode>(N)->get()] && 237 "Cond code doesn't exist!"); 238 CondCodeNodes[cast<CondCodeSDNode>(N)->get()] = 0; 239 break; 240 case ISD::GlobalAddress: 241 GlobalValues.erase(cast<GlobalAddressSDNode>(N)->getGlobal()); 242 break; 243 case ISD::FrameIndex: 244 FrameIndices.erase(cast<FrameIndexSDNode>(N)->getIndex()); 245 break; 246 case ISD::ConstantPool: 247 ConstantPoolIndices.erase(cast<ConstantPoolSDNode>(N)->getIndex()); 248 break; 249 case ISD::BasicBlock: 250 BBNodes.erase(cast<BasicBlockSDNode>(N)->getBasicBlock()); 251 break; 252 case ISD::ExternalSymbol: 253 ExternalSymbols.erase(cast<ExternalSymbolSDNode>(N)->getSymbol()); 254 break; 255 case ISD::VALUETYPE: 256 ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0; 257 break; 258 case ISD::Register: 259 RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0; 260 break; 261 case ISD::SRCVALUE: { 262 SrcValueSDNode *SVN = cast<SrcValueSDNode>(N); 263 ValueNodes.erase(std::make_pair(SVN->getValue(), SVN->getOffset())); 264 break; 265 } 266 case ISD::LOAD: 267 Loads.erase(std::make_pair(N->getOperand(1), 268 std::make_pair(N->getOperand(0), 269 N->getValueType(0)))); 270 break; 271 default: 272 if (N->getNumOperands() == 1) 273 UnaryOps.erase(std::make_pair(N->getOpcode(), 274 std::make_pair(N->getOperand(0), 275 N->getValueType(0)))); 276 else if (N->getNumOperands() == 2) 277 BinaryOps.erase(std::make_pair(N->getOpcode(), 278 std::make_pair(N->getOperand(0), 279 N->getOperand(1)))); 280 else if (N->getNumValues() == 1) { 281 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 282 OneResultNodes.erase(std::make_pair(N->getOpcode(), 283 std::make_pair(N->getValueType(0), 284 Ops))); 285 } else { 286 // Remove the node from the ArbitraryNodes map. 287 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 288 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 289 ArbitraryNodes.erase(std::make_pair(N->getOpcode(), 290 std::make_pair(RV, Ops))); 291 } 292 break; 293 } 294} 295 296/// AddNonLeafNodeToCSEMaps - Add the specified node back to the CSE maps. It 297/// has been taken out and modified in some way. If the specified node already 298/// exists in the CSE maps, do not modify the maps, but return the existing node 299/// instead. If it doesn't exist, add it and return null. 300/// 301SDNode *SelectionDAG::AddNonLeafNodeToCSEMaps(SDNode *N) { 302 assert(N->getNumOperands() && "This is a leaf node!"); 303 if (N->getOpcode() == ISD::LOAD) { 304 SDNode *&L = Loads[std::make_pair(N->getOperand(1), 305 std::make_pair(N->getOperand(0), 306 N->getValueType(0)))]; 307 if (L) return L; 308 L = N; 309 } else if (N->getNumOperands() == 1) { 310 SDNode *&U = UnaryOps[std::make_pair(N->getOpcode(), 311 std::make_pair(N->getOperand(0), 312 N->getValueType(0)))]; 313 if (U) return U; 314 U = N; 315 } else if (N->getNumOperands() == 2) { 316 SDNode *&B = BinaryOps[std::make_pair(N->getOpcode(), 317 std::make_pair(N->getOperand(0), 318 N->getOperand(1)))]; 319 if (B) return B; 320 B = N; 321 } else if (N->getNumValues() == 1) { 322 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 323 SDNode *&ORN = OneResultNodes[std::make_pair(N->getOpcode(), 324 std::make_pair(N->getValueType(0), Ops))]; 325 if (ORN) return ORN; 326 ORN = N; 327 } else { 328 // Remove the node from the ArbitraryNodes map. 329 std::vector<MVT::ValueType> RV(N->value_begin(), N->value_end()); 330 std::vector<SDOperand> Ops(N->op_begin(), N->op_end()); 331 SDNode *&AN = ArbitraryNodes[std::make_pair(N->getOpcode(), 332 std::make_pair(RV, Ops))]; 333 if (AN) return AN; 334 AN = N; 335 } 336 return 0; 337 338} 339 340 341 342SelectionDAG::~SelectionDAG() { 343 for (unsigned i = 0, e = AllNodes.size(); i != e; ++i) 344 delete AllNodes[i]; 345} 346 347SDOperand SelectionDAG::getZeroExtendInReg(SDOperand Op, MVT::ValueType VT) { 348 if (Op.getValueType() == VT) return Op; 349 int64_t Imm = ~0ULL >> (64-MVT::getSizeInBits(VT)); 350 return getNode(ISD::AND, Op.getValueType(), Op, 351 getConstant(Imm, Op.getValueType())); 352} 353 354SDOperand SelectionDAG::getConstant(uint64_t Val, MVT::ValueType VT) { 355 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 356 // Mask out any bits that are not valid for this constant. 357 if (VT != MVT::i64) 358 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 359 360 SDNode *&N = Constants[std::make_pair(Val, VT)]; 361 if (N) return SDOperand(N, 0); 362 N = new ConstantSDNode(false, Val, VT); 363 AllNodes.push_back(N); 364 return SDOperand(N, 0); 365} 366 367SDOperand SelectionDAG::getTargetConstant(uint64_t Val, MVT::ValueType VT) { 368 assert(MVT::isInteger(VT) && "Cannot create FP integer constant!"); 369 // Mask out any bits that are not valid for this constant. 370 if (VT != MVT::i64) 371 Val &= ((uint64_t)1 << MVT::getSizeInBits(VT)) - 1; 372 373 SDNode *&N = TargetConstants[std::make_pair(Val, VT)]; 374 if (N) return SDOperand(N, 0); 375 N = new ConstantSDNode(true, Val, VT); 376 AllNodes.push_back(N); 377 return SDOperand(N, 0); 378} 379 380SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT) { 381 assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP constant!"); 382 if (VT == MVT::f32) 383 Val = (float)Val; // Mask out extra precision. 384 385 // Do the map lookup using the actual bit pattern for the floating point 386 // value, so that we don't have problems with 0.0 comparing equal to -0.0, and 387 // we don't have issues with SNANs. 388 union { 389 double DV; 390 uint64_t IV; 391 }; 392 393 DV = Val; 394 395 SDNode *&N = ConstantFPs[std::make_pair(IV, VT)]; 396 if (N) return SDOperand(N, 0); 397 N = new ConstantFPSDNode(Val, VT); 398 AllNodes.push_back(N); 399 return SDOperand(N, 0); 400} 401 402 403 404SDOperand SelectionDAG::getGlobalAddress(const GlobalValue *GV, 405 MVT::ValueType VT) { 406 SDNode *&N = GlobalValues[GV]; 407 if (N) return SDOperand(N, 0); 408 N = new GlobalAddressSDNode(GV,VT); 409 AllNodes.push_back(N); 410 return SDOperand(N, 0); 411} 412 413SDOperand SelectionDAG::getFrameIndex(int FI, MVT::ValueType VT) { 414 SDNode *&N = FrameIndices[FI]; 415 if (N) return SDOperand(N, 0); 416 N = new FrameIndexSDNode(FI, VT); 417 AllNodes.push_back(N); 418 return SDOperand(N, 0); 419} 420 421SDOperand SelectionDAG::getConstantPool(unsigned CPIdx, MVT::ValueType VT) { 422 SDNode *N = ConstantPoolIndices[CPIdx]; 423 if (N) return SDOperand(N, 0); 424 N = new ConstantPoolSDNode(CPIdx, VT); 425 AllNodes.push_back(N); 426 return SDOperand(N, 0); 427} 428 429SDOperand SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { 430 SDNode *&N = BBNodes[MBB]; 431 if (N) return SDOperand(N, 0); 432 N = new BasicBlockSDNode(MBB); 433 AllNodes.push_back(N); 434 return SDOperand(N, 0); 435} 436 437SDOperand SelectionDAG::getValueType(MVT::ValueType VT) { 438 if ((unsigned)VT >= ValueTypeNodes.size()) 439 ValueTypeNodes.resize(VT+1); 440 if (ValueTypeNodes[VT] == 0) { 441 ValueTypeNodes[VT] = new VTSDNode(VT); 442 AllNodes.push_back(ValueTypeNodes[VT]); 443 } 444 445 return SDOperand(ValueTypeNodes[VT], 0); 446} 447 448SDOperand SelectionDAG::getExternalSymbol(const char *Sym, MVT::ValueType VT) { 449 SDNode *&N = ExternalSymbols[Sym]; 450 if (N) return SDOperand(N, 0); 451 N = new ExternalSymbolSDNode(Sym, VT); 452 AllNodes.push_back(N); 453 return SDOperand(N, 0); 454} 455 456SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) { 457 if ((unsigned)Cond >= CondCodeNodes.size()) 458 CondCodeNodes.resize(Cond+1); 459 460 if (CondCodeNodes[Cond] == 0) { 461 CondCodeNodes[Cond] = new CondCodeSDNode(Cond); 462 AllNodes.push_back(CondCodeNodes[Cond]); 463 } 464 return SDOperand(CondCodeNodes[Cond], 0); 465} 466 467SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) { 468 if (Reg >= RegNodes.size()) 469 RegNodes.resize(Reg+1); 470 RegisterSDNode *&Result = RegNodes[Reg]; 471 if (Result) { 472 assert(Result->getValueType(0) == VT && 473 "Inconsistent value types for machine registers"); 474 } else { 475 Result = new RegisterSDNode(Reg, VT); 476 AllNodes.push_back(Result); 477 } 478 return SDOperand(Result, 0); 479} 480 481SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, 482 SDOperand N2, ISD::CondCode Cond) { 483 // These setcc operations always fold. 484 switch (Cond) { 485 default: break; 486 case ISD::SETFALSE: 487 case ISD::SETFALSE2: return getConstant(0, VT); 488 case ISD::SETTRUE: 489 case ISD::SETTRUE2: return getConstant(1, VT); 490 } 491 492 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val)) { 493 uint64_t C2 = N2C->getValue(); 494 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 495 uint64_t C1 = N1C->getValue(); 496 497 // Sign extend the operands if required 498 if (ISD::isSignedIntSetCC(Cond)) { 499 C1 = N1C->getSignExtended(); 500 C2 = N2C->getSignExtended(); 501 } 502 503 switch (Cond) { 504 default: assert(0 && "Unknown integer setcc!"); 505 case ISD::SETEQ: return getConstant(C1 == C2, VT); 506 case ISD::SETNE: return getConstant(C1 != C2, VT); 507 case ISD::SETULT: return getConstant(C1 < C2, VT); 508 case ISD::SETUGT: return getConstant(C1 > C2, VT); 509 case ISD::SETULE: return getConstant(C1 <= C2, VT); 510 case ISD::SETUGE: return getConstant(C1 >= C2, VT); 511 case ISD::SETLT: return getConstant((int64_t)C1 < (int64_t)C2, VT); 512 case ISD::SETGT: return getConstant((int64_t)C1 > (int64_t)C2, VT); 513 case ISD::SETLE: return getConstant((int64_t)C1 <= (int64_t)C2, VT); 514 case ISD::SETGE: return getConstant((int64_t)C1 >= (int64_t)C2, VT); 515 } 516 } else { 517 // If the LHS is a ZERO_EXTEND and if this is an ==/!= comparison, perform 518 // the comparison on the input. 519 if (N1.getOpcode() == ISD::ZERO_EXTEND) { 520 unsigned InSize = MVT::getSizeInBits(N1.getOperand(0).getValueType()); 521 522 // If the comparison constant has bits in the upper part, the 523 // zero-extended value could never match. 524 if (C2 & (~0ULL << InSize)) { 525 unsigned VSize = MVT::getSizeInBits(N1.getValueType()); 526 switch (Cond) { 527 case ISD::SETUGT: 528 case ISD::SETUGE: 529 case ISD::SETEQ: return getConstant(0, VT); 530 case ISD::SETULT: 531 case ISD::SETULE: 532 case ISD::SETNE: return getConstant(1, VT); 533 case ISD::SETGT: 534 case ISD::SETGE: 535 // True if the sign bit of C2 is set. 536 return getConstant((C2 & (1ULL << VSize)) != 0, VT); 537 case ISD::SETLT: 538 case ISD::SETLE: 539 // True if the sign bit of C2 isn't set. 540 return getConstant((C2 & (1ULL << VSize)) == 0, VT); 541 default: 542 break; 543 } 544 } 545 546 // Otherwise, we can perform the comparison with the low bits. 547 switch (Cond) { 548 case ISD::SETEQ: 549 case ISD::SETNE: 550 case ISD::SETUGT: 551 case ISD::SETUGE: 552 case ISD::SETULT: 553 case ISD::SETULE: 554 return getSetCC(VT, N1.getOperand(0), 555 getConstant(C2, N1.getOperand(0).getValueType()), 556 Cond); 557 default: 558 break; // todo, be more careful with signed comparisons 559 } 560 } 561 562 uint64_t MinVal, MaxVal; 563 unsigned OperandBitSize = MVT::getSizeInBits(N2C->getValueType(0)); 564 if (ISD::isSignedIntSetCC(Cond)) { 565 MinVal = 1ULL << (OperandBitSize-1); 566 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 567 MaxVal = ~0ULL >> (65-OperandBitSize); 568 else 569 MaxVal = 0; 570 } else { 571 MinVal = 0; 572 MaxVal = ~0ULL >> (64-OperandBitSize); 573 } 574 575 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 576 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 577 if (C2 == MinVal) return getConstant(1, VT); // X >= MIN --> true 578 --C2; // X >= C1 --> X > (C1-1) 579 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 580 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 581 } 582 583 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 584 if (C2 == MaxVal) return getConstant(1, VT); // X <= MAX --> true 585 ++C2; // X <= C1 --> X < (C1+1) 586 return getSetCC(VT, N1, getConstant(C2, N2.getValueType()), 587 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 588 } 589 590 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal) 591 return getConstant(0, VT); // X < MIN --> false 592 593 // Canonicalize setgt X, Min --> setne X, Min 594 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal) 595 return getSetCC(VT, N1, N2, ISD::SETNE); 596 597 // If we have setult X, 1, turn it into seteq X, 0 598 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1) 599 return getSetCC(VT, N1, getConstant(MinVal, N1.getValueType()), 600 ISD::SETEQ); 601 // If we have setugt X, Max-1, turn it into seteq X, Max 602 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1) 603 return getSetCC(VT, N1, getConstant(MaxVal, N1.getValueType()), 604 ISD::SETEQ); 605 606 // If we have "setcc X, C1", check to see if we can shrink the immediate 607 // by changing cc. 608 609 // SETUGT X, SINTMAX -> SETLT X, 0 610 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 611 C2 == (~0ULL >> (65-OperandBitSize))) 612 return getSetCC(VT, N1, getConstant(0, N2.getValueType()), ISD::SETLT); 613 614 // FIXME: Implement the rest of these. 615 616 617 // Fold bit comparisons when we can. 618 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 619 VT == N1.getValueType() && N1.getOpcode() == ISD::AND) 620 if (ConstantSDNode *AndRHS = 621 dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 622 if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 623 // Perform the xform if the AND RHS is a single bit. 624 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 625 return getNode(ISD::SRL, VT, N1, 626 getConstant(Log2_64(AndRHS->getValue()), 627 TLI.getShiftAmountTy())); 628 } 629 } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { 630 // (X & 8) == 8 --> (X & 8) >> 3 631 // Perform the xform if C2 is a single bit. 632 if ((C2 & (C2-1)) == 0) { 633 return getNode(ISD::SRL, VT, N1, 634 getConstant(Log2_64(C2),TLI.getShiftAmountTy())); 635 } 636 } 637 } 638 } 639 } else if (isa<ConstantSDNode>(N1.Val)) { 640 // Ensure that the constant occurs on the RHS. 641 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 642 } 643 644 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) 645 if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.Val)) { 646 double C1 = N1C->getValue(), C2 = N2C->getValue(); 647 648 switch (Cond) { 649 default: break; // FIXME: Implement the rest of these! 650 case ISD::SETEQ: return getConstant(C1 == C2, VT); 651 case ISD::SETNE: return getConstant(C1 != C2, VT); 652 case ISD::SETLT: return getConstant(C1 < C2, VT); 653 case ISD::SETGT: return getConstant(C1 > C2, VT); 654 case ISD::SETLE: return getConstant(C1 <= C2, VT); 655 case ISD::SETGE: return getConstant(C1 >= C2, VT); 656 } 657 } else { 658 // Ensure that the constant occurs on the RHS. 659 return getSetCC(VT, N2, N1, ISD::getSetCCSwappedOperands(Cond)); 660 } 661 662 if (N1 == N2) { 663 // We can always fold X == Y for integer setcc's. 664 if (MVT::isInteger(N1.getValueType())) 665 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 666 unsigned UOF = ISD::getUnorderedFlavor(Cond); 667 if (UOF == 2) // FP operators that are undefined on NaNs. 668 return getConstant(ISD::isTrueWhenEqual(Cond), VT); 669 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 670 return getConstant(UOF, VT); 671 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 672 // if it is not already. 673 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 674 if (NewCond != Cond) 675 return getSetCC(VT, N1, N2, NewCond); 676 } 677 678 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 679 MVT::isInteger(N1.getValueType())) { 680 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 681 N1.getOpcode() == ISD::XOR) { 682 // Simplify (X+Y) == (X+Z) --> Y == Z 683 if (N1.getOpcode() == N2.getOpcode()) { 684 if (N1.getOperand(0) == N2.getOperand(0)) 685 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 686 if (N1.getOperand(1) == N2.getOperand(1)) 687 return getSetCC(VT, N1.getOperand(0), N2.getOperand(0), Cond); 688 if (isCommutativeBinOp(N1.getOpcode())) { 689 // If X op Y == Y op X, try other combinations. 690 if (N1.getOperand(0) == N2.getOperand(1)) 691 return getSetCC(VT, N1.getOperand(1), N2.getOperand(0), Cond); 692 if (N1.getOperand(1) == N2.getOperand(0)) 693 return getSetCC(VT, N1.getOperand(1), N2.getOperand(1), Cond); 694 } 695 } 696 697 // FIXME: move this stuff to the DAG Combiner when it exists! 698 699 // Simplify (X+Z) == X --> Z == 0 700 if (N1.getOperand(0) == N2) 701 return getSetCC(VT, N1.getOperand(1), 702 getConstant(0, N1.getValueType()), Cond); 703 if (N1.getOperand(1) == N2) { 704 if (isCommutativeBinOp(N1.getOpcode())) 705 return getSetCC(VT, N1.getOperand(0), 706 getConstant(0, N1.getValueType()), Cond); 707 else { 708 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 709 // (Z-X) == X --> Z == X<<1 710 return getSetCC(VT, N1.getOperand(0), 711 getNode(ISD::SHL, N2.getValueType(), 712 N2, getConstant(1, TLI.getShiftAmountTy())), 713 Cond); 714 } 715 } 716 } 717 718 if (N2.getOpcode() == ISD::ADD || N2.getOpcode() == ISD::SUB || 719 N2.getOpcode() == ISD::XOR) { 720 // Simplify X == (X+Z) --> Z == 0 721 if (N2.getOperand(0) == N1) { 722 return getSetCC(VT, N2.getOperand(1), 723 getConstant(0, N2.getValueType()), Cond); 724 } else if (N2.getOperand(1) == N1) { 725 if (isCommutativeBinOp(N2.getOpcode())) { 726 return getSetCC(VT, N2.getOperand(0), 727 getConstant(0, N2.getValueType()), Cond); 728 } else { 729 assert(N2.getOpcode() == ISD::SUB && "Unexpected operation!"); 730 // X == (Z-X) --> X<<1 == Z 731 return getSetCC(VT, getNode(ISD::SHL, N2.getValueType(), N1, 732 getConstant(1, TLI.getShiftAmountTy())), 733 N2.getOperand(0), Cond); 734 } 735 } 736 } 737 } 738 739 // Fold away ALL boolean setcc's. 740 if (N1.getValueType() == MVT::i1) { 741 switch (Cond) { 742 default: assert(0 && "Unknown integer setcc!"); 743 case ISD::SETEQ: // X == Y -> (X^Y)^1 744 N1 = getNode(ISD::XOR, MVT::i1, 745 getNode(ISD::XOR, MVT::i1, N1, N2), 746 getConstant(1, MVT::i1)); 747 break; 748 case ISD::SETNE: // X != Y --> (X^Y) 749 N1 = getNode(ISD::XOR, MVT::i1, N1, N2); 750 break; 751 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 752 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 753 N1 = getNode(ISD::AND, MVT::i1, N2, 754 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 755 break; 756 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 757 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 758 N1 = getNode(ISD::AND, MVT::i1, N1, 759 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 760 break; 761 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 762 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 763 N1 = getNode(ISD::OR, MVT::i1, N2, 764 getNode(ISD::XOR, MVT::i1, N1, getConstant(1, MVT::i1))); 765 break; 766 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 767 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 768 N1 = getNode(ISD::OR, MVT::i1, N1, 769 getNode(ISD::XOR, MVT::i1, N2, getConstant(1, MVT::i1))); 770 break; 771 } 772 if (VT != MVT::i1) 773 N1 = getNode(ISD::ZERO_EXTEND, VT, N1); 774 return N1; 775 } 776 777 // Could not fold it. 778 return SDOperand(); 779} 780 781SDOperand SelectionDAG::SimplifySelectCC(SDOperand N1, SDOperand N2, 782 SDOperand N3, SDOperand N4, 783 ISD::CondCode CC) { 784 MVT::ValueType VT = N3.getValueType(); 785 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 786 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 787 ConstantSDNode *N4C = dyn_cast<ConstantSDNode>(N4.Val); 788 789 // Check to see if we can simplify the select into an fabs node 790 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N2)) { 791 // Allow either -0.0 or 0.0 792 if (CFP->getValue() == 0.0) { 793 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 794 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 795 N1 == N3 && N4.getOpcode() == ISD::FNEG && 796 N1 == N4.getOperand(0)) 797 return getNode(ISD::FABS, VT, N1); 798 799 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 800 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 801 N1 == N4 && N3.getOpcode() == ISD::FNEG && 802 N3.getOperand(0) == N4) 803 return getNode(ISD::FABS, VT, N4); 804 } 805 } 806 807 // Check to see if we can perform the "gzip trick", transforming 808 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 809 if (N2C && N2C->isNullValue() && N4C && N4C->isNullValue() && 810 MVT::isInteger(N1.getValueType()) && 811 MVT::isInteger(N3.getValueType()) && CC == ISD::SETLT) { 812 MVT::ValueType XType = N1.getValueType(); 813 MVT::ValueType AType = N3.getValueType(); 814 if (XType >= AType) { 815 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 816 // single-bit constant. FIXME: remove once the dag combiner 817 // exists. 818 if (N3C && ((N3C->getValue() & (N3C->getValue()-1)) == 0)) { 819 unsigned ShCtV = Log2_64(N3C->getValue()); 820 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 821 SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy()); 822 SDOperand Shift = getNode(ISD::SRL, XType, N1, ShCt); 823 if (XType > AType) 824 Shift = getNode(ISD::TRUNCATE, AType, Shift); 825 return getNode(ISD::AND, AType, Shift, N3); 826 } 827 SDOperand Shift = getNode(ISD::SRA, XType, N1, 828 getConstant(MVT::getSizeInBits(XType)-1, 829 TLI.getShiftAmountTy())); 830 if (XType > AType) 831 Shift = getNode(ISD::TRUNCATE, AType, Shift); 832 return getNode(ISD::AND, AType, Shift, N3); 833 } 834 } 835 836 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 837 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 838 if (N2C && N2C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 839 N1 == N4 && N3.getOpcode() == ISD::SUB && N1 == N3.getOperand(1)) { 840 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 841 MVT::ValueType XType = N1.getValueType(); 842 if (SubC->isNullValue() && MVT::isInteger(XType)) { 843 SDOperand Shift = getNode(ISD::SRA, XType, N1, 844 getConstant(MVT::getSizeInBits(XType)-1, 845 TLI.getShiftAmountTy())); 846 return getNode(ISD::XOR, XType, getNode(ISD::ADD, XType, N1, Shift), 847 Shift); 848 } 849 } 850 } 851 852 // Could not fold it. 853 return SDOperand(); 854} 855 856/// getNode - Gets or creates the specified node. 857/// 858SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT) { 859 SDNode *N = new SDNode(Opcode, VT); 860 AllNodes.push_back(N); 861 return SDOperand(N, 0); 862} 863 864SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 865 SDOperand Operand) { 866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.Val)) { 867 uint64_t Val = C->getValue(); 868 switch (Opcode) { 869 default: break; 870 case ISD::SIGN_EXTEND: return getConstant(C->getSignExtended(), VT); 871 case ISD::ZERO_EXTEND: return getConstant(Val, VT); 872 case ISD::TRUNCATE: return getConstant(Val, VT); 873 case ISD::SINT_TO_FP: return getConstantFP(C->getSignExtended(), VT); 874 case ISD::UINT_TO_FP: return getConstantFP(C->getValue(), VT); 875 } 876 } 877 878 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.Val)) 879 switch (Opcode) { 880 case ISD::FNEG: 881 return getConstantFP(-C->getValue(), VT); 882 case ISD::FP_ROUND: 883 case ISD::FP_EXTEND: 884 return getConstantFP(C->getValue(), VT); 885 case ISD::FP_TO_SINT: 886 return getConstant((int64_t)C->getValue(), VT); 887 case ISD::FP_TO_UINT: 888 return getConstant((uint64_t)C->getValue(), VT); 889 } 890 891 unsigned OpOpcode = Operand.Val->getOpcode(); 892 switch (Opcode) { 893 case ISD::TokenFactor: 894 return Operand; // Factor of one node? No factor. 895 case ISD::SIGN_EXTEND: 896 if (Operand.getValueType() == VT) return Operand; // noop extension 897 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) 898 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 899 break; 900 case ISD::ZERO_EXTEND: 901 if (Operand.getValueType() == VT) return Operand; // noop extension 902 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) 903 return getNode(ISD::ZERO_EXTEND, VT, Operand.Val->getOperand(0)); 904 break; 905 case ISD::TRUNCATE: 906 if (Operand.getValueType() == VT) return Operand; // noop truncate 907 if (OpOpcode == ISD::TRUNCATE) 908 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 909 else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND) { 910 // If the source is smaller than the dest, we still need an extend. 911 if (Operand.Val->getOperand(0).getValueType() < VT) 912 return getNode(OpOpcode, VT, Operand.Val->getOperand(0)); 913 else if (Operand.Val->getOperand(0).getValueType() > VT) 914 return getNode(ISD::TRUNCATE, VT, Operand.Val->getOperand(0)); 915 else 916 return Operand.Val->getOperand(0); 917 } 918 break; 919 case ISD::FNEG: 920 if (OpOpcode == ISD::SUB) // -(X-Y) -> (Y-X) 921 return getNode(ISD::SUB, VT, Operand.Val->getOperand(1), 922 Operand.Val->getOperand(0)); 923 if (OpOpcode == ISD::FNEG) // --X -> X 924 return Operand.Val->getOperand(0); 925 break; 926 case ISD::FABS: 927 if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X) 928 return getNode(ISD::FABS, VT, Operand.Val->getOperand(0)); 929 break; 930 } 931 932 SDNode *&N = UnaryOps[std::make_pair(Opcode, std::make_pair(Operand, VT))]; 933 if (N) return SDOperand(N, 0); 934 N = new SDNode(Opcode, Operand); 935 N->setValueTypes(VT); 936 AllNodes.push_back(N); 937 return SDOperand(N, 0); 938} 939 940/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 941/// this predicate to simplify operations downstream. V and Mask are known to 942/// be the same type. 943static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 944 const TargetLowering &TLI) { 945 unsigned SrcBits; 946 if (Mask == 0) return true; 947 948 // If we know the result of a setcc has the top bits zero, use this info. 949 switch (Op.getOpcode()) { 950 case ISD::Constant: 951 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 952 953 case ISD::SETCC: 954 return ((Mask & 1) == 0) && 955 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 956 957 case ISD::ZEXTLOAD: 958 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 959 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 960 case ISD::ZERO_EXTEND: 961 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 962 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 963 964 case ISD::AND: 965 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 966 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 967 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 968 969 // FALL THROUGH 970 case ISD::OR: 971 case ISD::XOR: 972 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 973 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 974 case ISD::SELECT: 975 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 976 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 977 978 case ISD::SRL: 979 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 980 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 981 uint64_t NewVal = Mask << ShAmt->getValue(); 982 SrcBits = MVT::getSizeInBits(Op.getValueType()); 983 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 984 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 985 } 986 return false; 987 case ISD::SHL: 988 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 989 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 990 uint64_t NewVal = Mask >> ShAmt->getValue(); 991 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 992 } 993 return false; 994 // TODO we could handle some SRA cases here. 995 default: break; 996 } 997 998 return false; 999} 1000 1001 1002 1003SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1004 SDOperand N1, SDOperand N2) { 1005#ifndef NDEBUG 1006 switch (Opcode) { 1007 case ISD::TokenFactor: 1008 assert(VT == MVT::Other && N1.getValueType() == MVT::Other && 1009 N2.getValueType() == MVT::Other && "Invalid token factor!"); 1010 break; 1011 case ISD::AND: 1012 case ISD::OR: 1013 case ISD::XOR: 1014 case ISD::UDIV: 1015 case ISD::UREM: 1016 case ISD::MULHU: 1017 case ISD::MULHS: 1018 assert(MVT::isInteger(VT) && "This operator does not apply to FP types!"); 1019 // fall through 1020 case ISD::ADD: 1021 case ISD::SUB: 1022 case ISD::MUL: 1023 case ISD::SDIV: 1024 case ISD::SREM: 1025 assert(N1.getValueType() == N2.getValueType() && 1026 N1.getValueType() == VT && "Binary operator types must match!"); 1027 break; 1028 1029 case ISD::SHL: 1030 case ISD::SRA: 1031 case ISD::SRL: 1032 assert(VT == N1.getValueType() && 1033 "Shift operators return type must be the same as their first arg"); 1034 assert(MVT::isInteger(VT) && MVT::isInteger(N2.getValueType()) && 1035 VT != MVT::i1 && "Shifts only work on integers"); 1036 break; 1037 case ISD::FP_ROUND_INREG: { 1038 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1039 assert(VT == N1.getValueType() && "Not an inreg round!"); 1040 assert(MVT::isFloatingPoint(VT) && MVT::isFloatingPoint(EVT) && 1041 "Cannot FP_ROUND_INREG integer types"); 1042 assert(EVT <= VT && "Not rounding down!"); 1043 break; 1044 } 1045 case ISD::SIGN_EXTEND_INREG: { 1046 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1047 assert(VT == N1.getValueType() && "Not an inreg extend!"); 1048 assert(MVT::isInteger(VT) && MVT::isInteger(EVT) && 1049 "Cannot *_EXTEND_INREG FP types"); 1050 assert(EVT <= VT && "Not extending!"); 1051 } 1052 1053 default: break; 1054 } 1055#endif 1056 1057 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1058 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1059 if (N1C) { 1060 if (N2C) { 1061 uint64_t C1 = N1C->getValue(), C2 = N2C->getValue(); 1062 switch (Opcode) { 1063 case ISD::ADD: return getConstant(C1 + C2, VT); 1064 case ISD::SUB: return getConstant(C1 - C2, VT); 1065 case ISD::MUL: return getConstant(C1 * C2, VT); 1066 case ISD::UDIV: 1067 if (C2) return getConstant(C1 / C2, VT); 1068 break; 1069 case ISD::UREM : 1070 if (C2) return getConstant(C1 % C2, VT); 1071 break; 1072 case ISD::SDIV : 1073 if (C2) return getConstant(N1C->getSignExtended() / 1074 N2C->getSignExtended(), VT); 1075 break; 1076 case ISD::SREM : 1077 if (C2) return getConstant(N1C->getSignExtended() % 1078 N2C->getSignExtended(), VT); 1079 break; 1080 case ISD::AND : return getConstant(C1 & C2, VT); 1081 case ISD::OR : return getConstant(C1 | C2, VT); 1082 case ISD::XOR : return getConstant(C1 ^ C2, VT); 1083 case ISD::SHL : return getConstant(C1 << (int)C2, VT); 1084 case ISD::SRL : return getConstant(C1 >> (unsigned)C2, VT); 1085 case ISD::SRA : return getConstant(N1C->getSignExtended() >>(int)C2, VT); 1086 default: break; 1087 } 1088 1089 } else { // Cannonicalize constant to RHS if commutative 1090 if (isCommutativeBinOp(Opcode)) { 1091 std::swap(N1C, N2C); 1092 std::swap(N1, N2); 1093 } 1094 } 1095 1096 switch (Opcode) { 1097 default: break; 1098 case ISD::SHL: // shl 0, X -> 0 1099 if (N1C->isNullValue()) return N1; 1100 break; 1101 case ISD::SRL: // srl 0, X -> 0 1102 if (N1C->isNullValue()) return N1; 1103 break; 1104 case ISD::SRA: // sra -1, X -> -1 1105 if (N1C->isAllOnesValue()) return N1; 1106 break; 1107 case ISD::SIGN_EXTEND_INREG: // SIGN_EXTEND_INREG N1C, EVT 1108 // Extending a constant? Just return the extended constant. 1109 SDOperand Tmp = getNode(ISD::TRUNCATE, cast<VTSDNode>(N2)->getVT(), N1); 1110 return getNode(ISD::SIGN_EXTEND, VT, Tmp); 1111 } 1112 } 1113 1114 if (N2C) { 1115 uint64_t C2 = N2C->getValue(); 1116 1117 switch (Opcode) { 1118 case ISD::ADD: 1119 if (!C2) return N1; // add X, 0 -> X 1120 break; 1121 case ISD::SUB: 1122 if (!C2) return N1; // sub X, 0 -> X 1123 return getNode(ISD::ADD, VT, N1, getConstant(-C2, VT)); 1124 case ISD::MUL: 1125 if (!C2) return N2; // mul X, 0 -> 0 1126 if (N2C->isAllOnesValue()) // mul X, -1 -> 0-X 1127 return getNode(ISD::SUB, VT, getConstant(0, VT), N1); 1128 1129 // FIXME: Move this to the DAG combiner when it exists. 1130 if ((C2 & C2-1) == 0) { 1131 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1132 return getNode(ISD::SHL, VT, N1, ShAmt); 1133 } 1134 break; 1135 1136 case ISD::MULHU: 1137 case ISD::MULHS: 1138 if (!C2) return N2; // mul X, 0 -> 0 1139 1140 if (C2 == 1) // 0X*01 -> 0X hi(0X) == 0 1141 return getConstant(0, VT); 1142 1143 // Many others could be handled here, including -1, powers of 2, etc. 1144 break; 1145 1146 case ISD::UDIV: 1147 // FIXME: Move this to the DAG combiner when it exists. 1148 if ((C2 & C2-1) == 0 && C2) { 1149 SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy()); 1150 return getNode(ISD::SRL, VT, N1, ShAmt); 1151 } 1152 break; 1153 1154 case ISD::SHL: 1155 case ISD::SRL: 1156 case ISD::SRA: 1157 // If the shift amount is bigger than the size of the data, then all the 1158 // bits are shifted out. Simplify to undef. 1159 if (C2 >= MVT::getSizeInBits(N1.getValueType())) { 1160 return getNode(ISD::UNDEF, N1.getValueType()); 1161 } 1162 if (C2 == 0) return N1; 1163 1164 if (Opcode == ISD::SRA) { 1165 // If the sign bit is known to be zero, switch this to a SRL. 1166 if (MaskedValueIsZero(N1, 1167 1ULL << MVT::getSizeInBits(N1.getValueType())-1, 1168 TLI)) 1169 return getNode(ISD::SRL, N1.getValueType(), N1, N2); 1170 } else { 1171 // If the part left over is known to be zero, the whole thing is zero. 1172 uint64_t TypeMask = ~0ULL >> (64-MVT::getSizeInBits(N1.getValueType())); 1173 if (Opcode == ISD::SRL) { 1174 if (MaskedValueIsZero(N1, TypeMask << C2, TLI)) 1175 return getConstant(0, N1.getValueType()); 1176 } else if (Opcode == ISD::SHL) { 1177 if (MaskedValueIsZero(N1, TypeMask >> C2, TLI)) 1178 return getConstant(0, N1.getValueType()); 1179 } 1180 } 1181 1182 if (Opcode == ISD::SHL && N1.getNumOperands() == 2) 1183 if (ConstantSDNode *OpSA = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1184 unsigned OpSAC = OpSA->getValue(); 1185 if (N1.getOpcode() == ISD::SHL) { 1186 if (C2+OpSAC >= MVT::getSizeInBits(N1.getValueType())) 1187 return getConstant(0, N1.getValueType()); 1188 return getNode(ISD::SHL, N1.getValueType(), N1.getOperand(0), 1189 getConstant(C2+OpSAC, N2.getValueType())); 1190 } else if (N1.getOpcode() == ISD::SRL) { 1191 // (X >> C1) << C2: if C2 > C1, ((X & ~0<<C1) << C2-C1) 1192 SDOperand Mask = getNode(ISD::AND, VT, N1.getOperand(0), 1193 getConstant(~0ULL << OpSAC, VT)); 1194 if (C2 > OpSAC) { 1195 return getNode(ISD::SHL, VT, Mask, 1196 getConstant(C2-OpSAC, N2.getValueType())); 1197 } else { 1198 // (X >> C1) << C2: if C2 <= C1, ((X & ~0<<C1) >> C1-C2) 1199 return getNode(ISD::SRL, VT, Mask, 1200 getConstant(OpSAC-C2, N2.getValueType())); 1201 } 1202 } else if (N1.getOpcode() == ISD::SRA) { 1203 // if C1 == C2, just mask out low bits. 1204 if (C2 == OpSAC) 1205 return getNode(ISD::AND, VT, N1.getOperand(0), 1206 getConstant(~0ULL << C2, VT)); 1207 } 1208 } 1209 break; 1210 1211 case ISD::AND: 1212 if (!C2) return N2; // X and 0 -> 0 1213 if (N2C->isAllOnesValue()) 1214 return N1; // X and -1 -> X 1215 1216 if (MaskedValueIsZero(N1, C2, TLI)) // X and 0 -> 0 1217 return getConstant(0, VT); 1218 1219 { 1220 uint64_t NotC2 = ~C2; 1221 if (VT != MVT::i64) 1222 NotC2 &= (1ULL << MVT::getSizeInBits(VT))-1; 1223 1224 if (MaskedValueIsZero(N1, NotC2, TLI)) 1225 return N1; // if (X & ~C2) -> 0, the and is redundant 1226 } 1227 1228 // FIXME: Should add a corresponding version of this for 1229 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 1230 // we don't have yet. 1231 1232 // and (sign_extend_inreg x:16:32), 1 -> and x, 1 1233 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) { 1234 // If we are masking out the part of our input that was extended, just 1235 // mask the input to the extension directly. 1236 unsigned ExtendBits = 1237 MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT()); 1238 if ((C2 & (~0ULL << ExtendBits)) == 0) 1239 return getNode(ISD::AND, VT, N1.getOperand(0), N2); 1240 } else if (N1.getOpcode() == ISD::OR) { 1241 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) 1242 if ((ORI->getValue() & C2) == C2) { 1243 // If the 'or' is setting all of the bits that we are masking for, 1244 // we know the result of the AND will be the AND mask itself. 1245 return N2; 1246 } 1247 } 1248 break; 1249 case ISD::OR: 1250 if (!C2)return N1; // X or 0 -> X 1251 if (N2C->isAllOnesValue()) 1252 return N2; // X or -1 -> -1 1253 break; 1254 case ISD::XOR: 1255 if (!C2) return N1; // X xor 0 -> X 1256 if (N2C->isAllOnesValue()) { 1257 if (N1.Val->getOpcode() == ISD::SETCC){ 1258 SDNode *SetCC = N1.Val; 1259 // !(X op Y) -> (X !op Y) 1260 bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType()); 1261 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get(); 1262 return getSetCC(SetCC->getValueType(0), 1263 SetCC->getOperand(0), SetCC->getOperand(1), 1264 ISD::getSetCCInverse(CC, isInteger)); 1265 } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) { 1266 SDNode *Op = N1.Val; 1267 // !(X or Y) -> (!X and !Y) iff X or Y are freely invertible 1268 // !(X and Y) -> (!X or !Y) iff X or Y are freely invertible 1269 SDOperand LHS = Op->getOperand(0), RHS = Op->getOperand(1); 1270 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 1271 LHS = getNode(ISD::XOR, VT, LHS, N2); // RHS = ~LHS 1272 RHS = getNode(ISD::XOR, VT, RHS, N2); // RHS = ~RHS 1273 if (Op->getOpcode() == ISD::AND) 1274 return getNode(ISD::OR, VT, LHS, RHS); 1275 return getNode(ISD::AND, VT, LHS, RHS); 1276 } 1277 } 1278 // X xor -1 -> not(x) ? 1279 } 1280 break; 1281 } 1282 1283 // Reassociate ((X op C1) op C2) if possible. 1284 if (N1.getOpcode() == Opcode && isAssociativeBinOp(Opcode)) 1285 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1))) 1286 return getNode(Opcode, VT, N1.Val->getOperand(0), 1287 getNode(Opcode, VT, N2, N1.Val->getOperand(1))); 1288 } 1289 1290 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 1291 ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2.Val); 1292 if (N1CFP) { 1293 if (N2CFP) { 1294 double C1 = N1CFP->getValue(), C2 = N2CFP->getValue(); 1295 switch (Opcode) { 1296 case ISD::ADD: return getConstantFP(C1 + C2, VT); 1297 case ISD::SUB: return getConstantFP(C1 - C2, VT); 1298 case ISD::MUL: return getConstantFP(C1 * C2, VT); 1299 case ISD::SDIV: 1300 if (C2) return getConstantFP(C1 / C2, VT); 1301 break; 1302 case ISD::SREM : 1303 if (C2) return getConstantFP(fmod(C1, C2), VT); 1304 break; 1305 default: break; 1306 } 1307 1308 } else { // Cannonicalize constant to RHS if commutative 1309 if (isCommutativeBinOp(Opcode)) { 1310 std::swap(N1CFP, N2CFP); 1311 std::swap(N1, N2); 1312 } 1313 } 1314 1315 if (Opcode == ISD::FP_ROUND_INREG) 1316 return getNode(ISD::FP_EXTEND, VT, 1317 getNode(ISD::FP_ROUND, cast<VTSDNode>(N2)->getVT(), N1)); 1318 } 1319 1320 // Finally, fold operations that do not require constants. 1321 switch (Opcode) { 1322 case ISD::TokenFactor: 1323 if (N1.getOpcode() == ISD::EntryToken) 1324 return N2; 1325 if (N2.getOpcode() == ISD::EntryToken) 1326 return N1; 1327 break; 1328 1329 case ISD::AND: 1330 case ISD::OR: 1331 if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){ 1332 SDNode *LHS = N1.Val, *RHS = N2.Val; 1333 SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0); 1334 SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1); 1335 ISD::CondCode Op1 = cast<CondCodeSDNode>(LHS->getOperand(2))->get(); 1336 ISD::CondCode Op2 = cast<CondCodeSDNode>(RHS->getOperand(2))->get(); 1337 1338 if (LR == RR && isa<ConstantSDNode>(LR) && 1339 Op2 == Op1 && MVT::isInteger(LL.getValueType())) { 1340 // (X != 0) | (Y != 0) -> (X|Y != 0) 1341 // (X == 0) & (Y == 0) -> (X|Y == 0) 1342 // (X < 0) | (Y < 0) -> (X|Y < 0) 1343 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1344 ((Op2 == ISD::SETEQ && Opcode == ISD::AND) || 1345 (Op2 == ISD::SETNE && Opcode == ISD::OR) || 1346 (Op2 == ISD::SETLT && Opcode == ISD::OR))) 1347 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), LR, 1348 Op2); 1349 1350 if (cast<ConstantSDNode>(LR)->isAllOnesValue()) { 1351 // (X == -1) & (Y == -1) -> (X&Y == -1) 1352 // (X != -1) | (Y != -1) -> (X&Y != -1) 1353 // (X > -1) | (Y > -1) -> (X&Y > -1) 1354 if ((Opcode == ISD::AND && Op2 == ISD::SETEQ) || 1355 (Opcode == ISD::OR && Op2 == ISD::SETNE) || 1356 (Opcode == ISD::OR && Op2 == ISD::SETGT)) 1357 return getSetCC(VT, getNode(ISD::AND, LR.getValueType(), LL, RL), 1358 LR, Op2); 1359 // (X > -1) & (Y > -1) -> (X|Y > -1) 1360 if (Opcode == ISD::AND && Op2 == ISD::SETGT) 1361 return getSetCC(VT, getNode(ISD::OR, LR.getValueType(), LL, RL), 1362 LR, Op2); 1363 } 1364 } 1365 1366 // (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y) 1367 if (LL == RR && LR == RL) { 1368 Op2 = ISD::getSetCCSwappedOperands(Op2); 1369 goto MatchedBackwards; 1370 } 1371 1372 if (LL == RL && LR == RR) { 1373 MatchedBackwards: 1374 ISD::CondCode Result; 1375 bool isInteger = MVT::isInteger(LL.getValueType()); 1376 if (Opcode == ISD::OR) 1377 Result = ISD::getSetCCOrOperation(Op1, Op2, isInteger); 1378 else 1379 Result = ISD::getSetCCAndOperation(Op1, Op2, isInteger); 1380 1381 if (Result != ISD::SETCC_INVALID) 1382 return getSetCC(LHS->getValueType(0), LL, LR, Result); 1383 } 1384 } 1385 1386 // and/or zext(a), zext(b) -> zext(and/or a, b) 1387 if (N1.getOpcode() == ISD::ZERO_EXTEND && 1388 N2.getOpcode() == ISD::ZERO_EXTEND && 1389 N1.getOperand(0).getValueType() == N2.getOperand(0).getValueType()) 1390 return getNode(ISD::ZERO_EXTEND, VT, 1391 getNode(Opcode, N1.getOperand(0).getValueType(), 1392 N1.getOperand(0), N2.getOperand(0))); 1393 break; 1394 case ISD::XOR: 1395 if (N1 == N2) return getConstant(0, VT); // xor X, Y -> 0 1396 break; 1397 case ISD::ADD: 1398 if (N2.getOpcode() == ISD::FNEG) // (A+ (-B) -> A-B 1399 return getNode(ISD::SUB, VT, N1, N2.getOperand(0)); 1400 if (N1.getOpcode() == ISD::FNEG) // ((-A)+B) -> B-A 1401 return getNode(ISD::SUB, VT, N2, N1.getOperand(0)); 1402 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1403 cast<ConstantSDNode>(N1.getOperand(0))->getValue() == 0) 1404 return getNode(ISD::SUB, VT, N2, N1.getOperand(1)); // (0-A)+B -> B-A 1405 if (N2.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N2.getOperand(0)) && 1406 cast<ConstantSDNode>(N2.getOperand(0))->getValue() == 0) 1407 return getNode(ISD::SUB, VT, N1, N2.getOperand(1)); // A+(0-B) -> A-B 1408 if (N2.getOpcode() == ISD::SUB && N1 == N2.Val->getOperand(1) && 1409 !MVT::isFloatingPoint(N2.getValueType())) 1410 return N2.Val->getOperand(0); // A+(B-A) -> B 1411 break; 1412 case ISD::SUB: 1413 if (N1.getOpcode() == ISD::ADD) { 1414 if (N1.Val->getOperand(0) == N2 && 1415 !MVT::isFloatingPoint(N2.getValueType())) 1416 return N1.Val->getOperand(1); // (A+B)-A == B 1417 if (N1.Val->getOperand(1) == N2 && 1418 !MVT::isFloatingPoint(N2.getValueType())) 1419 return N1.Val->getOperand(0); // (A+B)-B == A 1420 } 1421 if (N2.getOpcode() == ISD::FNEG) // (A- (-B) -> A+B 1422 return getNode(ISD::ADD, VT, N1, N2.getOperand(0)); 1423 break; 1424 case ISD::FP_ROUND_INREG: 1425 if (cast<VTSDNode>(N2)->getVT() == VT) return N1; // Not actually rounding. 1426 break; 1427 case ISD::SIGN_EXTEND_INREG: { 1428 MVT::ValueType EVT = cast<VTSDNode>(N2)->getVT(); 1429 if (EVT == VT) return N1; // Not actually extending 1430 1431 // If we are sign extending an extension, use the original source. 1432 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) 1433 if (cast<VTSDNode>(N1.getOperand(1))->getVT() <= EVT) 1434 return N1; 1435 1436 // If we are sign extending a sextload, return just the load. 1437 if (N1.getOpcode() == ISD::SEXTLOAD) 1438 if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT) 1439 return N1; 1440 1441 // If we are extending the result of a setcc, and we already know the 1442 // contents of the top bits, eliminate the extension. 1443 if (N1.getOpcode() == ISD::SETCC && 1444 TLI.getSetCCResultContents() == 1445 TargetLowering::ZeroOrNegativeOneSetCCResult) 1446 return N1; 1447 1448 // If we are sign extending the result of an (and X, C) operation, and we 1449 // know the extended bits are zeros already, don't do the extend. 1450 if (N1.getOpcode() == ISD::AND) 1451 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 1452 uint64_t Mask = N1C->getValue(); 1453 unsigned NumBits = MVT::getSizeInBits(EVT); 1454 if ((Mask & (~0ULL << (NumBits-1))) == 0) 1455 return N1; 1456 } 1457 break; 1458 } 1459 1460 // FIXME: figure out how to safely handle things like 1461 // int foo(int x) { return 1 << (x & 255); } 1462 // int bar() { return foo(256); } 1463#if 0 1464 case ISD::SHL: 1465 case ISD::SRL: 1466 case ISD::SRA: 1467 if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG && 1468 cast<VTSDNode>(N2.getOperand(1))->getVT() != MVT::i1) 1469 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1470 else if (N2.getOpcode() == ISD::AND) 1471 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) { 1472 // If the and is only masking out bits that cannot effect the shift, 1473 // eliminate the and. 1474 unsigned NumBits = MVT::getSizeInBits(VT); 1475 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1476 return getNode(Opcode, VT, N1, N2.getOperand(0)); 1477 } 1478 break; 1479#endif 1480 } 1481 1482 // Memoize this node if possible. 1483 SDNode *N; 1484 if (Opcode != ISD::CALLSEQ_START && Opcode != ISD::CALLSEQ_END) { 1485 SDNode *&BON = BinaryOps[std::make_pair(Opcode, std::make_pair(N1, N2))]; 1486 if (BON) return SDOperand(BON, 0); 1487 1488 BON = N = new SDNode(Opcode, N1, N2); 1489 } else { 1490 N = new SDNode(Opcode, N1, N2); 1491 } 1492 1493 N->setValueTypes(VT); 1494 AllNodes.push_back(N); 1495 return SDOperand(N, 0); 1496} 1497 1498// setAdjCallChain - This method changes the token chain of an 1499// CALLSEQ_START/END node to be the specified operand. 1500void SDNode::setAdjCallChain(SDOperand N) { 1501 assert(N.getValueType() == MVT::Other); 1502 assert((getOpcode() == ISD::CALLSEQ_START || 1503 getOpcode() == ISD::CALLSEQ_END) && "Cannot adjust this node!"); 1504 1505 Operands[0].Val->removeUser(this); 1506 Operands[0] = N; 1507 N.Val->Uses.push_back(this); 1508} 1509 1510 1511 1512SDOperand SelectionDAG::getLoad(MVT::ValueType VT, 1513 SDOperand Chain, SDOperand Ptr, 1514 SDOperand SV) { 1515 SDNode *&N = Loads[std::make_pair(Ptr, std::make_pair(Chain, VT))]; 1516 if (N) return SDOperand(N, 0); 1517 N = new SDNode(ISD::LOAD, Chain, Ptr, SV); 1518 1519 // Loads have a token chain. 1520 N->setValueTypes(VT, MVT::Other); 1521 AllNodes.push_back(N); 1522 return SDOperand(N, 0); 1523} 1524 1525 1526SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT, 1527 SDOperand Chain, SDOperand Ptr, SDOperand SV, 1528 MVT::ValueType EVT) { 1529 std::vector<SDOperand> Ops; 1530 Ops.reserve(4); 1531 Ops.push_back(Chain); 1532 Ops.push_back(Ptr); 1533 Ops.push_back(SV); 1534 Ops.push_back(getValueType(EVT)); 1535 std::vector<MVT::ValueType> VTs; 1536 VTs.reserve(2); 1537 VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain. 1538 return getNode(Opcode, VTs, Ops); 1539} 1540 1541SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1542 SDOperand N1, SDOperand N2, SDOperand N3) { 1543 // Perform various simplifications. 1544 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1545 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1546 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1547 switch (Opcode) { 1548 case ISD::SETCC: { 1549 // Use SimplifySetCC to simplify SETCC's. 1550 SDOperand Simp = SimplifySetCC(VT, N1, N2, cast<CondCodeSDNode>(N3)->get()); 1551 if (Simp.Val) return Simp; 1552 break; 1553 } 1554 case ISD::SELECT: 1555 if (N1C) 1556 if (N1C->getValue()) 1557 return N2; // select true, X, Y -> X 1558 else 1559 return N3; // select false, X, Y -> Y 1560 1561 if (N2 == N3) return N2; // select C, X, X -> X 1562 1563 if (VT == MVT::i1) { // Boolean SELECT 1564 if (N2C) { 1565 if (N2C->getValue()) // select C, 1, X -> C | X 1566 return getNode(ISD::OR, VT, N1, N3); 1567 else // select C, 0, X -> ~C & X 1568 return getNode(ISD::AND, VT, 1569 getNode(ISD::XOR, N1.getValueType(), N1, 1570 getConstant(1, N1.getValueType())), N3); 1571 } else if (N3C) { 1572 if (N3C->getValue()) // select C, X, 1 -> ~C | X 1573 return getNode(ISD::OR, VT, 1574 getNode(ISD::XOR, N1.getValueType(), N1, 1575 getConstant(1, N1.getValueType())), N2); 1576 else // select C, X, 0 -> C & X 1577 return getNode(ISD::AND, VT, N1, N2); 1578 } 1579 1580 if (N1 == N2) // X ? X : Y --> X ? 1 : Y --> X | Y 1581 return getNode(ISD::OR, VT, N1, N3); 1582 if (N1 == N3) // X ? Y : X --> X ? Y : 0 --> X & Y 1583 return getNode(ISD::AND, VT, N1, N2); 1584 } 1585 if (N1.getOpcode() == ISD::SETCC) { 1586 SDOperand Simp = SimplifySelectCC(N1.getOperand(0), N1.getOperand(1), N2, 1587 N3, cast<CondCodeSDNode>(N1.getOperand(2))->get()); 1588 if (Simp.Val) return Simp; 1589 } 1590 break; 1591 case ISD::BRCOND: 1592 if (N2C) 1593 if (N2C->getValue()) // Unconditional branch 1594 return getNode(ISD::BR, MVT::Other, N1, N3); 1595 else 1596 return N1; // Never-taken branch 1597 break; 1598 } 1599 1600 std::vector<SDOperand> Ops; 1601 Ops.reserve(3); 1602 Ops.push_back(N1); 1603 Ops.push_back(N2); 1604 Ops.push_back(N3); 1605 1606 // Memoize nodes. 1607 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1608 if (N) return SDOperand(N, 0); 1609 1610 N = new SDNode(Opcode, N1, N2, N3); 1611 N->setValueTypes(VT); 1612 AllNodes.push_back(N); 1613 return SDOperand(N, 0); 1614} 1615 1616SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1617 SDOperand N1, SDOperand N2, SDOperand N3, 1618 SDOperand N4) { 1619 std::vector<SDOperand> Ops; 1620 Ops.reserve(4); 1621 Ops.push_back(N1); 1622 Ops.push_back(N2); 1623 Ops.push_back(N3); 1624 Ops.push_back(N4); 1625 return getNode(Opcode, VT, Ops); 1626} 1627 1628SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1629 SDOperand N1, SDOperand N2, SDOperand N3, 1630 SDOperand N4, SDOperand N5) { 1631 if (ISD::SELECT_CC == Opcode) { 1632 assert(N1.getValueType() == N2.getValueType() && 1633 "LHS and RHS of condition must have same type!"); 1634 assert(N3.getValueType() == N4.getValueType() && 1635 "True and False arms of SelectCC must have same type!"); 1636 assert(N3.getValueType() == VT && 1637 "select_cc node must be of same type as true and false value!"); 1638 SDOperand Simp = SimplifySelectCC(N1, N2, N3, N4, 1639 cast<CondCodeSDNode>(N5)->get()); 1640 if (Simp.Val) return Simp; 1641 } 1642 1643 std::vector<SDOperand> Ops; 1644 Ops.reserve(5); 1645 Ops.push_back(N1); 1646 Ops.push_back(N2); 1647 Ops.push_back(N3); 1648 Ops.push_back(N4); 1649 Ops.push_back(N5); 1650 return getNode(Opcode, VT, Ops); 1651} 1652 1653 1654SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) { 1655 assert((!V || isa<PointerType>(V->getType())) && 1656 "SrcValue is not a pointer?"); 1657 SDNode *&N = ValueNodes[std::make_pair(V, Offset)]; 1658 if (N) return SDOperand(N, 0); 1659 1660 N = new SrcValueSDNode(V, Offset); 1661 AllNodes.push_back(N); 1662 return SDOperand(N, 0); 1663} 1664 1665SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, 1666 std::vector<SDOperand> &Ops) { 1667 switch (Ops.size()) { 1668 case 0: return getNode(Opcode, VT); 1669 case 1: return getNode(Opcode, VT, Ops[0]); 1670 case 2: return getNode(Opcode, VT, Ops[0], Ops[1]); 1671 case 3: return getNode(Opcode, VT, Ops[0], Ops[1], Ops[2]); 1672 default: break; 1673 } 1674 1675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Ops[1].Val); 1676 switch (Opcode) { 1677 default: break; 1678 case ISD::BRCONDTWOWAY: 1679 if (N1C) 1680 if (N1C->getValue()) // Unconditional branch to true dest. 1681 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[2]); 1682 else // Unconditional branch to false dest. 1683 return getNode(ISD::BR, MVT::Other, Ops[0], Ops[3]); 1684 break; 1685 case ISD::BRTWOWAY_CC: 1686 assert(Ops.size() == 6 && "BRTWOWAY_CC takes 6 operands!"); 1687 assert(Ops[2].getValueType() == Ops[3].getValueType() && 1688 "LHS and RHS of comparison must have same type!"); 1689 break; 1690 case ISD::TRUNCSTORE: { 1691 assert(Ops.size() == 5 && "TRUNCSTORE takes 5 operands!"); 1692 MVT::ValueType EVT = cast<VTSDNode>(Ops[4])->getVT(); 1693#if 0 // FIXME: If the target supports EVT natively, convert to a truncate/store 1694 // If this is a truncating store of a constant, convert to the desired type 1695 // and store it instead. 1696 if (isa<Constant>(Ops[0])) { 1697 SDOperand Op = getNode(ISD::TRUNCATE, EVT, N1); 1698 if (isa<Constant>(Op)) 1699 N1 = Op; 1700 } 1701 // Also for ConstantFP? 1702#endif 1703 if (Ops[0].getValueType() == EVT) // Normal store? 1704 return getNode(ISD::STORE, VT, Ops[0], Ops[1], Ops[2], Ops[3]); 1705 assert(Ops[1].getValueType() > EVT && "Not a truncation?"); 1706 assert(MVT::isInteger(Ops[1].getValueType()) == MVT::isInteger(EVT) && 1707 "Can't do FP-INT conversion!"); 1708 break; 1709 } 1710 } 1711 1712 // Memoize nodes. 1713 SDNode *&N = OneResultNodes[std::make_pair(Opcode, std::make_pair(VT, Ops))]; 1714 if (N) return SDOperand(N, 0); 1715 N = new SDNode(Opcode, Ops); 1716 N->setValueTypes(VT); 1717 AllNodes.push_back(N); 1718 return SDOperand(N, 0); 1719} 1720 1721SDOperand SelectionDAG::getNode(unsigned Opcode, 1722 std::vector<MVT::ValueType> &ResultTys, 1723 std::vector<SDOperand> &Ops) { 1724 if (ResultTys.size() == 1) 1725 return getNode(Opcode, ResultTys[0], Ops); 1726 1727 switch (Opcode) { 1728 case ISD::EXTLOAD: 1729 case ISD::SEXTLOAD: 1730 case ISD::ZEXTLOAD: { 1731 MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT(); 1732 assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!"); 1733 // If they are asking for an extending load from/to the same thing, return a 1734 // normal load. 1735 if (ResultTys[0] == EVT) 1736 return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]); 1737 assert(EVT < ResultTys[0] && 1738 "Should only be an extending load, not truncating!"); 1739 assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) && 1740 "Cannot sign/zero extend a FP load!"); 1741 assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) && 1742 "Cannot convert from FP to Int or Int -> FP!"); 1743 break; 1744 } 1745 1746 // FIXME: figure out how to safely handle things like 1747 // int foo(int x) { return 1 << (x & 255); } 1748 // int bar() { return foo(256); } 1749#if 0 1750 case ISD::SRA_PARTS: 1751 case ISD::SRL_PARTS: 1752 case ISD::SHL_PARTS: 1753 if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && 1754 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) 1755 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1756 else if (N3.getOpcode() == ISD::AND) 1757 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { 1758 // If the and is only masking out bits that cannot effect the shift, 1759 // eliminate the and. 1760 unsigned NumBits = MVT::getSizeInBits(VT)*2; 1761 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1) 1762 return getNode(Opcode, VT, N1, N2, N3.getOperand(0)); 1763 } 1764 break; 1765#endif 1766 } 1767 1768 // Memoize the node. 1769 SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys, 1770 Ops))]; 1771 if (N) return SDOperand(N, 0); 1772 N = new SDNode(Opcode, Ops); 1773 N->setValueTypes(ResultTys); 1774 AllNodes.push_back(N); 1775 return SDOperand(N, 0); 1776} 1777 1778 1779/// SelectNodeTo - These are used for target selectors to *mutate* the 1780/// specified node to have the specified return type, Target opcode, and 1781/// operands. Note that target opcodes are stored as 1782/// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. 1783void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1784 unsigned TargetOpc, SDOperand Op1) { 1785 RemoveNodeFromCSEMaps(N); 1786 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1787 N->setValueTypes(VT); 1788 N->setOperands(Op1); 1789} 1790void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1791 unsigned TargetOpc, SDOperand Op1, 1792 SDOperand Op2) { 1793 RemoveNodeFromCSEMaps(N); 1794 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1795 N->setValueTypes(VT); 1796 N->setOperands(Op1, Op2); 1797} 1798void SelectionDAG::SelectNodeTo(SDNode *N, MVT::ValueType VT, 1799 unsigned TargetOpc, SDOperand Op1, 1800 SDOperand Op2, SDOperand Op3) { 1801 RemoveNodeFromCSEMaps(N); 1802 N->MorphNodeTo(ISD::BUILTIN_OP_END+TargetOpc); 1803 N->setValueTypes(VT); 1804 N->setOperands(Op1, Op2, Op3); 1805} 1806 1807/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead. 1808/// This can cause recursive merging of nodes in the DAG. 1809/// 1810void SelectionDAG::ReplaceAllUsesWith(SDNode *From, SDNode *To) { 1811 assert(From != To && "Cannot replace uses of with self"); 1812 while (!From->use_empty()) { 1813 // Process users until they are all gone. 1814 SDNode *U = *From->use_begin(); 1815 1816 // This node is about to morph, remove its old self from the CSE maps. 1817 RemoveNodeFromCSEMaps(U); 1818 1819 for (unsigned i = 0, e = U->getNumOperands(); i != e; ++i) 1820 if (U->getOperand(i).Val == From) { 1821 assert(From->getValueType(U->getOperand(i).ResNo) == 1822 To->getValueType(U->getOperand(i).ResNo)); 1823 From->removeUser(U); 1824 U->Operands[i].Val = To; 1825 To->addUser(U); 1826 } 1827 1828 // Now that we have modified U, add it back to the CSE maps. If it already 1829 // exists there, recursively merge the results together. 1830 if (SDNode *Existing = AddNonLeafNodeToCSEMaps(U)) 1831 ReplaceAllUsesWith(U, Existing); 1832 // U is now dead. 1833 } 1834} 1835 1836 1837 1838/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the 1839/// indicated value. This method ignores uses of other values defined by this 1840/// operation. 1841bool SDNode::hasNUsesOfValue(unsigned NUses, unsigned Value) { 1842 assert(Value < getNumValues() && "Bad value!"); 1843 1844 // If there is only one value, this is easy. 1845 if (getNumValues() == 1) 1846 return use_size() == NUses; 1847 if (Uses.size() < NUses) return false; 1848 1849 SDOperand TheValue(this, Value); 1850 1851 std::set<SDNode*> UsersHandled; 1852 1853 for (std::vector<SDNode*>::iterator UI = Uses.begin(), E = Uses.end(); 1854 UI != E; ++UI) { 1855 SDNode *User = *UI; 1856 if (User->getNumOperands() == 1 || 1857 UsersHandled.insert(User).second) // First time we've seen this? 1858 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1859 if (User->getOperand(i) == TheValue) { 1860 if (NUses == 0) 1861 return false; // too many uses 1862 --NUses; 1863 } 1864 } 1865 1866 // Found exactly the right number of uses? 1867 return NUses == 0; 1868} 1869 1870 1871const char *SDNode::getOperationName(const SelectionDAG *G) const { 1872 switch (getOpcode()) { 1873 default: 1874 if (getOpcode() < ISD::BUILTIN_OP_END) 1875 return "<<Unknown DAG Node>>"; 1876 else { 1877 if (G) 1878 if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo()) 1879 return TII->getName(getOpcode()-ISD::BUILTIN_OP_END); 1880 return "<<Unknown Target Node>>"; 1881 } 1882 1883 case ISD::PCMARKER: return "PCMarker"; 1884 case ISD::SRCVALUE: return "SrcValue"; 1885 case ISD::EntryToken: return "EntryToken"; 1886 case ISD::TokenFactor: return "TokenFactor"; 1887 case ISD::Constant: return "Constant"; 1888 case ISD::TargetConstant: return "TargetConstant"; 1889 case ISD::ConstantFP: return "ConstantFP"; 1890 case ISD::GlobalAddress: return "GlobalAddress"; 1891 case ISD::FrameIndex: return "FrameIndex"; 1892 case ISD::BasicBlock: return "BasicBlock"; 1893 case ISD::Register: return "Register"; 1894 case ISD::ExternalSymbol: return "ExternalSymbol"; 1895 case ISD::ConstantPool: return "ConstantPoolIndex"; 1896 case ISD::CopyToReg: return "CopyToReg"; 1897 case ISD::CopyFromReg: return "CopyFromReg"; 1898 case ISD::ImplicitDef: return "ImplicitDef"; 1899 case ISD::UNDEF: return "undef"; 1900 1901 // Unary operators 1902 case ISD::FABS: return "fabs"; 1903 case ISD::FNEG: return "fneg"; 1904 case ISD::FSQRT: return "fsqrt"; 1905 case ISD::FSIN: return "fsin"; 1906 case ISD::FCOS: return "fcos"; 1907 1908 // Binary operators 1909 case ISD::ADD: return "add"; 1910 case ISD::SUB: return "sub"; 1911 case ISD::MUL: return "mul"; 1912 case ISD::MULHU: return "mulhu"; 1913 case ISD::MULHS: return "mulhs"; 1914 case ISD::SDIV: return "sdiv"; 1915 case ISD::UDIV: return "udiv"; 1916 case ISD::SREM: return "srem"; 1917 case ISD::UREM: return "urem"; 1918 case ISD::AND: return "and"; 1919 case ISD::OR: return "or"; 1920 case ISD::XOR: return "xor"; 1921 case ISD::SHL: return "shl"; 1922 case ISD::SRA: return "sra"; 1923 case ISD::SRL: return "srl"; 1924 1925 case ISD::SETCC: return "setcc"; 1926 case ISD::SELECT: return "select"; 1927 case ISD::SELECT_CC: return "select_cc"; 1928 case ISD::ADD_PARTS: return "add_parts"; 1929 case ISD::SUB_PARTS: return "sub_parts"; 1930 case ISD::SHL_PARTS: return "shl_parts"; 1931 case ISD::SRA_PARTS: return "sra_parts"; 1932 case ISD::SRL_PARTS: return "srl_parts"; 1933 1934 // Conversion operators. 1935 case ISD::SIGN_EXTEND: return "sign_extend"; 1936 case ISD::ZERO_EXTEND: return "zero_extend"; 1937 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; 1938 case ISD::TRUNCATE: return "truncate"; 1939 case ISD::FP_ROUND: return "fp_round"; 1940 case ISD::FP_ROUND_INREG: return "fp_round_inreg"; 1941 case ISD::FP_EXTEND: return "fp_extend"; 1942 1943 case ISD::SINT_TO_FP: return "sint_to_fp"; 1944 case ISD::UINT_TO_FP: return "uint_to_fp"; 1945 case ISD::FP_TO_SINT: return "fp_to_sint"; 1946 case ISD::FP_TO_UINT: return "fp_to_uint"; 1947 1948 // Control flow instructions 1949 case ISD::BR: return "br"; 1950 case ISD::BRCOND: return "brcond"; 1951 case ISD::BRCONDTWOWAY: return "brcondtwoway"; 1952 case ISD::BR_CC: return "br_cc"; 1953 case ISD::BRTWOWAY_CC: return "brtwoway_cc"; 1954 case ISD::RET: return "ret"; 1955 case ISD::CALL: return "call"; 1956 case ISD::TAILCALL:return "tailcall"; 1957 case ISD::CALLSEQ_START: return "callseq_start"; 1958 case ISD::CALLSEQ_END: return "callseq_end"; 1959 1960 // Other operators 1961 case ISD::LOAD: return "load"; 1962 case ISD::STORE: return "store"; 1963 case ISD::EXTLOAD: return "extload"; 1964 case ISD::SEXTLOAD: return "sextload"; 1965 case ISD::ZEXTLOAD: return "zextload"; 1966 case ISD::TRUNCSTORE: return "truncstore"; 1967 1968 case ISD::DYNAMIC_STACKALLOC: return "dynamic_stackalloc"; 1969 case ISD::EXTRACT_ELEMENT: return "extract_element"; 1970 case ISD::BUILD_PAIR: return "build_pair"; 1971 case ISD::MEMSET: return "memset"; 1972 case ISD::MEMCPY: return "memcpy"; 1973 case ISD::MEMMOVE: return "memmove"; 1974 1975 // Bit counting 1976 case ISD::CTPOP: return "ctpop"; 1977 case ISD::CTTZ: return "cttz"; 1978 case ISD::CTLZ: return "ctlz"; 1979 1980 // IO Intrinsics 1981 case ISD::READPORT: return "readport"; 1982 case ISD::WRITEPORT: return "writeport"; 1983 case ISD::READIO: return "readio"; 1984 case ISD::WRITEIO: return "writeio"; 1985 1986 case ISD::CONDCODE: 1987 switch (cast<CondCodeSDNode>(this)->get()) { 1988 default: assert(0 && "Unknown setcc condition!"); 1989 case ISD::SETOEQ: return "setoeq"; 1990 case ISD::SETOGT: return "setogt"; 1991 case ISD::SETOGE: return "setoge"; 1992 case ISD::SETOLT: return "setolt"; 1993 case ISD::SETOLE: return "setole"; 1994 case ISD::SETONE: return "setone"; 1995 1996 case ISD::SETO: return "seto"; 1997 case ISD::SETUO: return "setuo"; 1998 case ISD::SETUEQ: return "setue"; 1999 case ISD::SETUGT: return "setugt"; 2000 case ISD::SETUGE: return "setuge"; 2001 case ISD::SETULT: return "setult"; 2002 case ISD::SETULE: return "setule"; 2003 case ISD::SETUNE: return "setune"; 2004 2005 case ISD::SETEQ: return "seteq"; 2006 case ISD::SETGT: return "setgt"; 2007 case ISD::SETGE: return "setge"; 2008 case ISD::SETLT: return "setlt"; 2009 case ISD::SETLE: return "setle"; 2010 case ISD::SETNE: return "setne"; 2011 } 2012 } 2013} 2014 2015void SDNode::dump() const { dump(0); } 2016void SDNode::dump(const SelectionDAG *G) const { 2017 std::cerr << (void*)this << ": "; 2018 2019 for (unsigned i = 0, e = getNumValues(); i != e; ++i) { 2020 if (i) std::cerr << ","; 2021 if (getValueType(i) == MVT::Other) 2022 std::cerr << "ch"; 2023 else 2024 std::cerr << MVT::getValueTypeString(getValueType(i)); 2025 } 2026 std::cerr << " = " << getOperationName(G); 2027 2028 std::cerr << " "; 2029 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 2030 if (i) std::cerr << ", "; 2031 std::cerr << (void*)getOperand(i).Val; 2032 if (unsigned RN = getOperand(i).ResNo) 2033 std::cerr << ":" << RN; 2034 } 2035 2036 if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) { 2037 std::cerr << "<" << CSDN->getValue() << ">"; 2038 } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) { 2039 std::cerr << "<" << CSDN->getValue() << ">"; 2040 } else if (const GlobalAddressSDNode *GADN = 2041 dyn_cast<GlobalAddressSDNode>(this)) { 2042 std::cerr << "<"; 2043 WriteAsOperand(std::cerr, GADN->getGlobal()) << ">"; 2044 } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) { 2045 std::cerr << "<" << FIDN->getIndex() << ">"; 2046 } else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){ 2047 std::cerr << "<" << CP->getIndex() << ">"; 2048 } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) { 2049 std::cerr << "<"; 2050 const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock(); 2051 if (LBB) 2052 std::cerr << LBB->getName() << " "; 2053 std::cerr << (const void*)BBDN->getBasicBlock() << ">"; 2054 } else if (const RegisterSDNode *C2V = dyn_cast<RegisterSDNode>(this)) { 2055 std::cerr << " #" << C2V->getReg(); 2056 } else if (const ExternalSymbolSDNode *ES = 2057 dyn_cast<ExternalSymbolSDNode>(this)) { 2058 std::cerr << "'" << ES->getSymbol() << "'"; 2059 } else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) { 2060 if (M->getValue()) 2061 std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">"; 2062 else 2063 std::cerr << "<null:" << M->getOffset() << ">"; 2064 } 2065} 2066 2067static void DumpNodes(SDNode *N, unsigned indent, const SelectionDAG *G) { 2068 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 2069 if (N->getOperand(i).Val->hasOneUse()) 2070 DumpNodes(N->getOperand(i).Val, indent+2, G); 2071 else 2072 std::cerr << "\n" << std::string(indent+2, ' ') 2073 << (void*)N->getOperand(i).Val << ": <multiple use>"; 2074 2075 2076 std::cerr << "\n" << std::string(indent, ' '); 2077 N->dump(G); 2078} 2079 2080void SelectionDAG::dump() const { 2081 std::cerr << "SelectionDAG has " << AllNodes.size() << " nodes:"; 2082 std::vector<SDNode*> Nodes(AllNodes); 2083 std::sort(Nodes.begin(), Nodes.end()); 2084 2085 for (unsigned i = 0, e = Nodes.size(); i != e; ++i) { 2086 if (!Nodes[i]->hasOneUse() && Nodes[i] != getRoot().Val) 2087 DumpNodes(Nodes[i], 2, this); 2088 } 2089 2090 DumpNodes(getRoot().Val, 2, this); 2091 2092 std::cerr << "\n\n"; 2093} 2094 2095